NSC DM54LS161AW-883, DM54LS161AW-MLS, DM54LS161AJ-MLS Datasheet

May 1992

54LS161A/DM54LS161A/DM74LS161A,

54LS163A/DM54LS163A/DM74LS163A Synchronous 4-Bit Binary Counters

General Description

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The LS161A and LS163A are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform.

These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input. The clear function for the LS161A is asynchronous; and a low level at the clear input sets all four of the flip-flop outputs low, regardless of the levels of clock, load, or enable inputs. The clear function for the LS163A is synchronous; and a low level at the clear inputs sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all low outputs.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional

gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output.

Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-lev- el output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs may occur, regardless of the logic level of the clock.

These counters feature a fully independent clock circuit. Changes made to control inputs (enable P or T or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable set-up and hold times.

Features

YSynchronously programmable

YInternal look-ahead for fast counting

YCarry output for n-bit cascading

YSynchronous counting

YLoad control line

YDiode-clamped inputs

YTypical propagation time, clock to Q output 14 ns

YTypical clock frequency 32 MHz

YTypical power dissipation 93 mW

YAlternate Military/Aerospace device (54LS161, 54LS163) is available. Contact a National Semiconductor Sales Office/Distributor for specificaitons.

Connection Diagram

Dual-In-Line Package

Order Numbers 54LS161ADMQB, 54LS161AFMQB, 54LS161ALMQB, 54LS163ADMQB, 54LS163AFMQB, 54LS163ALMQB, DM54LS161AJ, DM54LS161AW, DM54LS163AJ, DM54LS163AW, DM74LS161AM, DM74LS161AN, DM74LS163AM or DM74LS163AN See NS Package Number E20A, J16A,

M16A, N16E or W16A

TL/F/6397 ± 1

Synchronous 54LS163A/DM54LS163A/DM74LS163A 54LS161A/DM54LS161A/DM74LS161A, Counters Binary Bit-4

C1995 National Semiconductor Corporation

TL/F/6397

RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage	7V
Input Voltage	7V
Operating Free Air Temperature Range	b55§C to a125§C
DM54LS and 54LS
DM74LS	0§C to a70§C
Storage Temperature Range	b65§C to a150§C

Note: The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings. The ``Recommended Operating Conditions'' table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol		Parameter			DM54LS161A					DM74LS161A				Units
				Min		Nom		Max	Min		Nom		Max
VCC	Supply Voltage			4.5		5		5.5	4.75		5		5.25	V
VIH	High Level Input Voltage			2					2					V
VIL	Low Level Input Voltage							0.7					0.8	V
IOH	High Level Output Current							b0.4					b0.4	mA
IOL	Low Level Output Current							4					8	mA
fCLK	Clock Frequency (Note 1)			0				25	0				25	MHz
	Clock Frequency (Note 2)			0				20	0				20	MHz
tW	Pulse Width		Clock	20		6			20		6			ns
	(Note 1)		Clear	20		9			20		9
	Pulse Width		Clock	25					25					ns
	(Note 2)
			Clear	25					25
tSU	Setup Time		Data	20		8			20		8
	(Note 1)		Enable P	25		17			25		17			ns
			Load	25		15			25		15
	Setup Time		Data	20					20
	(Note 2)
			Enable P	30					30					ns
			Load	30					30
tH	Hold Time		Data	0		b3			0		b3			ns
	(Note 1)		Others	0		b3			0		b3
	Hold Time		Data	5					5					ns
	(Note 2)
			Others	5					5
tREL	Clear Release Time (Note 1)			20					20					ns
	Clear Release Time (Note 2)			25					25					ns
TA	Free Air Operating Temperature			b55				125	0				70	§C

Note 1: CL e 15 pF, RL e 2 kX, TA e 25§C and VCC e 5.5V.

Note 2: CL e 50 pF, RL e 2 kX, TA e 25§C and VCC e 5.5V.

2

'LS161 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Symbol	Parameter	Conditions		Min	Typ	Max	Units
					(Note 1)
VI	Input Clamp Voltage	VCC e Min, II e b18 mA				b1.5	V
VOH	High Level Output	VCC e Min, IOH e Max	DM54	2.5	3.4		V
	Voltage	VIL e Max, VIH e Min	DM74	2.7	3.4
VOL	Low Level Output	VCC e Min, IOL e Max	DM54		0.25	0.4
	Voltage	VIL e Max, VIH e Min	DM74		0.35	0.5	V
		IOL e 4 mA, VCC e Min	DM74		0.25	0.4
II	Input Current @ Max	VCC e Max	Enable T			0.2
	Input Voltage	VI e 7V	Clock			0.2
							mA
			Load			0.2
			Others			0.1
IIH	High Level Input	VCC e Max	Enable T			40
	Current	VI e 2.7V	Clock			40
							mA
			Load			40
			Others			20
IIL	Low Level Input	VCC e Max	Enable T			b0.8
	Current	VI e 0.4V	Clock			b0.8
							mA
			Load			b0.8
			Others			b0.4
IOS	Short Circuit	VCC e Max	DM54	b20		b100	mA
	Output Current	(Note 2)	DM74	b20		b100
ICCH	Supply Current with	VCC e Max			18	31	mA
	Outputs High	(Note 3)
ICCL	Supply Current with	VCC e Max			19	32	mA
	Outputs Low	(Note 4)

Note 1: All typicals are at VCC e 5V, TA e 25§C.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open.

Note 4: ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open.

'LS161 Switching Characteristics

at VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load)

			From (Input)		RL e 2 kX
	Symbol	Parameter		CL e 15 pF		CL e 50 pF		Units
			To (Output)
				Min	Max	Min	Max
	fMAX	Maximum Clock Frequency		25		20		MHz
	tPLH	Propagation Delay Time	Clock to		25		30	ns
		Low to High Level Output	Ripple Carry
	tPHL	Propagation Delay Time	Clock to		30		38	ns
		High to Low Level Output	Ripple Carry
	tPLH	Propagation Delay Time	Clock to Any Q		22		27	ns
		Low to High Level Output	(Load High)
	tPHL	Propagation Delay Time	Clock to Any Q		27		38	ns
		High to Low Level Output	(Load High)

3

'LS161 Switching Characteristics

at VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load) (Continued)

			From (Input)		RL e 2 kX
	Symbol	Parameter		CL e 15 pF		CL e 50 pF		Units
			To (Output)
				Min	Max	Min	Max
	tPLH	Propagation Delay Time	Clock to Any Q		24		30	ns
		Low to High Level Output	(Load Low)
	tPHL	Propagation Delay Time	Clock to Any Q		27		38	ns
		High to Low Level Output	(Load Low)
	tPLH	Propagation Delay Time	Enable T to		14		27	ns
		Low to High Level Output	Ripple Carry
	tPHL	Propagation Delay Time	Enable T to		15		27	ns
		High to Low Level Output	Ripple Carry
	tPHL	Propagation Delay Time	Clear to		28		45	ns
		High to Low Level Output	Any Q

Recommended Operating Conditions

Symbol		Parameter			DM54LS163A					DM74LS163A				Units
				Min		Nom		Max	Min		Nom		Max
VCC	Supply Voltage			4.5		5		5.5	4.75		5		5.25	V
VIH	High Level Input Voltage			2					2					V
VIL	Low Level Input Voltage							0.7					0.8	V
IOH	High Level Output Current							b0.4					b0.4	mA
IOL	Low Level Output Current							4					8	mA
fCLK	Clock Frequency (Note 1)			0				25	0				25	MHz
	Clock Frequency (Note 2)			0				20	0				20	MHz
tW	Pulse Width		Clock	20		6			20		6			ns
	(Note 1)		Clear	20		9			20		9
	Pulse Width		Clock	25					25					ns
	(Note 2)		Clear	25					25
tSU	Setup Time		Data	20		8			20		8
	(Note 1)		Enable P	25		17			25		17			ns
			Load	25		15			25		15
	Setup Time		Data	20					20
	(Note 2)		Enable P	30					30					ns
			Load	30					30
tH	Hold Time		Data	0		b3			0		b3			ns
	(Note 1)		Others	0		b3			0		b3
	Hold Time		Data	5					5					ns
	(Note 2)		Others	5					5
tREL	Clear Release Time (Note 1)			20					20					ns
	Clear Release Time (Note 2)			25					25					ns
TA	Free Air Operating Temperature			b55				125	0				70	§C

Note 1: CL e 15 pF, RL e 2 kX, TA e 25§C and VCC e 5V.

Note 2: CL e 50 pF, RL e 2 kX, TA e 25§C and VCC e 5V.

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