NSC COP8CCE9IMT9, COP8CCE9IMT7, COP8CCE9HVA9, COP8CCE9HVA7, COP8CCE9HLQ9 Datasheet

PRELIMINARY

April 2002

COP8CBE9/CCE9/CDE9

8-Bit CMOS Flash Microcontroller with 8k Memory, Virtual EEPROM, 10-Bit A/D and Brownout Reset

General Description

The COP8CBE9/CCE9/CDE9 Flash microcontrollers are highly integrated COP8™ Feature core devices, with 8k Flash memory and advanced features including Virtual EEPROM, A/D, High Speed Timers, USART, and Brownout Reset. This single-chip CMOS device is suited for applica-

Devices included in this datasheet:

tions requiring a full featured, in-system reprogrammable controller with large memory and low EMI. The same device is used for development, pre-production and volume production with a range of COP8 software and hardware development tools.

	Device	Flash Program	RAM	Brownout	I/O	Packages	Temperature
		Memory (bytes)	(bytes)	Voltage	Pins
	COP8CBE9	8k	256	2.7V to 2.9V	37,39	44 LLP, 44PLCC,	0ÊC to +70ÊC
						48 TSSOP
	COP8CCE9	8k	256	4.17V to 4.5V	37,39	44 LLP, 44PLCC,	0ÊC to +70ÊC
						48 TSSOP	−40ÊC to +125ÊC
						44 LLP,	0ÊC to +70ÊC
	COP8CDE9	8k	256	No Brownout	37,39	44 PLCC,
							−40ÊC to +125ÊC
						48 TSSOP

Features

KEY FEATURES

n8k bytes Flash Program Memory with Security Feature

nVirtual EEPROM using Flash Program Memory

n256byte volatile RAM

n10-bit Successive Approximation Analog to Digital Converter (up to 16 channels)

n100% Precise Analog Emulation

nUSART with onchip baud generator

n2.7V ± 5.5V In-System Programmability of Flash

nHigh endurance -100k Read/Write Cycles

nSuperior Data Retention - 100 years

nDual Clock Operation with HALT/IDLE Power Save Modes

nTwo 16-bit timers:

ÐTimer T2 can operate at high speed (50 ns resolution)

ÐProcessor Independent PWM mode

ÐExternal Event counter mode

ÐInput Capture mode

nBrown-out Reset (COP8CBE9/CCE9)

nHigh Current I/Os

ÐB0± B3: 10 mA @ 0.3V

ÐAll others: 10 mA @ 1.0V

OTHER FEATURES

nSingle supply operation:

Ð2.7V±5.5V (0ÊC to +70ÊC)

Ð4.5V±5.5V (−40ÊC to +125ÊC)

nQuiet Design (low radiated emissions)

nMulti-Input Wake-up with optional interrupts

nMICROWIRE/PLUS (Serial Peripheral Interface Compatible)

nClock Doubler for 20 MHz operation from 10 MHz Oscillator, with 0.5 µs Instruction Cycle

nEleven multi-source vectored interrupts servicing:

ÐExternal Interrupt

ÐUSART (2)

ÐIdle Timer T0

ÐTwo Timers (each with 2 interrupts)

ÐMICROWIRE/PLUS Serial peripheral interface

ÐMulti-Input Wake-up

ÐSoftware Trap

nIdle Timer with programmable interrupt interval

n8-bit Stack Pointer SP (stack in RAM)

nTwo 8-bit Register Indirect Data Memory Pointers

nTrue bit manipulation

nWATCHDOG and Clock Monitor logic

nSoftware selectable I/O options

ÐTRI-STATE Output/High Impedance Input

ÐPush-Pull Output

ÐWeak Pull Up Input

nSchmitt trigger inputs on I/O ports

nTemperature range: 0ÊC to +70ÊC and ±40ÊC to +125ÊC (COP8CCE9/CDE9)

nPackaging: 44 PLCC, 44 LLP and 48 TSSOP

COP8™ is a trademark of National Semiconductor Corporation.

and A/D Bit-10 EEPROM,	8 COP8CBE9/CCE9/CDE9
Brownout	CMOS Bit-
Reset	Flash
	Virtual Memory, 8k with Microcontroller Based

© 2002 National Semiconductor Corporation

DS200225

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COP8CBE9/CCE9/CDE9

Block Diagram

						20022563
Ordering Information
		Part Numbering Scheme
COP8	CB	E	9	H	VA	8
	Family and Feature Set	Program	Program		Package
		Memory	Memory	No. Of Pins		Temperature
	Indicator				Type
		Size	Type
	CB = Low Brownout Voltage	E = 8k	9 = Flash	H = 44 Pin	LQ = LLP	7 = -40 to +125ÊC
	CC = High Brownout Voltage			I = 48 Pin	MT = TSSOP	9 = 0 to +70ÊC
	CD = No Brownout				VA = PLCC

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Connection Diagrams

20022564

Top View

Plastic Chip Package

See NS Package Number V44A

20022559

Top View

TSSOP Package

See NS Package Number MTD48

20022555

Top View

LLP Package

See NS Package Number LQA44A

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COP8CBE9/CCE9/CDE9

Pinouts for 44and 48-Pin Packages

					In System					48-Pin
	Port		Type	Alt. Function	Emulation			44-Pin LLP	44-Pin PLCC
										TSSOP
						Mode
L0			I/O	MIWU or Low Speed OSC In				16	11	11
L1			I/O	MIWU or CKX or Low Speed OSC Out				17	12	12
L2			I/O	MIWU or TDX				18	13	13
L3			I/O	MIWU or RDX				19	14	14
L4			I/O	MIWU or T2A				20	15	15
L5			I/O	MIWU or T2B				21	16	16
L6			I/O	MIWU				22	17	17
L7			I/O	MIWU				23	18	18
G0			I/O	INT		Input		7	2	2
G1			I/O	WDOUTa		POUT		8	3	3
	G2		I/O	T1B		Output		9	4	4
	G3		I/O	T1A		Clock		10	5	5
	G4		I/O	SO				11	6	6
	G5		I/O	SK				12	7	7
	G6		I	SI				13	8	8
	G7		I	CKO				14	9	9
	H0		I/O					42	37	41
	H1		I/O					43	38	42
	H2		I/O					44	39	43
	H3		I/O					1	40	44
	H4		I/O					2	41	45
	H5		I/O					3	42	46
	H6		I/O					4	43	47
	H7		I/O					5	44	48
	A0		I/O	ADCH0						33
	A1		I/O	ADCH1						34
	A2		I/O	ADCH2				36	31	35
	A3		I/O	ADCH3				37	32	36
	A4		I/O	ADCH4				38	33	37
	A5		I/O	ADCH5				39	34	38
	A6		I/O	ADCH6				40	35	39
	A7		I/O	ADCH7				41	36	40
	B0		I/O	ADCH8				24	19	19
	B1		I/O	ADCH9				25	20	20
	B2		I/O	ADCH10				26	21	21
	B3		I/O	ADCH11				27	22	22
	B4		I/O	ADCH12				28	23	23
	B5		I/O	ADCH13 or A/D MUX OUT				29	24	24
	B6		I/O	ADCH14 or A/D MUX OUT				30	25	25
	B7		I/O	ADCH15 or A/DIN				31	26	26
	DVCC					VCC		35	30	32
	DGND					GND		32	27	27
	AVCC							34	29	31
	AGND							33	28	28
	CKI		I					15	10	10
			I					6	1	1
	RESET					RESET

a. G1 operation as WDOUT is controlled by Option Register bit 2.

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1.0General Description

1.1EMI REDUCTION

The COP8CBE9/CCE9/CDE9 devices incorporate circuitry that guards against electromagnetic interference - an increasing problem in today's microcontroller board designs. National's patented EMI reduction technology offers low EMI clock circuitry, gradual turn-on output drivers (GTOs) and internal Icc smoothing filters, to help circumvent many of the EMI issues influencing embedded control designs. National has achieved 15 dB±20 dB reduction in EMI transmissions when designs have incorporated its patented EMI reducing circuitry.

1.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM

The device includes a program in a boot ROM that provides the capability, through the MICROWIRE/PLUS serial interface, to erase, program and read the contents of the Flash memory.

Additional routines are included in the boot ROM, which can be called by the user program, to enable the user to customize in system software update capability if MICROWIRE/ PLUS is not desired.

Additional functions will copy blocks of data between the RAM and the Flash Memory. These functions provide a virtual EEPROM capability by allowing the user to emulate a variable amount of EEPROM by initializing nonvolatile variables from the Flash Memory and occasionally restoring these variables to the Flash Memory.

The contents of the boot ROM have been defined by National. Execution of code from the boot ROM is dependent on the state of the FLEX bit in the Option Register on exit from RESET. If the FLEX bit is a zero, the Flash Memory is assumed to be empty and execution from the boot ROM begins. For further information on the FLEX bit, refer to Section 4.5, Option Register.

1.3 DUAL CLOCK AND CLOCK DOUBLER

The device includes a versatile clocking system and two oscillator circuits designed to drive a crystal or ceramic resonator. The primary oscillator operates at high speed up to 10 MHz. The secondary oscillator is optimized for operation at 32.768 kHz.

The user can, through specified transition sequences (please refer to 7.0 Power Saving Features), switch execution between the high speed and low speed oscillators. The unused oscillator can then be turned off to minimize power dissipation. If the low speed oscillator is not used, the pins are available as general purpose bidirectional ports.

The operation of the CPU will use a clock at twice the frequency of the selected oscillator (up to 20 MHz for high speed operation and 65.536 kHz for low speed operation). This doubled clock will be referred to in this document as `MCLK'. The frequency of the selected oscillator will be referred to as CKI. Instruction execution occurs at one tenth the selected MCLK rate.

1.4 TRUE IN-SYSTEM EMULATION

On-chip emulation capability has been added which allows the user to perform true in-system emulation using final production boards and devices. This simplifies testing and evaluation of software in real environmental conditions. The user, merely by providing for a standard connector which can

be bypassed by jumpers on the final application board, can provide for software and hardware debugging using actual production units.

1.5 ARCHITECTURE

The COP8 family is based on a modified Harvard architecture, which allows data tables to be accessed directly from program memory. This is very important with modern microcontroller-based applications, since program memory is usually ROM or EPROM, while data memory is usually RAM. Consequently constant data tables need to be contained in non-volatile memory, so they are not lost when the microcontroller is powered down. In a modified Harvard architecture, instruction fetch and memory data transfers can be overlapped with a two stage pipeline, which allows the next instruction to be fetched from program memory while the current instruction is being executed using data memory. This is not possible with a Von Neumann single-address bus architecture.

The COP8 family supports a software stack scheme that allows the user to incorporate many subroutine calls. This capability is important when using High Level Languages. With a hardware stack, the user is limited to a small fixed number of stack levels.

1.6 INSTRUCTION SET

In today's 8-bit microcontroller application arena cost/ performance, flexibility and time to market are several of the key issues that system designers face in attempting to build well-engineered products that compete in the marketplace. Many of these issues can be addressed through the manner in which a microcontroller's instruction set handles processing tasks. And that's why the COP8 family offers a unique and code-efficient instruction set - one that provides the flexibility, functionality, reduced costs and faster time to market that today's microcontroller based products require.

Code efficiency is important because it enables designers to pack more on-chip functionality into less program memory space (ROM, OTP or Flash). Selecting a microcontroller with less program memory size translates into lower system costs, and the added security of knowing that more code can be packed into the available program memory space.

1.6.1 Key Instruction Set Features

The COP8 family incorporates a unique combination of instruction set features, which provide designers with optimum code efficiency and program memory utilization.

1.6.2 Single Byte/Single Cycle Code Execution

The efficiency is due to the fact that the majority of instructions are of the single byte variety, resulting in minimum program space. Because compact code does not occupy a substantial amount of program memory space, designers can integrate additional features and functionality into the microcontroller program memory space. Also, the majority instructions executed by the device are single cycle, resulting in minimum program execution time. In fact, 77% of the instructions are single byte single cycle, providing greater code and I/O efficiency, and faster code execution.

1.6.3 Many Single-Byte, Multi-Function Instructions

The COP8 instruction set utilizes many single-byte, multifunction instructions. This enables a single instruction to accomplish multiple functions, such as DRSZ, DCOR, JID, LD (Load) and X (Exchange) instructions with postincrementing and post-decrementing, to name just a few

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1.0 General Description (Continued)

examples. In many cases, the instruction set can simultaneously execute as many as three functions with the same single-byte instruction.

JID: (Jump Indirect); Single byte instruction decodes external events and jumps to corresponding service routines (analogous to ªDO CASEº statements in higher level languages).

LAID: (Load Accumulator-Indirect); Single byte look up table instruction provides efficient data path from the program memory to the CPU. This instruction can be used for table lookup and to read the entire program memory for checksum calculations.

RETSK: (Return Skip); Single byte instruction allows return from subroutine and skips next instruction. Decision to branch can be made in the subroutine itself, saving code.

AUTOINC/DEC: (Auto-Increment/Auto-Decrement); These instructions use the two memory pointers B and X to efficiently process a block of data (simplifying ªFOR NEXTº or other loop structures in higher level languages).

1.6.4 Bit-Level Control

Bit-level control over many of the microcontroller's I/O ports provides a flexible means to ease layout concerns and save board space. All members of the COP8 family provide the

ability to set, reset and test any individual bit in the data memory address space, including memory-mapped I/O ports and associated registers.

1.6.5 Register Set

Three memory-mapped pointers handle register indirect addressing and software stack pointer functions. The memory data pointers allow the option of post-incrementing or postdecrementing with the data movement instructions (LOAD/ EXCHANGE). And 15 memory-mapped registers allow designers to optimize the precise implementation of certain specific instructions.

1.7 PACKAGING/PIN EFFICIENCY

Real estate and board configuration considerations demand maximum space and pin efficiency, particularly given today's high integration and small product form factors. Microcontroller users try to avoid using large packages to get the I/O needed. Large packages take valuable board space and increase device cost, two trade-offs that microcontroller designs can ill afford.

The COP8 family offers a wide range of packages and does not waste pins.

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (VCC)	7V
Voltage at Any Pin	−0.3V to V CC +0.3V
Total Current into VCC Pin (Source)	200 mA

Total Current out of GND Pin (Sink)	200 mA
Storage Temperature Range	−65ÊC to +140ÊC
ESD Protection Level	2 kV (Human Body
	Model)

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

2.0 Electrical Characteristics

TABLE 1. DC Electrical Characteristics (0ÊC ≤ TA ≤ +70ÊC)

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter	Conditions	Min	Typ	Max	Units
Operating Voltage		2.7		5.5	V
Power Supply Rise Time		10		50 x 106	ns
Power Supply Ripple (Note 2)	Peak-to-Peak			0.1 VCC	V
Supply Current (Note 3)
High Speed Mode
CKI = 10 MHz	VCC = 5.5V, tC = 0.5 µs			11.5	mA
CKI = 3.33 MHz	VCC = 4.5V, tC = 1.5 µs			5	mA
Dual Clock Mode
CKI = 10 MHz, Low Speed OSC = 32 kHz	VCC = 5.5V, tC = 0.5 µs			11.5	mA
CKI = 3.33 MHz, Low Speed OSC = 32 kHz	VCC = 4.5V, tC = 1.5 µs			5	mA
Low Speed Mode
Low Speed OSC = 32 kHz	VCC = 5.5V		60	103	µA
HALT Current with BOR Disabled (Note 4)
High Speed Mode	VCC = 5.5V, CKI = 0 MHz		<2	10	µA
Dual Clock Mode	VCC = 5.5V, CKI = 0 MHz,		<5	17	µA
	Low Speed OSC = 32 kHz
Low Speed Mode	VCC = 5.5V, CKI = 0 MHz,		<5	17	µA
	Low Speed OSC = 32 kHz
Idle Current (Note 3)
High Speed Mode
CKI = 10 MHz	VCC = 5.5V, tC = 0.5 µs			1.8	mA
CKI = 3.33 MHz	VCC = 4.5V, tC = 1.5 µs			0.8	mA
Dual Clock Mode
CKI = 10 MHz, Low Speed OSC = 32 kHz	VCC = 5.5V, tC = 0.5 µs			1.8	mA
CKI = 3.33 MHz, Low Speed OSC = 32 kHz	VCC = 4.5V, tC = 1.5 µs			0.8	mA
Low Speed Mode
Low Speed OSC = 32 kHz	VCC = 5.5V		15	30	µA
Supply Current When Programming In ISP	VCC = 5.0V, tC = 0.5 µs		26		mA
Supply Current for BOR Feature	VCC = 5.5V			45	µA
High Brownout Trip Level (BOR Enabled)		4.17	4.28	4.5	V
Low Brownout Trip Level (BOR Enabled)		2.7	2.78	2.9	V
Input Levels (VIH, VIL)
Logic High		0.8 VCC			V
Logic Low				0.16 VCC	V
Internal Bias Resistor for the CKI		0.3	1.0	2.5	MΩ
Crystal/Resonator Oscillator
Hi-Z Input Leakage	VCC = 5.5V	−0.5		+0.5	µA
Input Pullup Current	VCC = 5.5V, VIN = 0V	−50		−210	µA
Port Input Hysteresis		0.25 VCC			V

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COP8CBE9/CCE9/CDE9

2.0 Electrical Characteristics	(Continued)
TABLE 1. DC Electrical Characteristics (0ÊC ≤ TA ≤ +70ÊC) (Continued)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter	Conditions	Min	Typ	Max	Units
Output Current Levels
B0-B3 Outputs
Source (Weak Pull-Up Mode)	VCC = 4.5V, VOH = 3.8V	−10			µA
	VCC = 2.7V, VOH = 1.8V	-5			µA
Source (Push-Pull Mode) (Note 7)	VCC = 4.5V, VOH = 4.2V	−10			mA
	VCC = 2.7V, VOH = 2.4V	−6			mA
Sink (Push-Pull Mode) (Note 7)	VCC = 4.5V, VOL = 0.3V	10			mA
	VCC = 2.7V, VOL = 0.3V	6			mA
Allowable Sink and Source Current per Pin				20	mA
All Others
Source (Weak Pull-Up Mode)	VCC = 4.5V, VOH = 3.8V	−10			µA
	VCC = 2.7V, VOH = 1.8V	−5			µA
Source (Push-Pull Mode)	VCC = 4.5V, VOH = 3.8V	−7			mA
	VCC = 2.7V, VOH = 1.8V	−4			mA
Sink (Push-Pull Mode) (Note 7)	VCC = 4.5V, VOL = 1.0V	10			mA
	VCC = 2.7V, VOL = 0.4V	3.5			mA
Allowable Sink and Source Current per Pin				15	mA
TRI-STATE Leakage	VCC = 5.5V	−0.5		+0.5	µA
Maximum Input Current without Latchup (Note 5)				±200	mA
RAM Retention Voltage, VR (in HALT Mode)		2.0			V
Input Capacitance				7	pF
Voltage on G6 to Force Execution from Boot	G6 rise time must be slower	2 x VCC		VCC + 7	V
ROM(Note 8)	than 100 ns
G6 Rise Time to Force Execution from Boot ROM		100			nS
Input Current on G6 when Input > VCC	VIN = 11V, VCC = 5.5V		500		µA
Flash Memory Data Retention	25ÊC		100		yrs
Flash Memory Number of Erase/Write Cycles	See Table 14, Typical Flash		105		cycles
	Memory Endurance

AC Electrical Characteristics (0ÊC ≤ TA ≤ +70ÊC)

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter	Conditions	Min	Typ	Max	Units
Instruction Cycle Time (tC)
Crystal/Resonator	4.5V ≤ VCC ≤ 5.5V	0.5		DC	µs
	2.7V ≤ VCC < 4.5V	1.5		DC	µs
Flash Memory Page Erase Time	See Table 14, Typical
	Flash Memory		1		ms
	Endurance
Flash Memory Mass Erase Time			8		ms
Frequency of MICROWIRE/PLUS in				2	MHz
Slave Mode
MICROWIRE/PLUS Setup Time (tUWS)		20			ns
MICROWIRE/PLUS Hold Time (tUWH)		20			ns
MICROWIRE/PLUS Output Propagation				150	ns
Delay (tUPD)

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AC Electrical Characteristics (0ÊC ≤ TA ≤ +70ÊC) (Continued)

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter		Conditions	Min	Typ	Max	Units
Input Pulse Width
Interrupt Input High Time			1			tC
Interrupt Input Low Time			1			tC
Timer 1 Input High Time			1			tC
Timer 1 Input Low Time			1			tC
Timer 2 Input High Time (Note 6)			1			MCLK or tC
Timer 2 Input Low Time (Note 6)			1			MCLK or tC
Output Pulse Width
Timer 2 Output High Time			150			ns
Timer 2 Output Low Time			150			ns
USART Bit Time when using External			6 CKI
CKX			periods
USART CKX Frequency when being					2	MHz
Driven by Internal Baud Rate Generator
Reset Pulse Width			1			tC
tC = instruction cycle time.
Note 2: Maximum rate of voltage change must be < 0.5 V/ms.

Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180Ê out of phase with CKI, inputs connected to VCC and outputs driven low but not connected to a load.

Note 4: The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with A. B, G0, G2±G5, H and L programmed as low outputs and not driving a load; all inputs tied to VCC; A/D converter and clock monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.

Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.

Note 6: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC.

Note 7: Absolute Maximum Ratings should not be exceeded.

Note 8: Vcc must be valid and stable before G6 is raised to a high voltage.

A/D Converter Electrical Characteristics (0ÊC ≤ TA ≤ +70ÊC) (Single-ended mode only)

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter	Conditions	Min	Typ	Max	Units
Resolution				10	Bits
DNL	VCC = 5V			±1	LSB
DNL	VCC = 3V			±1	LSB
INL	VCC = 5V			±2	LSB
INL	VCC = 3V			±4	LSB
Offset Error	VCC = 5V			±1.5	LSB
Offset Error	VCC = 3V			±2.5	LSB
Gain Error	VCC = 5V			±1.5	LSB
Gain Error	VCC = 3V			±2.5	LSB
Input Voltage Range	2.7V ≤ VCC < 5.5V	0		VCC	V
Analog Input Leakage Current				0.5	µA
Analog Input Resistance (Note 9)				6k	Ω
Analog Input Capacitance				7	pF
Conversion Clock Period	4.5V ≤ VCC < 5.5V	0.8		30	µs
	2.7V ≤ VCC < 4.5V	1.2		30	µs
Conversion Time (including S/H Time)			15		A/D
					Conversion
					Clock
					Cycles
Operating Current on AVCC	AVCC = 5.5V		0.2	0.6	mA

Note 9: Resistance between the device input and the internal sample and hold capacitance.

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COP8CBE9/CCE9/CDE9

DC Electrical Characteristics (−40ÊC ≤ TA ≤ +125ÊC)

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter	Conditions	Min	Typ	Max	Units
Operating Voltage		4.5		5.5	V
Power Supply Rise Time		10		50 x 106	ns
Power Supply Ripple (Note 2)	Peak-to-Peak			0.1 VCC	V
Supply Current (Note 3)
High Speed Mode
CKI = 10 MHz	VCC = 5.5V, tC = 0.5 µs			12.4	mA
CKI = 3.33 MHz	VCC = 4.5V, tC = 1.5 µs			5.5	mA
Dual Clock Mode
CKI = 10 MHz, Low Speed OSC = 32 kHz	VCC = 5.5V, tC = 0.5 µs			12.4	mA
CKI = 3.33 MHz, Low Speed OSC = 32 kHz	VCC = 4.5V, tC = 1.5 µs			5.5	mA
Low Speed Mode
Low Speed OSC = 32 kHz	VCC = 5.5V		65	110	µA
HALT Current with BOR Disabled (Note 4)
High Speed Mode	VCC = 5.5V, CKI = 0 MHz		<4	40	µA
Dual Clock Mode	VCC = 5.5V, CKI = 0 MHz,		<9	50	µA
	Low Speed OSC = 32 kHz
Low Speed Mode	VCC = 5.5V, CKI = 0 MHz,		<9	50	µA
	Low Speed OSC = 32 kHz
Idle Current (Note 3)
High Speed Mode
CKI = 10 MHz	VCC = 5.5V, tC = 0.5 µs			1.9	mA
Dual Clock Mode
CKI = 10 MHz, Low Speed OSC = 32 kHz	VCC = 5.5V, tC = 0.5 µs			1.9	mA
Low Speed Mode
Low Speed OSC = 32 kHz	VCC = 5.5V		30	70	µA
Supply Current When Programming In ISP	VCC = 5.0V, tC = 0.5 µs		26		mA
Supply Current for BOR Feature	VCC = 5.5V			45	µA
High Brownout Trip Level (BOR Enabled)		4.17	4.28	4.5	V
Input Levels (VIH, VIL)
Logic High		0.8 VCC			V
Logic Low				0.16 VCC	V
Internal Bias Resistor for the CKI Crystal/Resonator		0.3	1.0	2.5	MΩ
Oscillator
Hi-Z Input Leakage	VCC = 5.5V	−3		+3	µA
Input Pullup Current	VCC = 5.5V, VIN = 0V	−40		−250	µA
Port Input Hysteresis		0.25 VCC			V
Output Current Levels
B0-B3 Outputs
Source (Weak Pull-Up Mode)	VCC = 4.5V, VOH = 3.8V	−9			µA
Source (Push-Pull Mode)	VCC = 4.5V, VOH = 4.2V	−9			mA
Sink (Push-Pull Mode) (Note 7)	VCC = 4.5V, VOL = 0.3V	9			mA
Allowable Sink and Source Current per Pin				15	mA
All Others
Source (Weak Pull-Up Mode)	VCC = 4.5V, VOH = 3.8V	−9			µA
Source (Push-Pull Mode)	VCC = 4.5V, VOH = 3.8V	−6.3			mA
Sink (Push-Pull Mode) (Note 7)	VCC = 4.5V, VOL = 1.0V	9			mA
Allowable Sink and Source Current per Pin				12	mA
TRI-STATE Leakage	VCC = 5.5V	−3		+3	µA
Maximum Input Current without Latchup (Note 5)				±200	mA

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10

DC Electrical Characteristics (−40ÊC ≤ TA ≤ +125ÊC)		(Continued)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter	Conditions	Min	Typ	Max	Units
RAM Retention Voltage, VR (in HALT Mode)		2.0			V
Input Capacitance				7	pF
Voltage on G6 to Force Execution from Boot	G6 rise time must be slower	2 x VCC		VCC + 7	V
ROM(Note 8)	than 100 ns
G6 Rise Time to Force Execution from Boot ROM		100			nS
Input Current on G6 when Input > VCC	VIN = 11V, VCC = 5.5V		500		µA

AC Electrical Characteristics (−40ÊC ≤ TA ≤ +125ÊC)

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter	Conditions	Min	Typ	Max	Units
Instruction Cycle Time (tC)
Crystal/Resonator	4.5V ≤ VCC ≤ 5.5V	0.5		DC	µs
Output Propagation Delay	RL =2.2k, CL = 100 pF
Frequency of MICROWIRE/PLUS in Slave				2	MHz
Mode
MICROWIRE/PLUS Setup Time (tUWS)		20			ns
MICROWIRE/PLUS Hold Time (tUWH)		20			ns
MICROWIRE/PLUS Output Propagation Delay				150	ns
(tUPD)
Input Pulse Width
Interrupt Input High Time		1			tC
Interrupt Input Low Time		1			tC
Timer 1 Input High Time		1			tC
Timer 1 Input Low Time		1			tC
Timer 2, 3 Input High Time (Note 6)		1			MCLK or tC
Timer 2, 3 Input Low Time (Note 6)		1			MCLK or tC
Output Pulse Width
Timer 2, 3 Output High Time		150			ns
Timer 2, 3 Output Low Time		150			ns
USART Bit Time when using External CKX		6 CKI
		periods
USART CKX Frequency when being Driven by				2	MHz
Internal Baud Rate Generator
Reset Pulse Width		0.5			tC
tC = instruction cycle time.
Note 10: Maximum rate of voltage change must be < 0.5 V/ms.

Note 11: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180Ê out of phase with CKI, inputs connected to VCC and outputs driven low but not connected to a load.

Note 12: The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F, G0, and G2±G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to VCC; A/D converter and clock monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.

Note 13: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at the pins must be limited to < (VCC + 7V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.

Note 14: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC.

Note 15: Absolute Maximum Ratings should not be exceeded.

Note 16: Vcc must be valid and stable before G6 is raised to a high voltage.

COP8CBE9/CCE9/CDE9

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COP8CBE9/CCE9/CDE9

A/D Converter Electrical Characteristics (−40ÊC		≤ TA ≤ +125ÊC) (Single-ended mode only)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter	Conditions		Min	Typ		Max	Units
Resolution						10	Bits
DNL	VCC = 5V					±1	LSB
INL	VCC = 5V					±2	LSB
Offset Error	VCC = 5V					±1.5	LSB
Gain Error	VCC = 5V					±1.5	LSB
Input Voltage Range	4.5V ≤ VCC < 5.5V		0			VCC	V
Analog Input Leakage Current						0.5	µA
Analog Input Resistance (Note 9)						6k	Ω
Analog Input Capacitance						7	pF
Conversion Clock Period	4.5V ≤ VCC < 5.5V		0.8			30	µs
Conversion Time (including S/H Time)				15			A/D
							Conversion
							Clock
							Cycles
Operating Current on AVCC	AVCC = 5.5V			0.2		0.66	mA

Note 17: Resistance between the device input and the internal sample and hold capacitance.

20022505

FIGURE 1. MICROWIRE/PLUS Timing

3.0 Pin Descriptions

The COP8CBE/CCE/CDE I/O structure enables designers to reconfigure the microcontroller's I/O functions with a single instruction. Each individual I/O pin can be independently configured as output pin low, output high, input with high impedance or input with weak pull-up device. A typical example is the use of I/O pins as the keyboard matrix input lines. The input lines can be programmed with internal weak pull-ups so that the input lines read logic high when the keys are all open. With a key closure, the corresponding input line will read a logic zero since the weak pull-up can easily be overdriven. When the key is released, the internal weak pull-up will pull the input line back to logic high. This eliminates the need for external pull-up resistors. The high current options are available for driving LEDs, motors and speakers. This flexibility helps to ensure a cleaner design, with less external components and lower costs. Below is the general description of all available pins.

Users of the LLP package are cautioned to be aware that the central metal area and the pin 1 index mark on the bottom of the package may be connected to GND. See figure below:

VCC and GND are the power supply pins. All VCC and GND	20022570
pins must be connected.	FIGURE 2.

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12

3.0 Pin Descriptions (Continued)

CKI is the clock input. This can be connected (in conjunction with CKO) to an external crystal circuit to form a crystal oscillator. See Oscillator Description section.

RESET is the master reset input. See Reset description section.

AVCC is the Analog Supply for A/D converter. It should be connected to VCC externally. This is also the top of the resistor ladder D/A converter used within the A/D converter.

AGND is the ground pin for the A/D converter. It should be connected to GND externally. This is also the bottom of the resistor ladder D/A converter used within the A/D converter.

The device contains up to six bidirectional 8-bit I/O ports (A, B, G, H and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G), output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has three associated 8-bit memory mapped registers, the CONFIGURATION register, the output DATA register and the Pin input register. (See the memory map for the various addresses associated with the I/O ports.) Figure 3 shows the I/O port configurations. The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below:

	CONFIGURATION	DATA	Port Set-Up
	Register	Register
	0	0	Hi-Z Input
			(TRI-STATE Output)
	0	1	Input with Weak Pull-Up
	1	0	Push-Pull Zero Output
	1	1	Push-Pull One Output

Port A is an 8-bit I/O port. All A pins have Schmitt triggers on the inputs. The 44-pin package does not have a full 8-bit port and contains some unbonded, floating pads internally on the chip. The binary value read from these bits is undetermined. The application software should mask out these unknown bits when reading the Port A register, or use only bit-access program instructions when accessing Port A. These unconnected bits draw power only when they are addressed (i.e., in brief spikes). Additionally, if Port A is being used with some combination of digital inputs and analog inputs, the analog inputs will read as undetermined values and should be masked out by software.

Port A supports the analog inputs for the A/D converter. Port A has the following alternate pin functions:

A7 Analog Channel 7

A6 Analog Channel 6

A5 Analog Channel 5

A4 Analog Channel 4

A3 Analog Channel 3

A2 Analog Channel 2

A1 Analog Channel 1

A0 Analog Channel 0

Port B is an 8-bit I/O port. All B pins have Schmitt triggers on the inputs. If Port B is being used with some combination of digital inputs and analog inputs, the analog inputs will read as undetermined values. The application software should mask out these unknown bits when reading the Port B register, or use only bit-access program instructions when accessing Port B.

Port B supports the analog inputs for the A/D converter. Port B has the following alternate pin functions:

B7 Analog Channel 15 or A/D Input

B6 Analog Channel 14 or Analog Multiplexor Output

B5 Analog Channel 13 or Analog Multiplexor Output

B4 Analog Channel 12

B3 Analog Channel 11

B2 Analog Channel 10

B1 Analog Channel 9

B0 Analog Channel 8

Port G is an 8-bit port. Pin G0, G2±G5 are bi-directional I/O ports. Pin G6 is always a general purpose Hi-Z input. All pins have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WATCHDOG output with weak pull-up if the WATCHDOG feature is selected by the Option register. The pin is a general purpose I/O if WATCHDOG feature is not selected. If WATCHDOG feature is selected, bit 1 of the Port G configuration and data register does not have any effect on Pin G1 setup. G7 serves as the dedicated output pin for the CKO clock output.

Since G6 is an input only pin and G7 is the dedicated CKO clock output pin, the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will return zeros.

The device will be placed in the HALT mode by writing a ª1º to bit 7 of the Port G Data Register. Similarly the device will be placed in the IDLE mode by writing a ª1º to bit 6 of the Port G Data Register.

Writing a ª1º to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay after HALT when the R/C clock configuration is used.

		Config. Reg.	Data Reg.
	G7	CLKDLY	HALT
	G6	Alternate SK	IDLE
Port G has the following alternate features:
G7	CKO Oscillator dedicated output
G6	SI (MICROWIRE/PLUS Serial Data Input)
G5	SK (MICROWIRE/PLUS Serial Clock)
G4	SO (MICROWIRE/PLUS Serial Data Output)
G3	T1A (Timer T1 I/O)
G2	T1B (Timer T1 Capture Input)
G1	WDOUT WATCHDOG and/or Clock Monitor if WATCH-
	DOG enabled, otherwise it is a general purpose I/O
G0	INTR (External Interrupt Input)

G0 through G3 are also used for In-System Emulation.

Port H is an 8-bit I/O port. All H pins have Schmitt triggers on the inputs.

Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs.

Port L supports the Multi-Input Wake-up feature on all eight pins. Port L has the following alternate pin functions:

L7 Multi-Input Wake-up

L6 Multi-Input Wake-up

L5 Multi-Input Wake-up or T2B (Timer T2B Input) L4 Multi-input Wake-up or T2A (Timer T2A Input)

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COP8CBE9/CCE9/CDE9

3.0 Pin Descriptions (Continued)

L3 Multi-Input Wake-up and/or RDX (USART Receive) L2 Multi-Input Wake-up or TDX (USART Transmit)

L1 Multi-Input Wake-up and/or CKX (USART Clock) (Low Speed Oscillator Output)

L0 Multi-Input Wake-up (Low Speed Oscillator Input)

20022560

FIGURE 3. I/O Port Configurations

20022561

FIGURE 4. I/O Port Configurations Ð Output Mode

20022562

FIGURE 5. I/O Port Configurations Ð Input Mode

3.1 EMULATION CONNECTION

Connection to the emulation system is made via a 2 x 7 connector which interrupts the continuity of the RESET, G0, G1, G2 and G3 signals between the COP8 device and the rest of the target system (as shown in Figure 6). This connector can be designed into the production pc board and can be replaced by jumpers or signal traces when emulation is no longer necessary. The emulator will replicate all functions of G0 - G3 and RESET. For proper operation, no connection should be made on the device side of the emulator connector.

20022509

FIGURE 6. Emulation Connection

4.0 Functional Description

The architecture of the device is a modified Harvard architecture. With the Harvard architecture, the program memory (Flash) is separate from the data store memory (RAM). Both Program Memory and Data Memory have their own separate addressing space with separate address buses. The architecture, though based on the Harvard architecture, permits transfer of data from Flash Memory to RAM.

4.1 CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (tC) cycle time.

There are six CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or decremented.

S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256 data segments of 128 bytes each.

SP is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in RAM). With reset the SP is initialized to

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14

4.0 Functional Description (Continued)

RAM address 06F Hex. The SP is decremented as items are pushed onto the stack. SP points to the next available location on the stack.

All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).

4.2 PROGRAM MEMORY

The program memory consists of 8192 bytes of Flash Memory. These bytes may hold program instructions or constant data (data tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit

program counter (PC). All interrupts in the device vector to program memory location 00FF Hex. The program memory reads 00 Hex in the erased state. Program execution starts at location 0 after RESET.

If a Return instruction is executed when the SP contains 6F (hex), instruction execution will continue from Program Memory location 7FFF (hex). If location 7FFF is accessed by an instruction fetch, the Flash Memory will return a value of 00. This is the opcode for the INTR instruction and will cause a Software Trap.

For the purpose of erasing and rewriting the Flash Memory, it is organized in pages of 64 bytes as show in Table 2.

TABLE 2. Available Memory Address Ranges

		Program	Flash Memory				Maximum
				Option Register	Data Memory	Segments	RAM
	Device	Memory	Page Size
				Address (Hex)	Size (RAM)	Available	Address
		Size (Flash)	(Bytes)
							(HEX)
	COP8CBE9
	COP8CCE9	8192	64	1FFF	256	0-1	017F
	COP8CDE9

4.3 DATA MEMORY

The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the various registers, and counters associated with the timers and the USART (with the exception of the IDLE timer). Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers.

The data memory consists of 256 bytes of RAM. Sixteen bytes of RAM are mapped as ªregistersº at addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP, B and S are memory mapped into this space at address locations 0FC to 0FF Hex respectively, with the other registers being available for general usage.

The instruction set permits any bit in memory to be set, reset or tested. All I/O and registers (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

4.4 DATA MEMORY SEGMENT RAM EXTENSION

Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S).

The data store memory is either addressed directly by a single byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows an addressing range of 256 locations from 00 to FF hex. The upper bit of this single-byte address divides the data store memory into two separate sections as outlined previously. With the exception of the RAM register memory from address locations 00F0 ± 00FF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte address to determine whether or not the base address range (from 0000 ± 00FF) is extended. If this upper bit equals one (representing address range 0080 ± 00FF),

then address extension does not take place. Alternatively, if this upper bit equals zero, then the data segment extension register S is used to extend the base address range from 0000 ± 007F to XX00 ± XX7F, where XX represents the 8 bits from the S register. Thus the 128-byte data segment extensions are located from addresses 0100 ± 017F for data segment 1, 0200 ± 027F for data segment 2, etc., up to FF00

± FF7F for data segment 255. The base address range from 0000 ± 007F represents data segment 0.

Refer to Table 2, to determine available RAM segments for this device.

Figure 7 illustrates how the S register data memory extension is used in extending the lower half of the base address range (00 to 7F hex) into 256 data segments of 128 bytes each, with a total addressing range of 32 kbytes from XX00 to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are available for all data segments. The S register must be changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I/O registers, control registers, etc.) is always available regardless of the contents of the S register, since the upper base segment (address range 0080 to 00FF) is independent of data segment extension.

The instructions that utilize the stack pointer (SP) always reference the stack as part of the base segment (Segment 0), regardless of the contents of the S register. The S register is not changed by these instructions. Consequently, the stack (used with subroutine linkage and interrupts) is always located in the base segment. The stack pointer will be initialized to point at data memory location 006F as a result of reset.

The 128 bytes of RAM contained in the base segment are split between the lower and upper base segments. The first 112 bytes of RAM are resident from address 0000 to 006F in the lower base segment, while the remaining 16 bytes of RAM represent the 16 data memory registers located at

COP8CBE9/CCE9/CDE9

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COP8CBE9/CCE9/CDE9

4.0 Functional Description (Continued)	at the data segment address extensions (XX00 to XX7F) of
	the lower base segment. The additional 128 bytes of RAM in
addresses 00F0 to 00FF of the upper base segment. No	this device are memory mapped at address locations 0100
RAM is located at the upper sixteen addresses (0070 to	through 017F.
007F) of the lower base segment.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)

20022510

FIGURE 7. RAM Organization

4.4.1 Virtual EEPROM

The Flash memory and the User ISP functions (see Section 5.7), provide the user with the capability to use the flash program memory to back up user defined sections of RAM. This effectively provides the user with the same nonvolatile data storage as EEPROM. Management, and even the amount of memory used, are the responsibility of the user, however the flash memory read and write functions have been provided in the boot ROM.

One typical method of using the Virtual EEPROM feature would be for the user to copy the data to RAM during system initialization, periodically, and if necessary, erase the page of Flash and copy the contents of the RAM back to the Flash.

4.5 OPTION REGISTER

The Option register, located at address 0x3FFF (hex) in the Flash Program Memory, is used to configure the user selectable security, WATCHDOG, and HALT options. The register can be programmed only in external Flash Memory programming or ISP Programming modes. Therefore, the register must be programmed at the same time as the program memory. The contents of the Option register shipped from the factory read 00 Hex.

The format of the Option register is as follows:

	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	Reserved		SECURITY	Reserved		WATCH	HALT	FLEX
						DOG

Bits 7, 6 These bits are reserved and must be 0.

Bit 5

=1 Security enabled. Flash Memory read and write are not allowed except in User ISP/Virtual E2 commands. Mass Erase is allowed.

=0 Security disabled. Flash Memory read and write are allowed.

Bits 4, 3 These bits are reserved and must be 0.

Bit 2

=1 WATCHDOG feature disabled. G1 is a general purpose I/O.

=0 WATCHDOG feature enabled. G1 pin is WATCHDOG output with weak pullup.

Bit 1

=1 HALT mode disabled.

=0 HALT mode enabled. Bit 0

=1 Execution following RESET will be from Flash Memory.

=0 Flash Memory is erased. Execution following RESET will be from Boot ROM with the MICROWIRE/ PLUS ISP routines.

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4.0 Functional Description (Continued)

The COP8 assembler defines a special ROM section type, CONF, into which the Option Register data may be coded. The Option Register is programmed automatically by programmers that are certified by National.

The user needs to ensure that the FLEX bit will be set when the device is programmed.

The following examples illustrate the declaration of the Option Register.

Syntax:
[label:].sect	config, conf
.db	value	;1 byte,
		;configures
		;options

.endsect

Example: The following sets a value in the Option Register and User Identification for a COP8CBE9HVA7. The Option Register bit values shown select options: Security disabled, WATCHDOG enabled HALT mode enabled and execution will commence from Flash Memory.

.chip	8CBE
.sect	option, conf
.db	0x01	;wd, halt, flex
.endsect
...
.end	start

Note: All programmers certified for programming this family of parts will support programming of the Option Register. Please contact National or your device programmer supplier for more information.

4.6 SECURITY

The device has a security feature which, when enabled, prevents external reading of the Flash program memory. The security bit in the Option Register determines, whether security is enabled or disabled. If the security feature is disabled, the contents of the internal Flash Memory may be read by external programmers or by the built in MICROWIRE/PLUS serial interface ISP. Security must be enforced by the user when the contents of the Flash Memory are accessed via the user ISP or Virtual EEPROM capability.

If the security feature is enabled, then any attempt to externally read the contents of the Flash Memory will result in the value FF (hex) being read from all program locations (except the Option Register). In addition, with the security feature enabled, the write operation to the Flash program memory and Option Register is inhibited. Page Erases are also inhibited when the security feature is enabled. The Option Register is readable regardless of the state of the security bit by accessing location FFFF (hex). Mass Erase Operations are possible regardless of the state of the security bit.

The security bit can be erased only by a Mass Erase of the entire contents of the Flash unless Flash operation is under the control of User ISP functions.

Note: The actual memory address of the Option Register is 0x3FFF (hex), however the MICROWIRE/PLUS ISP routines require the address FFFF (hex) to be used to read the Option Register when the Flash Memory is secured.

The entire Option Register must be programmed at one time and cannot be rewritten without first erasing the entire last page of Flash Memory.

4.7 RESET

The device is initialized when the RESET pin is pulled low or the On-chip Brownout Reset is activated. The Brownout Reset feature is not available on the COP8CDE9.

20022511

FIGURE 8. Reset Logic

The following occurs upon initialization:

Port A: TRI-STATE (High Impedance Input)

Port B: TRI-STATE (High Impedance Input)

Port G: TRI-STATE (High Impedance Input). Exceptions: If Watchdog is enabled, then G1 is Watchdog output. G0 and G2 have their weak pull-up enabled during RESET.

Port H: TRI-STATE (High Impedance Input)

Port L: TRI-STATE (High Impedance Input)

PC: CLEARED to 0000

PSW, CNTRL and ICNTRL registers: CLEARED

SIOR:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

T2CNTRL: CLEARED

HSTCR: CLEARED

ITMR: Cleared except Bit 6 (HSON) = 1

Accumulator, Timer 1 and Timer 2:

RANDOM after RESET

WKEN, WKEDG: CLEARED

WKPND: RANDOM

SP (Stack Pointer):

Initialized to RAM address 06F Hex

B and X Pointers:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

S Register: CLEARED

RAM:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

USART:

PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit

which is set to one.

ANALOG TO DIGITAL CONVERTER:

ENAD: CLEARED

ADRSTH: RANDOM

ADRSTL: RANDOM

ISP CONTROL:

ISPADLO: CLEARED

ISPADHI: CLEARED

PGMTIM: PRESET TO VALUE FOR 10 MHz CKI

WATCHDOG (if enabled):

The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with the

COP8CBE9/CCE9/CDE9

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4.0 Functional Description (Continued)

WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits being initialized high default to the maximum WATCHDOG service window of 64k T0 clock cycles. The Clock Monitor bit being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor error will cause an active low error output on pin G1. This error output will continue until 16±32 T0 clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will go high.

4.7.1 External Reset

The RESET input when pulled low initializes the device. The RESET pin must be held low for a minimum of one instruction cycle to guarantee a valid reset. During Power-Up initialization, the user must ensure that the RESET pin of a device without the Brownout Reset feature is held low until the device is within the specified VCC voltage. An R/C circuit on the RESET pin with a delay 5 times (5x) greater than the power supply rise time is recommended. Reset should also be wide enough to ensure crystal start-up upon Power-Up.

RESET may also be used to cause an exit from the HALT mode.

A recommended reset circuit for this device is shown in

Figure 9.

20022512

FIGURE 9. Reset Circuit Using External Reset

4.7.2 On-Chip Brownout Reset

When enabled, the device generates an internal reset as VCC rises. While VCC is less than the specified brownout voltage (Vbor), the device is held in the reset condition and the Idle Timer is preset with 00Fx (240±256 tC). When VCC reaches a value greater than Vbor, the Idle Timer starts counting down. Upon underflow of the Idle Timer, the internal reset is released and the device will start executing instructions. This internal reset will perform the same functions as external reset. Once VCC is above the Vbor and this initial Idle Timer time-out takes place, instruction execution begins and the Idle Timer can be used normally. If, however, VCC drops below the selected Vbor, an internal reset is generated, and the Idle Timer is preset with 00Fx. The device now waits until VCC is greater than Vbor and the countdown starts over. When enabled, the functional operation of the device, at frequency, is guaranteed down to the Vbor level.

	20022513
FIGURE 10. Brownout Reset Operation
One exception to the above is that the brownout circuit will	Timer starts counting the 240 to 256 tC. This delay starts as
insert a delay of approximately 3 ms on power up or any time	soon as the VCC rises above the trigger voltage (approxi-
the VCC drops below a voltage of about 1.8V. The device will	mately 1.8V). This behavior is shown in Figure 10.
be held in Reset for the duration of this delay before the Idle

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4.0 Functional Description (Continued)

In Case 1, VCC rises from 0V and the on-chip RESET is undefined until the supply is greater than approximately 1.0V. At this time the brownout circuit becomes active and holds the device in RESET. As the supply passes a level of about 1.8V, a delay of about 3 ms (td) is started and the Idle Timer is preset to a value between 00F0 and 00FF (hex).

Once VCC is greater than Vbor and td has expired, the Idle Timer is allowed to count down (tid).

Case 2 shows a subsequent dip in the supply voltage which goes below the approximate 1.8V level. As VCC drops below Vbor, the internal RESET signal is asserted. When VCC rises back above the 1.8V level, td is started. Since the power supply rise time is longer for this case, td has expired before VCC rises above Vbor and tid starts immediately when VCC is greater than Vbor.

Case 3 shows a dip in the supply where VCC drops below Vbor, but not below 1.8V. On-chip RESET is asserted when

VCC goes below Vbor and tid starts as soon as the supply goes back above Vbor.

If the Brownout Reset feature is enabled, the internal reset will not be turned off until the Idle Timer underflows. The internal reset will perform the same functions as external reset. The device is guaranteed to operate at the specified frequency down to the specified brownout voltage. After the underflow, the logic is designed such that no additional internal resets occur as long as VCC remains above the brownout voltage.

The device is relatively immune to short duration negativegoing VCC transients (glitches). It is essential that good filtering of VCC be done to ensure that the brownout feature works correctly. Power supply decoupling is vital even in battery powered systems.

There are two optional brownout voltages. The part numbers for the three versions of this device are:

COP8CBE, Vbor = low voltage range

COP8CCE, Vbor = high voltage range

COP8CDE, BOR is disabled.

Refer to the device specifications for the actual Vbor voltages.

High brownout voltage devices are guaranteed to operate at 10MHz down to the high brownout voltage. Low brownout voltage devices are guaranteed to operate at 3.33MHz down to the low brownout voltage. Low brownout voltage devices are not guaranteed to operate at 10MHz down to the low brownout voltage.

Under no circumstances should the RESET pin be allowed to float. If the on-chip Brownout Reset feature is being used,

the RESET pin should be connected directly to VCC. The RESET input may also be connected to an external pull-up resistor or to other external circuitry. The output of the brownout reset detector will always preset the Idle Timer to a value between 00F0 and 00FF (240 to 256 tC). At this time, the internal reset will be generated.

If the BOR feature is disabled, then no internal resets are generated and the Idle Timer will power-up with an unknown value. In this case, the external RESET must be used. When BOR is disabled, this on-chip circuitry is disabled and draws no DC current.

The contents of data registers and RAM are unknown following the on-chip reset.

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FIGURE 11. Reset Circuit Using Power-On Reset

4.8 OSCILLATOR CIRCUITS

The device has two crystal oscillators to facilitate low power operation while maintaining throughput when required. Further information on the use of the two oscillators is found in Section 7.0 Power Saving Features. The low speed oscillator utilizes the L0 and L1 port pins. References in the following text to CKI will also apply to L0 and references to G7/CKO will also apply to L1.

4.8.1 Oscillator

CKI is the clock input while G7/CKO is the clock generator output to the crystal. An on-chip bias resistor connected between CKI and CKO is provided to reduce system part count. The value of the resistor is in the range of 0.5M to 2M (typically 1.0M). Table 3 shows the component values required for various standard crystal values. Resistor R2 is on-chip, for the high speed oscillator, and is shown for reference. Figure 12 shows the crystal oscillator connection diagram. A ceramic resonator of the required frequency may be used in place of a crystal if the accuracy requirements are not quite as strict.

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4.0 Functional Description (Continued)

High Speed Oscillator

Low Speed Oscillator

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20022515

FIGURE 12. Crystal Oscillator

TABLE 3. Crystal Oscillator Configuration,

TA = 25ÊC, VCC = 5V

	R1 (kΩ)	R2 (MΩ)	C1 (pF)	C2 (pF)	CKI Freq.
					(MHz)
	0	On Chip	18	18	10
	0	On Chip	18	18	5
	0	On Chip	18±36	18±36	1
	5.6	On Chip	100	100±156	0.455
	0	20	**	**	32.768
					kHz*

*Applies to connection to low speed oscillator on port pins L0 and L1 only. **See Note below.

The crystal and other oscillator components should be placed in close proximity to the CKI and CKO pins to minimize printed circuit trace length.

The values for the external capacitors should be chosen to obtain the manufacturer's specified load capacitance for the crystal when combined with the parasitic capacitance of the trace, socket, and package (which can vary from 0 to 8 pF). The guideline in choosing these capacitors is:

Manufacturer's specified load cap = (C1 * C2) / (C1 + C2) +

Cparasitic

C2 can be trimmed to obtain the desired frequency. C2 should be less than or equal to C1.

Note: The low power design of the low speed oscillator makes it extremely sensitive to board layout and load capacitance. The user should place the crystal and load capacitors within 1cm. of the device and must ensure that the above equation for load capacitance is strictly followed. If these conditions are not met, the application may have problems with startup of the low speed oscillator.

TABLE 4. Startup Times

CKI Frequency	Startup Time
10 MHz	1±10 ms
3.33 MHz	3±10 ms
1 MHz	3±20 ms
455 kHz	10±30 ms
32 kHz (low speed oscillator)	2±5 sec

4.8.2 Clock Doubler

This device contains a frequency doubler that doubles the frequency of the oscillator selected to operate the main microcontroller core. The details of how to select either the high speed oscillator or low speed oscillator are described in, Power Saving Features. When the high speed oscillator connected to CKI operates at 10 MHz, the internal clock frequency is 20 MHz, resulting in an instruction cycle time of 0.5 µs. When the 32 kHz oscillator connected to L0 and L1 is selected, the internal clock frequency is 64 kHz, resulting in an instruction cycle of 152.6 µs. The output of the clock doubler is called MCLK and is referenced in many places within this document.

4.9 CONTROL REGISTERS

CNTRL Register (Address X©00EE)

T1C3	T1C2	T1C1	T1C0	MSEL	IEDG	SL1	SL0
Bit 7							Bit 0

The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits:

T1C3	Timer T1 mode control bit
T1C2	Timer T1 mode control bit
T1C1	Timer T1 mode control bit
T1C0	Timer T1 Start/Stop control in		timer
	modes 1 and 2.	T1 Underflow Interrupt
	Pending Flag in timer mode 3
MSEL	Selects G5 and G4 as MICROWIRE/PLUS
	signals SK and SO respectively
IEDG	External interrupt	edge polarity	select
	(0 = Rising edge, 1 = Falling edge)
SL1 & SL0	Select the MICROWIRE/PLUS clock divide
	by (00 = 2, 01 = 4, 1x = 8)

PSW Register (Address X©00EF)

HC	C	T1PNDA	T1ENA	EXPND	BUSY	EXEN	GIE
Bit 7							Bit 0

The PSW register contains the following select bits:

HC	Half Carry Flag

C Carry Flag

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA

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4.0 Functional Description (Continued)

	in mode 1, T1 Underflow in Mode 2, T1A capture
	edge in mode 3)
T1ENA	Timer T1 Interrupt Enable for Timer Underflow or
	T1A Input capture edge
EXPND	External interrupt pending
BUSY	MICROWIRE/PLUS busy shifting flag
EXEN	Enable external interrupt
GIE	Global interrupt enable (enables interrupts)

The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and R/C (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and R/C instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags.

ICNTRL Register (Address X©00E8)

Unused	LPEN		T0PND	T0EN	µWPND	µWEN	T1PNDB	T1ENB
Bit 7								Bit 0
The ICNTRL register contains the following bits:
LPEN		L	Port	Interrupt		Enable (Multi-Input
		Wake-up/Interrupt)
T0PND		Timer T0		Interrupt pending
T0EN		Timer T0		Interrupt Enable (Bit 12 toggle)
µWPND		MICROWIRE/PLUS interrupt pending
µWEN		Enable MICROWIRE/PLUS interrupt

T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge

T1ENB Timer T1 Interrupt Enable for T1B Input capture edge

T2CNTRL Register (Address X©00C6)

T2C3	T2C2		T2C1	T2C0		T2PNDA		T2ENA	T2PNDB	T2ENB
Bit 7										Bit 0
The T2CNTRL register contains the following bits:
T2C3		Timer T2 mode control bit
T2C2		Timer T2 mode control bit
T2C1		Timer T2 mode control bit
T2C0		Timer		T2	Start/Stop			control in		timer
		modes 1 and 2, Timer T2 Underflow Interrupt
		Pending Flag in timer mode 3
T2PNDA		Timer T2 Interrupt Pending Flag (Autoreload
		RA in mode 1, T2 Underflow in mode 2, T2A
		capture edge in mode 3)
T2ENA		Timer T2 Interrupt Enable for Timer Underflow
		or T2A Input capture edge
T2PNDB		Timer T2 Interrupt Pending Flag for T2B cap-
		ture edge
T2ENB		Timer T2 Interrupt Enable for T2B Input capture
		edge
HSTCR Register (Address X©00AF)
				Reserved						T2HS
Bit 7										Bit 0

The HSTCR register contains the following bits:

T2HS Places Timer T2 in High Speed Mode.

ITMR Register (Address X©00CF)

	LSON	HSON	DCEN	CCKS	RSVD	ITSEL2	ITSEL1	ITSEL0
				EL
	Bit 7							Bit 0

The ITMR register contains the following bits:

LSON	Turns the low speed oscillator on or off.
HSON	Turns the high speed oscillator on or off.
DCEN	Selects the high speed oscillator or the low
	speed oscillator as the Idle Timer Clock.

CCKSEL Selects the high speed oscillator or the low speed oscillator as the primary CPU clock.

RSVD	This bit is reserved and must be 0.
ITSEL2	Idle Timer period select bit.
ITSEL1	Idle Timer period select bit.
ITSEL0	Idle Timer period select bit.

ENAD Register (Address X©00CB)

ADCH3	ADCH2	ADCH1	ADCH0	ADMOD	MUX	PSC	ADBSY
	Channel Select			Mode	Mux Out	Prescale	Busy
				Select
Bit 7							Bit 0

The ENAD register contains the following bits:

ADCH3 ADC channel select bit

ADCH2 ADC channel select bit

ADCH1 ADC channel select bit

ADCH0 ADC channel select bit

ADMOD Places the ADC in single-ended or differential mode.

MUX	Enables the ADC multiplexor output.
PSC	Switches the ADC clock between a divide by one
	or a divide by sixteen of MCLK.
ADBSY	Signifies that the ADC is currently busy perform-
	ing a conversion. When set by the user, starts a
	conversion.

5.0In-System Programming

5.1INTRODUCTION

This device provides the capability to program the program memory while installed in an application board. This feature is called In System Programming (ISP). It provides a means of ISP by using the MICROWIRE/PLUS, or the user can provide his own, customized ISP routine. The factory installed ISP uses the MICROWIRE/PLUS port. The user can provide his own ISP routine that uses any of the capabilities of the device, such as USART, parallel port, etc.

5.2 FUNCTIONAL DESCRIPTION

The organization of the ISP feature consists of the user flash program memory, the factory boot ROM, and some registers dedicated to performing the ISP function. See Figure 13 for a simplified block diagram. The factory installed ISP that uses MICROWIRE/PLUS is located in the Boot ROM. The size of the Boot ROM is 1k bytes and also contains code to facilitate in system emulation capability. If a user chooses to write his own ISP routine, it must be located in the flash program memory.

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5.0 In-System Programming (Continued)

20022517

FIGURE 13. Block Diagram of ISP

As described in 4.5 OPTION REGISTER, there is a bit, FLEX, that controls whether the device exits RESET executing from the flash memory or the Boot ROM. The user must program the FLEX bit as appropriate for the application. In the erased state, the FLEX bit = 0 and the device will power-up executing from Boot ROM. When FLEX = 0, this assumes that either the MICROWIRE/PLUS ISP routine or external programming is being used to program the device. If using the MICROWIRE/PLUS ISP routine, the software in the boot ROM will monitor the MICROWIRE/PLUS for commands to program the flash memory. When programming the flash program memory is complete, the FLEX bit will have to be programmed to a 1 and the device will have to be reset, either by pulling external Reset to ground or by a MICROWIRE/PLUS ISP EXIT command, before execution from flash program memory will occur.

If FLEX = 1, upon exiting Reset, the device will begin executing from location 0000 in the flash program memory. The assumption, here, is that either the application is not using ISP, is using MICROWIRE/PLUS ISP by jumping to it within the application code, or is using a customized ISP routine. If a customized ISP routine is being used, then it must be programmed into the flash memory by means of the MICROWIRE/PLUS ISP or external programming as described in the preceding paragraph.

5.3 REGISTERS

cleared to 00 on Reset. These registers can be loaded from either flash program memory or Boot ROM and must be maintained for the entire duration of the operation.

Note: The actual memory address of the Option Register is 0x3FFF (hex), however the MICROWIRE/PLUS ISP routines require the address FFFF (hex) to be used to read the Option Register when the Flash Memory is secured.

TABLE 5. High Byte of ISP Address

ISPADHi

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Addr 15	Addr 14	Addr 13	Addr 12	Addr 11	Addr 10	Addr 9	Addr 8

TABLE 6. Low Byte of ISP Address

ISPADLO

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Addr 7	Addr 6	Addr 5	Addr 4	Addr 3	Addr 2	Addr 1	Addr 0

5.3.2 ISP Read Data Register

The Read Data Register (ISPRD) contains the value read back from a read operation. This register can be accessed from either flash program memory or Boot ROM. This register is undefined on Reset.

There are six registers required to support ISP: Address			TABLE 7. ISP Read Data Register
Register Hi byte (ISPADHI), Address Register Low byte
(ISPADLO), Read Data Register (ISPRD), Write Data Reg-					ISPRD
ister (ISPWR), Write Timing Register (PGMTIM), and the	Bit 7	Bit 6		Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Control Register (ISPCNTRL). The ISPCNTRL Register is	Bit7	Bit6		Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
not available to the user.

5.3.1 ISP Address Registers

The address registers (ISPADHI & ISPADLO) are used to specify the address of the byte of data being written or read. For page erase operations, the address of the beginning of the page should be loaded. For mass erase operations, 0000 must be placed into the address registers. When reading the Option register, FFFF (hex) should be placed into the address registers. Registers ISPADHI and ISPADLO are

5.3.3 ISP Write Data Register

The Write Data Register (ISPWR) contains the data to be written into the specified address. This register is undetermined on Reset. This register can be accessed from either flash program memory or Boot ROM. The Write Data register must be maintained for the entire duration of the operation.

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5.0 In-System Programming

(Continued)

TABLE 8. ISP Write Data Register

ISPWR

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0

5.3.4 ISP Write Timing Register

The Write Timing Register (PGMTIM) is used to control the width of the timing pulses for write and erase operations. The value to be written into this register is dependent on the

frequency of CKI and is shown in Table 9. This register must be written before any write or erase operation can take place. It only needs to be loaded once, for each value of CKI frequency. This register can be loaded from either flash program memory or Boot ROM and must be maintained for the entire duration of the operation. The MICROWIRE/PLUS ISP routine that is resident in the boot ROM requires that this Register be defined prior to any access to the Flash memory. Refer to 5.7 MICROWIRE/PLUS ISP for more information on available ISP commands. On Reset, the PGMTIM register is loaded with the value that corresponds to 10 MHz frequency for CKI.

TABLE 9. PGMTIM Register Format

PGMTIM

			Register Bit					CKI Frequency Range
7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	1	25 kHz±33.3 kHz
0	0	0	0	0	0	1	0	37.5 kHz±50 kHz
0	0	0	0	0	0	1	1	50 kHz±66.67 kHz
0	0	0	0	0	1	0	0	62.5 kHz±83.3 kHz
0	0	0	0	0	1	0	1	75 kHz±100 kHz
0	0	0	0	0	1	1	1	100 kHz±133 kHz
0	0	0	0	1	0	0	0	112.5 kHz±150 kHz
0	0	0	0	1	0	1	1	150 kHz±200 kHz
0	0	0	0	1	1	1	1	200 kHz±266.67 kHz
0	0	0	1	0	0	0	1	225 kHz±300 kHz
0	0	0	1	0	1	1	1	300 kHz±400 kHz
0	0	0	1	1	1	0	1	375 kHz±500 kHz
0	0	1	0	0	1	1	1	500 kHz±666.67 kHz
0	0	1	0	1	1	1	1	600 kHz±800 kHz
0	0	1	1	1	1	1	1	800 kHz±1.067 MHz
0	1	0	0	0	1	1	1	1 MHz±1.33 MHz
0	1	0	0	1	0	0	0	1.125 MHz±1.5 MHz
0	1	0	0	1	0	1	1	1.5 MHz±2 MHz
0	1	0	0	1	1	1	1	2 MHz±2.67 MHz
0	1	0	1	0	1	0	0	2.625 MHz±3.5 MHz
0	1	0	1	1	0	1	1	3.5 MHz±4.67 MHz
0	1	1	0	0	0	1	1	4.5 MHz±6 MHz
0	1	1	0	1	1	1	1	6 MHz±8 MHz
0	1	1	1	1	0	1	1	7.5 MHz±10 MHz
R	R/W	R/W	R/W	R/W	R/W	R/W	R/W

5.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM

When using ISP, at some point, it will be necessary to maneuver between the flash program memory and the Boot ROM, even when using customized ISP routines. This is because it's not possible to execute from the flash program memory while it's being programmed.

Two instructions are available to perform the jumping back and forth: Jump to Boot (JSRB) and Return to Flash (RETF). The JSRB instruction is used to jump from flash memory to Boot ROM, and the RETF is used to return from the Boot ROM back to the flash program memory. See 14.0 Instruction Set for specific details on the operation of these instructions.

The JSRB instruction must be used in conjunction with the Key register. This is to prevent jumping to the Boot ROM in the event of run-away software. For the JSRB instruction to actually jump to the Boot ROM, the Key bit must be set. This is done by writing the value shown in Table 10 to the Key register. The Key is a 6 bit key and if the key matches, the KEY bit will be set for 8 instruction cycles. The JSRB instruction must be executed while the KEY bit is set. If the KEY does not match, then the KEY bit will not be set and the JSRB will jump to the specified location in the flash memory. In emulation mode, if a breakpoint is encountered while the KEY is set, the counter that counts the instruction cycles will be frozen until the breakpoint condition is cleared. If an interrupt occurs while the key is set, the key will expire

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