NSC CLC522MDC, CLC522AMC, CLC522AJP, CLC522AJE-TR13, CLC522AJE Datasheet

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CLC522

Wideband Variable-Gain Amplifier

General Description

The CLC522 variable gain amplifier (VGA) is a dc-coupled, twoquadrant multiplier with differential voltage inputs and a single-ended voltage output. Two input buffers and an output operational amplifer are integrated with the multiplier core to make the CLC522 a complete VGA system that does not require external buffering.

The CLC522 provides the flexibility of externally setting the maximum gain with only two external resistors. Greater than 40dB gain control is easily achieved through a single high impedance voltage input. The CLC522 provides a linear (in Volts per Volt) relationship between the amplifier's gain and the gain-control input voltage.

The CLC522's maximum gain may be set anywhere over a nominal range of 2V/V to 100V/V. The gain control input then provides attenuation from the maximum setting. For example, set for a maximum gain of 100V/V, the CLC522 will provide a 100V/V to 1V/V gain control range by sweeping the gain control input voltage from +1 to -0.98V.

Set at a maximum gain of 10V/V, the CLC522 provides a 165MHz signal channel bandwidth and a 165MHz gain control bandwidth. Gain nonlinearity over a 40dB gain range is 0.5% and gain accuracy at AVmax = 10V/V is typically ±0.3%.

June 1999

Features

■330MHz signal bandwidth: Avmax = 2

■165MHz gain-control bandwidth

■0.3° to 60MHz linear phase deviation

■0.04% (-68dB) signal-channel non-linearity

■>40dB gain-adjustment range

■Differential or single-end voltage inputs

■Single-ended voltage output

Applications

■Variable attenuators

■Pulse amplitude equalizers

■HF modulators

■Automatic gain control & leveling loops

■Video production switching

■Differential line receivers

■Voltage controlled filters

Gain vs. Gain Control Voltage (Vg)

10
Gain(V/V)
0
-1.1	Gain Control Voltage, Vg (Volts)	1.1

CLC522

Amplifier Gain-Variable Wideband

	Typical Application							Pinout
	2nd Order Tuneable Bandpass Filter
								DIP & SOIC
					s	1
				1
	Vo		−		CRb
		=			1		k
	Vin	n s2 + s				+
							2	2
					CRb		C Ry
	k = 185. Rf , Q =				k Rb , ω o =			k
			Rg		Ry			CRy

1999 National Semiconductor Corporation

http://www.national.com

Printed in the U.S.A.

CLC522 Electrical Characteristics (VCC = ±5V; AVmax = +10; Rf =1kΩ; Rg =182W; RL = 100Ω; Vg=+1.1V)

PARAMETERS			CONDITIONS			TYP		MIN/MAX RATINGS					UNITS		NOTES
Ambient Temperature			AJ			+25		+25	0 to +70	-40 to +85			°C		1
FREQUENCY DOMAIN RESPONSE
	-3dB bandwidth		Vout < 0.5Vpp			165		120	115		110		MHz
			Vout < 5.0Vpp			150		100	95		90		MHz
	gain control bandwidth		Vout < 0.5Vpp			165		120	115		110		MHz		3
	gain flatness		Vout < 0.5Vpp
		peaking	DC to 30MHz			0		0.1	0.1		0.1		dB
		rolloff	DC to 30MHz			0.05		0.25	0.25		0.4		dB
	linear phase deviation		DC to 60MHz			0.3		1.0	1.1		1.2		°
	feedthrough		30MHz			- 62		- 57	- 57		-57		dB		4
	TIME DOMAIN RESPONSE
	rise and fall time		0.5V step			2.2		2.9	3.0		3.2		ns
			5.0V step			3.0		5.0	5.0		5.0		ns
	settling time		2.0V step to 0.1%			12		18	18		18		ns
	overshoot		0.5V step			2		15	15		15		%
	slew rate		4.0V step			2000		1400	1400		1400		V/µs
	DISTORTION AND NOISE RESPONSE
	2nd	harmonic distortion	2Vpp, 20MHz			- 50		- 44	- 44		-44		dBc
	3rd	harmonic distortion	2Vpp, 20MHz			- 65		- 58	- 56		-54		dBc
	equivalent input noise		1 to	200MHz		5.8		6.2	6.5		6.8		nV/√Hz
		noise floor	1 to	200MHz		- 152		- 150	- 149	-	149		dBm1Hz
GAIN ACCURACY
	signal channel nonlinearity (SGNL)		Vout = ±2Vpp			0.04		0.1	0.1		0.1		%		2
	gain control nonlinearity (GCNL)		full range			0.5		2.0	2.2		3.0		%		2
	gain error (GACCU)		AVmax=+10			± 0.0		± 0.5	± 0.5	±	1.0		dB		2
	Vg high					+ 990		+ 990±60	+ 990±60	+	990±60		mV
		low				- 975		- 975±80	- 975±80	- 975±80			mV
	STATIC DC PERFORMANCE
	Vin	voltage range	common mode			± 2.2		± 1.2	± 1.2	±	1.4		V
		bias current				9		21	26		45		µA		2
		average drift				65		---	175		275		nA/°C
		offset current				0.2		2.0	3.0		4.0		µA
		average drift				5		---	30		40		nA/°C
		resistance				1500		650	450		175		kΩ
		capacitance				1.0		2.0	2.0		2.0		pF
	Vg	bias current				15		38	47		82		µA
		average drift				125		---	300		600		nA/°C
		resistance				100		38	30		15		kΩ
		capacitance				1.0		2.0	2.0		2.0		pF
	output voltage range		RL= ∞			± 4.0		± 3.7	± 3.6	±	3.5		V
		current				± 70		± 47	± 40	±	25		mA
		offset voltage	AVmax=+10			25		85	95		120		mV		2
		average drift				100		---	350		400		µV/°C
		resistance				0.1		0.2	0.3		0.6		Ω
	IRgmax					1.8		1.37	1.26		1.15		mA
	power supply sensitivity		output referred			10		40	40		40		mV/V
	common-mode rejection ratio		input referred			70		59	59		59		dB
	supply current		RL= ∞			46		61	62		63		mA		2

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.

Absolute Maximum Ratings

supply voltage	±7V
short circuit current	80mA
common-mode input voltage	±Vcc
maximum junction temperature	+150° C
storage temperature	-65°C to+150°C
lead temperature (soldering 10 sec)	+300°C
transistor count	74

Notes

1)AJE (SOIC) is tested/guaranteed with Rf=866Ω and Rg= 165Ω.

2)J-level, spec is 100% tested at +25°C.

3)Specified with Vin = 0.2V and Vg < 0.5Vpp.

4)Feedtrough is specified at max. attenuation (i.e Vg =-1.1V)

Ordering Information

Model	Temperature Range	Description
CLC522AJP	-40°C to +85°C	14-pin PDIP
CLC522AJE	-40°C to +85°C	14-pin SOIC
CLC522ALC	-40°C to +85°C	dice
CLC522AMC	-55°C to +125°C	dice, MIL-STD-883

Package Thermal Resistance

Package	θJC	θJA
Plastic (AJP)	55°C/W	100°C/W
Surface Mount (AJE)	35°C/W	105°C/W
CerDIP	40°C/W	95°C/W

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Normalized Magnitude (1dB/div)

CLC522 Typical Performance (TA=+25°C, Vcc=±5V, Av=+10, Vg=1.1V, RL=100Ω; unless noted)

Frequency Response (AVmax=2)

Frequency Response (AVmax=10)

Frequency Response (AVmax=100)

Gain		Vout = 2Vpp	Phase(45/div)°	(1dB/div)	Gain	Vout = 500m Vpp	Phase(45/div)°	(1dB/div)
	AV=AVmax		-45	Magnitude		AV=AVmax	-45	Magnitude
Phase	(Vg=1.0V)				Phase	(Vg=1.0V)
			0				0
				Normalized				Normalized
Rg=2kΩ	(Vg=0V)		-180		Rg=182Ω	(Vg=-0.8V)	-180
			-90				-90
	AV=1		-135			AV=1	-135
Rf = 2.2kΩ			-270		Rf = 1kΩ		-270
1	Frequency (MHz)		500	1		Frequency (MHz)	200

Gain		Vin = 25mVpp	Phase
			(45°
	AV=AVmax
			/div)
	(Vg=1.0V)
Phase			0
			-45
			-90
Rg=10.2Ω	AV=1		-135
	(Vg=-0.98V)		-180
Rf = 715Ω
			-270
1
	Frequency (MHz)		100

PSRR and CMRR (Input Referred)

Feed - through Isolation

	100										55			V o = 2 . 5 V p p
	90	CMRR									40
	80										25
(dB)	70	PSRR									10
	60									)	-5		A V m a x = + 1 0	A V m a x = + 1 0 0
PSRR/CMRR										aGin(dB		= + 2
	30										-50
	50										A V m a x		R f = 1 k Ω	R f = 7 5 0 Ω
											-20
	40										R f = 2 k Ω
											-35
	20										-65
	10										-80
	0										-95		10	10 0
	10	4	10	5	10	6	10	7	10	8	1
													Frequency (MHz)
					Frequency (Hz)

V g =+1.1V

V g =-1 .1V

Magnitude (0.1dB/div)

Gain Flatness & Linear Phase Deviation

Avmax + 10

Deviation

Vg = 1.1V

G a i n

Vo = 2Vpp

Rf = 1k

fromLinear

Phase(0/div)1.°

Ph a s e

0

Frequency (3MHz/div)

30MHz

	SGNL vs. Vg , Gain										Large Signal Frequency Response						Large & Small Signal Pulse Response
	0.20									10			Vo = 5Vpp	Phase(deg)			Avmax = +10
)%(	0.14										Magnitude	Avmax = +2						Vo u t = 5Vp p
	0.18												Vg = 1.1V			3	Vg =1.0V		+.75
	0.16											Rf = 2kΩ
NoelacSln-linearity											Magnitude(1dB/div)					2	Rf = 1kΩ		+.50
										Gai n(VV)/					signalLarge(Volts)
												Avmax = +10				-2			-.50
	0.12											Rf = 1kΩ		0				Vout = 0.5Vpp
	0.10													-45		0			0
	0.08										Phase			-90		-1			-.25
	0.06													-135
l	0.04	SGNL												-180
Fu	0.02							Gain			Avmax = +100			-225		-3			-.75
										0	Rf = 806Ω
	0.00
	0.9	0.7	0.5	0.3	0.1	-0.1	-0.3	-0.5	-0.7	-0.9	0	Frequency (25MHz/div)	250					Ti m e ( 5 n s / d i v )
					Vg (Volts)

Gain Control Settling Time & Delay

Gain Control Channel Feedthrough

.2

Short Term Settling Time

Avmax = + 10

+1V

Vin = 0

.15

AVmax = + 10

V

in = 0.25V DC

2V output step

Vo u t

Vg Input

2.5

0

ErrorSettling(%)

0.1

Vg = 1.0V

(0.5V/div.)Vout

-1V

.05

100mV/div

0

-.05

Vg = 1.0V

Output

-.1

Vg

0

-.15

Vg

= -1.0V

-.2

Time (5ns/div)

Time (5ns/div)

0

Time (10ns/div)

100

Signal Small

(Volts)

Settling Error (%)

	.20			Long Term Settling Time
																	AVmax = + 10
	.15
																	2V output step
	.10																Vg = 1.0V
	.05
	0
	-.05
	-.10
	-.15
	-.20
		- 9			- 8		- 7		- 6		- 5		- 4		- 3			- 2		- 1		0
		1 0			1 0		1 0		1 0		1 0		1 0		1 0			1 0		1 0		1 0

Time (sec)

Settling Time vs. Capacitive Load

	50				Avmax	100			50
				Vg=1.0Volt		= +10			45
SettlingTime,TS,(ns),to0.1%				1kΩ		90
	40	Ω	Ω	Rs		80		SettlingTimeto0.1%(ns)	40
		50
			182	CLC522
				1kΩ	CL	70			35
		Rs
	30					60	Rs(ohms)		30
						50			25
	20					40			20
		Ts				30			15
						20
	10								10
						10			5
	0					0			0
		10		100		1000
			Load Capacitance, CL (pF)

Settling Time vs. Gain

						Vo = 1Vpp
						Rf = 2kΩ
					Avmax = 5
				Avmax = 10
					Avmax = 20
0	2	4	6	8	10	12	14
	Attenuation From Maximum Gain (dB)

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