NSC DAC1232LIN, DAC1232LCWMX, DAC1232LCWM, DAC1232LCN, DAC1232LCJ Datasheet

February 1995

MICRO-DACTM DAC1208/DAC1209/DAC1210/DAC1230/ DAC1231/DAC1232 12-Bit, mP Compatible, Double-Buffered D to A Converters

General Description

The DAC1208 and the DAC1230 series are 12-bit multiplying D to A converters designed to interface directly with a wide variety of microprocessors (8080, 8048, 8085, Z-80, etc.). Double buffering input registers and associated control lines allow these DACs to appear as a two-byte ``stack'' in the system's memory or I/O space with no additional interfacing logic required.

The DAC1208 series provides all 12 input lines to allow single buffering for maximum throughput when used with 16-bit processors. These input lines can also be externally configured to permit an 8-bit data interface. The DAC1230 series can be used with an 8-bit data bus directly as it internally formulates the 12-bit DAC data from its 8 input lines. All of these DACs accept left-justified data from the processor.

The analog section is a precision silicon-chromium (Si-Cr) R-2R ladder network and twelve CMOS current switches. An inverted R-2R ladder structure is used with the binary weighted currents switched between the IOUT1 and IOUT2 maintaining a constant current in each ladder leg independent of the switch state. Special circuitry provides TTL logic input voltage level compatibility.

The DAC1208 series and DAC1230 series are the 12-bit members of a family of microprocessor compatible DACs (MICRO-DACsTM). For applications requiring other resolutions, the DAC1000 series for 10-bit and DAC0830 series for 8-bit are available alternatives.

Features

YLinearity specified with zero and full-scale adjust only

YDirect interface to all popular microprocessors

YDouble-buffered, single-buffered or flow through digital data inputs

YLogic inputs which meet TTL voltage level specs (1.4V logic threshold)

YWorks with g10V referenceÐfull 4-quadrant multiplication

YOperates stand-alone (without mP) if desired

YAll parts guaranteed 12-bit monotonic

YDAC1230 series is pin compatible with the DAC0830 series 8-bit MICRO-DACs

Key Specifications

Y Current Settling Time	1 ms
Y Resolution	12 Bits
Y Linearity (Guaranteed
over temperature)	10, 11, or 12 Bits of FS
Y Gain Tempco	1.3 ppm/§C
Y Low Power Dissipation	20 mW
Y Single Power Supply	5 VDC to 15 VDC

Typical Application

TL/H/5690 ± 1

TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

MICRO-DACTM is a trademark of National Semiconductor Corp.

DAC1208/DAC1209/DAC1210/DAC1230/DAC1231/DAC1232 DAC-MICRO Converters A to D Buffered-Double Compatible, Pm Bit,-12

C1995 National Semiconductor Corporation

TL/H/5690

RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

(Notes 1 and 2)

Supply Voltage (VCC)	17 VDC
Voltage at Any Digital Input	VCC to GND
Voltage at VREF Input	g25V
Storage Temperature Range	b65§C to a150§C
Package Dissipation at TAe25§C	500 mW
(Note 3)
DC Voltage Applied to IOUT1 or IOUT2	b100 mV to VCC
(Note 4)
ESD Susceptability	800V

Operating Conditions

Lead Temperature (Soldering, 10 sec.)		300§C
Temperature Range		TMIN s TA s TMAX
DAC1208LCJ, DAC1209LCJ,
DAC1210LCJ, DAC1230LCJ,
DAC1231LCJ, DAC1232LCJ,	b40§C s TA s a85§C
DAC1231LIN, DAC1232LIN
DAC1208LCJ-1, DAC1210LCJ-1,
DAC1230LCJ-1, DAC1231LCJ-1,
DAC1232LCJ-1, DAC1231LCN,
DAC1232LCN, DAC1231LCWM,		0§C s TA s a70§C
DAC1232LCWM
Range of VCC		4.75 VDC to 16 VDC
Voltage at Any Digital Input		VCC to GND

Electrical Characteristics

VREFe10.000 VDC, VCCe11.4 VDC to 15.75 VDC unless otherwise noted. Boldface limits apply from TMIN to TMAX (see Note 13); all other limits TA e TJ e 25§C.

					Typ	Tested	Design
	Parameter	Conditions		Notes		Limit	Limit	Units
					(Note 10)
						(Note 5)	(Note 6)
	Resolution				12	12	12	Bits
	Linearity Error	Zero and Full-Scale		4, 7, 13
	(End Point Linearity)	Adjusted
		DAC1208, DAC1230				g0.018	g0.018	% of FSR
		DAC1209, DAC1231				g0.024	g0.024	% of FSR
		DAC1210, DAC1232				g0.050	g0.05	% of FSR
	Differential Non-Linearity	Zero and Full-Scale		4, 7, 13
		Adjusted
		DAC1208, DAC1230				g0.018	g0.018	% of FSR
		DAC1209, DAC1231				g0.024	g0.024	% of FSR
		DAC1210, DAC1232				g0.050	g0.05	% of FSR
	Monotonicity			4	12	12	12	Bits
	Gain Error (Min)	Using Internal RFb		7	b0.1	0.0		% of FSR
	Gain Error (Max)	Vref e g10V, g1V		7	b0.1	b0.2		% of FSR
	Gain Error Tempco			7	g1.3		g6.0	ppm of FS/§C
	Power Supply Rejection	All Digital Inputs		7	g3.0	g30		ppm of FSR/V
		Latched High
	Reference Input Resistance (Min)			13	15	10	10	kX
	Reference Input Resistance (Max)				15	20	20
	Output Feedthrough Error	VREFe20 Vp-p, fe100 kHz
		All Data Inputs Latched		9	3.0			mVp-p
		Low
	Output Capacitance	All Data Inputs	IOUT1				200	pF
		Latched High	IOUT2				70	pF
		All Data Inputs	IOUT1				70	pF
		Latched Low	IOUT2				200	pF
	Supply Current Drain			13		2.0	2.5	mA
	Output Leakage Current
	IOUT1	All Data Inputs Latched		11, 13	0.1	15	15	nA
		Low
	IOUT2	All Data Inputs Latched		11, 13	0.1	15	15	nA
		High
	Digital Input Threshold	Low Threshold		13		0.8	0.8	VDC
		High Threshold		13		2.2	2.2	VDC
	Digital Input Currents	Digital Inputs k0.8V		13		b200	b200	mADC
		Digital Inputs l2.2V		13		10	10	mADC

2

Electrical Characteristics (Continued)

VREF e 10.000 VDC, VCC e 11.4 VDC to 15.75 VDC unless otherwise noted. Boldface limits apply from TMIN to TMAX (see Note 13); all other limits TA e TJ e 25§C.

				See	Typ	Tested	Design
	Symbol	Parameter	Conditions			Limit	Limit	Units
				Note	(Note 10)
						(Note 5)	(Note 6)
	AC CHARACTERISTICS
	ts	Current Setting Time	VIL e 0V, VIH e 5V		1.0			ms
	tW	Write and XFER	VIL e 0V, VIH e 5V	8	50		320
		Pulse Width Min.					320
	tDS	Data Setup Time Min.	VIL e 0V, VIH e 5V		70		320
							320
	tDH	Data Hold Time Min.	VIL e 0V, VIH e 5V		30		90	ns
							90
	tCS	Control Setup Time Min.	VIL e 0V, VIH e 5V		60		320
							320
	tCH	Control Hold Time Min.	VIL e 0V, VIH e 5V		0		10

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify the power dissipation) removes concern for heat sinking.

Note 4: Both IOUT1 and IOUT2 must go to ground or the virtual ground of an operational amplifier. The linearity error is degraded by approximately VOSdVREF. For example, if VREFe10V then a 1 mV offset, VOS, on IOUT1 or IOUT2 will introduce an additional 0.01% linearity error.

Note 5: Tested and guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 6: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Guaranteed for VCC e 11.4V to 15.75V and VREF e b10V to a10V.

Note 7: The unit FSR stands for full-scale range. Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular VREF value to indicate the true performance of the part. The Linearity Error specification of the DAC1208 is 0.012% of FSR(max). This guarantees that after performing a zero and full-scale adjustment, the plot of the 4096 analog voltage outputs will each be within 0.012% c VREF of a straight line which passes through zero and full-scale. The unit ppm of FSR(parts per million of full-scale range) and ppm of FS(parts per million of full-scale) are used for convenience to define specs of very small percentage values, typical of higher accuracy converters. In this instance, 1 ppm of FSReVREF/106 is the conversion factor to provide an actual output voltage quantity. For example, the gain error tempco spec of g6 ppm of FS/§C represents a worst-case full-scale gain error change with temperature from b40§C to a85§C of g(6)(VREF/106)(125§C) or g0.75 (10b3) VREF which is g0.075% of VREF.

Note 8: This spec implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (tW) of 320 ns. A typical part will operate with tW of only 100 ns. The entire write pulse must occur within the valid data interval for the specified tW, tDS, tDH and tS to apply.

Note 9: To achieve this low feedthrough in the D package, the user must ground the metal lid. If the lid is left floating the feedthrough is typically 6 mV.

Note 10: Typicals are at 25§C and represent the most likely parametric norm.

Note 11: A 10 nA leakage current with RFbe20k and VREFe10V corresponds to a zero error of (10c10b9c20c103)c100% 10V or 0.002% of FS. Note 12: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 13: Tested limit for b1 suffix parts applies only at 25§C.

Connection Diagrams

Dual-In-Line Package

Dual-In-Line Package

TL/H/5690 ± 2

See Ordering Information

3

Switching Waveforms

		TL/H/5690 ± 3
Typical Performance Characteristics
Digital Input Threshold	Digital Input Threshold vs	Gain and Linearity Error
vs VCC	Temperature	Variation vs Temperature

TL/H/5690 ± 4

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Definition of Package Pinouts

CONTROL SIGNALS (all control signals are level actuated)

CS: Chip Select (active low). The CS will enable WR1.

WR1: Write 1. The active low WR1 is used to load the digital data bits (DI) into the input latch. The data in the input latch is latched when WR1 is high. The 12-bit input latch is split into two latches. One holds the first 8 bits, while the other holds 4 bits. The Byte 1/Byte 2 control pin is used to select both latches when Byte 1/Byte 2 is high or to overwrite the 4-bit input latch when in the low state.

Byte 1/Byte 2: Byte Sequence Control. When this control is high, all 12 locations of the input latch are enabled. When low, only the four least significant locations of the input latch are enabled.

WR2: Write 2 (active low). The WR2 will enable XFER.

XFER: Transfer Control Signal (active low). This signal, in combination with WR2, causes the 12-bit data which is available in the input latches to transfer to the DAC register.

DI0 to DI11: Digital Inputs. DI0 is the least significant digital input (LSB) and DI11 is the most significant digital input (MSB).

IOUT1: DAC Current Output 1. IOUT1 is a maximum for a digital code of all 1s in the DAC# register,J and is zero for all

0s in the DAC register.

IOUT2: DAC Current Output 2. IOUT2 is a constant minus IOUT1, or IOUT1aIOUT2econstant (for a fixed reference voltage). This constant current is

1 VREF c 1 b 4096

divided by the reference input resistance.

RFb: Feedback Resistor. The feedback resistor is provided on the IC chip for use as the shunt feedback resistor for the external op amp which is used to provide an output voltage for the DAC. This on-chip resistor should always be used (not an external resistor) since it matches the resistors in the on-chip R-2R ladder and tracks these resistors over temperature.

VREF: Reference Voltage Input. This input connects an external precision voltage source to the internal R-2R ladder.

VREF can be selected over the range of 10V to b10V. This is also the analog voltage input for a 4-quadrant multiplying

DAC application.

VCC: Digital Supply Voltage. This is the power supply pin for the part. VCC can be from 5 VDC to 15 VDC. Operation is optimum for 15 VDC.

GND: Pins 3 and 12 of the DAC1208, DAC1209, and DAC1210 must be connected to ground. Pins 3 and 10 of

a) End Point Test After Zero and FS Adjust

the DAC1230, DAC1231, and DAC1232 must be connected

to ground. It is important that IOUT1 and IOUT2 are at ground potential for current switching applications. Any difference

of potential (VOS on these pins) will result in a linearity

change of

VOS

3 VREF

For example, if VREF e 10V and these ground pins are 9 mV offset from IOUT1 and IOUT2, the linearity change will be

0.03%.

Definition of Terms

Resolution: Resolution is defined as the reciprocal of the number of discrete steps in the DAC output. It is directly related to the number of switches or bits within the DAC. For example, the DAC1208 has 212 or 4096 steps and therefore has 12-bit resolution.

Linearity Error: Linearity error is the maximum deviation from a straight line passing through the endpoints of the DAC transfer characteristic . It is measured after adjusting for zero and full-scale. Linearity error is a parameter intrinsic to the device and cannot be externally adjusted.

National's linearity test (a) and the best straight line test (b) used by other suppliers are illustrated below. The best straight line (b) requires a special zero and FS adjustment for each part, which is almost impossible for the user to determine. The end point test uses a standard zero FS adjustment procedure and is a much more stringent test for DAC linearity.

Power Supply Sensitivity: Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output.

Settling Time: Full-scale current settling time requires zero to full-scale or full-scale to zero output change. Settling time is the time required from a code transition until the DAC output reaches within g(/2 LSB of the final output value.

Full-Scale Error: Full-scale error is a measure of the output error between an ideal DAC and the actual device output. Ideally, for the DAC1208 or DAC1230 series, full-scale is

VREFb1 LSB. For VREFe10V and unipolar operation, VFULL-SCALEe10.0000Vb2.44 mVe9.9976V. Full-scale error is adjustable to zero.

Differential Non-Linearity: The difference between any two consecutive codes in the transfer curve from the theoretical 1 LSB is differential non-linearity.

Monotonic: If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 12-bit DAC which is monotonic to 12 bits simply means that input increasing digital input codes will produce an increasing analog output.

TL/H/5690 ± 5

b)Shifting FS Adjust to Pass Best Straight Line Test

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Application Hints

1.0 DIGITAL INTERFACE

These DACs are designed to provide all of the necessary digital input circuitry to permit a direct interface to a wide variety of microprocessor systems. The timing and logic level convention of the input control signals allow the DACs to be treated as a typical memory device or I/O peripheral with no external logic required in most systems. Essentially these DACs can be mapped as a two-byte stack in memory (or I/O space) to receive their 12 bits of input data in two successive 8-bit data writing sequences. The DAC1230 series is intended for use in systems with an 8-bit data bus. The DAC1208 series provides all 12 digital input lines which can be externally configured to be controlled from an 8-bit bus or can be driven directly from a 16-bit data bus.

All of the digital inputs to these DACs contain a unique threshold regulator circuit to maintain TTL voltage level compatibility independent of the applied VCC to the DAC. Any input can also be driven from higher voltage CMOS logic levels in non-microprocessor based systems. To prevent damage to the chip from static discharge, all unused digital inputs should be tied to VCC or ground. As a troubleshooting aid, if any digital input is inadvertently left floating, the DAC will interpret the pin as a logic ``1''.

Double buffered digital inputs allow the DAC to internally format the 12-bit word used to set the current switching R- 2R ladder network (see section 2.0) from two 8-bit data write cycles. Figures 1 and 2 show the internal data registers and their controlling logic circuitry. The timing diagrams for updating the DAC output are shown in sections 1.1, 1.2 and 1.3 for three possible control modes. The method used depends strictly upon the particular application.

TL/H/5690 ± 6

FIGURE 2. DAC1230, DAC1231, DAC1232 Functional Diagram

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