NSC DAC1008LCN, DAC1006LCWM, DAC1006LCN Datasheet

January 1995

DAC1006/DAC1007/DAC1008 mP Compatible, Double-Buffered D to A Converters

General Description

The DAC1006/7/8 are advanced CMOS/Si-Cr 10-, 9- and 8-bit accurate multiplying DACs which are designed to interface directly with the 8080, 8048, 8085, Z-80 and other popular microprocessors. These DACs appear as a memory location or an I/O port to the mP and no interfacing logic is needed.

These devices, combined with an external amplifier and voltage reference, can be used as standard D/A converters; and they are very attractive for multiplying applications (such as digitally controlled gain blocks) since their linearity error is essentially independent of the voltage reference. They become equally attractive in audio signal processing equipment as audio gain controls or as programmable attenuators which marry high quality audio signal processing to digitally based systems under microprocessor control.

All of these DACs are double buffered. They can load all 10 bits or two 8-bit bytes and the data format is left justified. The analog section of these DACs is essentially the same as that of the DAC1020.

The DAC1006 series are the 10-bit members of a family of microprocessor-compatible DAC's (MICRO-DACTM's). For applications requiring other resolutions, the DAC0830 series (8 bits) and the DAC1208 and DAC1230 (12 bits) are available alternatives.

	Part Ý	Accuracy	Pin	Description
		(bits)
	DAC1006	10		For left-
	DAC1007	9	20
				justified
	DAC1008	8		data

MICRO-DACTM and BI-FETTM are trademarks of National Semiconductor Corp.

Features

Y Uses easy to adjust END POINT specs, NOT BEST STRAIGHT LINE FIT

YLow power consumption

YDirect interface to all popular microprocessors

YIntegrated thin film on CMOS structure

YDouble-buffered, single-buffered or flow through digital data inputs

YLoads two 8-bit bytes or a single 10-bit word

YLogic inputs which meet TTL voltage level specs (1.4V logic threshold)

YWorks with g10V referenceÐfull 4-quadrant multiplication

YOperates STAND ALONE (without mP) if desired

YAvailable in 0.3× standard 20-pin package

YDifferential non-linearity selection available as special order

Key Specifications

Y Output Current Settling Time	500 ns
Y Resolution	10	bits
Y Linearity	10, 9, and 8	bits
	(guaranteed over temp.)
Y Gain Tempco	b0.0003% of FS/§C
Y Low Power Dissipation	20 mW
(including ladder)
Y Single Power Supply	5 to 15 VDC

Typical Application

DAC1006/1007/1008

OF BUS

SECTION 6.0

TL/H/5688 ± 1

Compatible, Pm DAC1006/DAC1007/DAC1008

Converters A to D Buffered-Double

C1995 National Semiconductor Corporation

TL/H/5688

RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (VCC)		17 VDC
Voltage at Any Digital Input		VCC to GND
Voltage at VREF Input		g25V
Storage Temperature Range	b65§C to a150§C
Package Dissipation at TAe25§C (Note 3)		500 mW
DC Voltage Applied to IOUT1 or IOUT2		b100 mV to VCC
(Note 4)

ESD Susceptibility (Note 11)	800V
Lead Temp. (Soldering, 10 seconds)	260§C
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)	300§C

Operating Ratings (Note 1)

Temperature Range	TMIN s TA s TMAX
Part numbers with	0§C to 70§C
``LCN'' and ``LCWN'' suffix
Voltage at Any Digital Input	VCC to GND

Electrical Characteristics

Tested at VCC e 4.75 VDC and 15.75 VDC, TAe25§C, VREFe10.000 VDC unless otherwise noted

			See	VCCe12VDCg5%				VCCe5VDCg5%
Parameter		Conditions			to 15VDCg5%						Units
			Note
				Min.		Typ.	Max.	Min.	Typ.	Max.
Resolution							10			10	bits
Linearity Error		Endpoint adjust only	4,7
		TMINkTAkTMAX	6
		b10VsVREFsa10V	5
		DAC1006					0.05			0.05	% of FSR
		DAC1007					0.1			0.1	% of FSR
		DAC1008					0.2			0.2	% of FSR
Differential		Endpoint adjust only	4,7
Nonlinearity		TMINkTAkTMAX	6
		b10VsVREFsa10V	5
		DAC1006					0.1			0.1	% of FSR
		DAC1007					0.2			0.2	% of FSR
		DAC1008					0.4			0.4	% of FSR
Monotonicity		TMINkTAkTMAX	4,6
		b10VsVREFsa10V	5
		DAC1006		10				10			bits
		DAC1007		9				9			bits
		DAC1008		8				8			bits
Gain Error		Using internal Rfb
		b10VsVREFsa10V	5	b1.0		g0.3	1.0	b1.0	g0.3	1.0	% of FS
Gain Error Tempco		TMINkTAkTMAX	6			b0.0003	b0.001		b0.0006	b0.002	% of FS/§C
		Using internal Rfb	9
Power Supply		All digital inputs
Rejection		latched high
		VCCe14.5V to 15.5V				0.003	0.008				% FSR/V
		11.5V to 12.5V				0.004	0.010				% FSR/V
		4.75V to 5.25V							0.033	0.10	% FSR/V
Reference Input
Resistance				10		15	20	10	15	20	kX
Output Feedthrough		VREF e 20Vp-p, fe100 kHz
Error		All data inputs				90			90		mVp-p
		latched low
Output	IOUT1	All data inputs				60			60		pF
Capacitance	IOUT2	latched low				250			250		pF
	IOUT1	All data inputs				250			250		pF
	IOUT2	latched high				60			60		pF
Supply Current Drain		TMINsTAsTMAX	6			0.5	3.5		0.5	3.5	mA

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Electrical Characteristics

Tested at VCC e 4.75 VDC and 15.75 VDC, TAe25§C, VREFe10.000 VDC unless otherwise noted (Continued)

					See	VCCe12VDCg5%				VCCe5VDCg5%
Parameter				Conditions			to 15VDCg5%						Units
					Note
						Min.		Typ.	Max.	Min.	Typ.	Max.
Output Leakage				TMINsTAsTMAX	6
Current IOUT1				All data inputs
				latched low	10				200			200	nA
	IOUT2			All data inputs
				latched high					200			200	nA
Digital Input				TMINsTAsTMAX	6
Voltages				Low level
				LCN and LCWM suffix					0.8, 0.8			0.7, 0.8	VDC
				High level (all parts)		2.0				2.0			VDC
Digital Input				TMINsTAsTMAX	6			b40	b150		b40	b150
Currents				Digital inputs k0.8V									mADC
				Digital inputs l2.0V				1.0	a10		1.0	a10	mADC
Current Settling			tS	VILe0V, VIHe5V				500			500		ns
Time
				VILe0V, VIHe5V,
Write and XFER			tW
Pulse Width				TAe25§C	8	150		60		320	200		ns
				TMINsTAsTMAX	9	320		100		500	250		ns
Data Set Up Time			tDS	VILe0V, VIHe5V,
				TAe25§C	9	150		80		320	170		ns
				TMINsTAsTMAX		320		120		500	250		ns
Data Hold Time			tDH	VILeOV, VIHe5V
				TAe25§C	9	200		100		320	220		ns
				TMINsTAsTMAX		250		120		500	320		ns
Control Set Up			tCS	VILe0V, VILe5V,
Time				TAe25§C	9	150		60		320	180		ns
				TMINsTAsTMAX		320		100		500	260		ns
Control Hold Time			tCH	VILe0V, VIHe5V,
				TAe25§C	9	10		0		10	0		ns
				TMINsTAsTMAX		10		0		10	0		ns

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify the power dissipation) removes concern for heat sinking.

Note 4: For current switching applications, both IOUT1 and IOUT2 must go to ground or the ``Virtual Ground'' of an operational amplifier. The linearity error is degraded by approximately VOSdVREF. For example, if VREFe10V then a 1 mV offset, VOS, on IOUT1 or IOUT2 will introduce an additional 0.01% linearity error. Note 5: Guaranteed at VREFeg10 VDC and VREFeg1 VDC.

Note 6: TMINe0§C and TMAXe70§C for ``LCN'' and ``LCWM'' suffix parts.

Note 7: The unit ``FSR'' stands for ``Full Scale Range.'' ``Linearity Error'' and ``Power Supply Rejection'' specs are based on this unit to eliminate dependence on a particular VREF value and to indicate the true performance of the part. The ``Linearity Error'' specification of the DAC1006 is ``0.05% of FSR (MAX).'' This guarantees that after performing a zero and full scale adjustment (See Sections 2.5 and 2.6), the plot of the 1024 analog voltage outputs will each be within 0.05%cVREF of a straight line which passes through zero and full scale.

Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (tW) of 320 ns. A typical part will operate with tW of only 100 ns. The entire write pulse must occur within the valid data interval for the specified tW, tDS, tDH, and tS to apply.

Note 9: Guaranteed by design but not tested.

Note 10: A 200 nA leakage current with Rfbe20K and VREFe10V corresponds to a zero error of (200c10b9c20c103)c100d10 which is 0.04% of FS. Note 11: Human body model, 100 pF discharged through a 1.5 kX resistor.

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Switching Waveforms

TL/H/5688 ± 2

Typical Performance Characteristics

Errors vs. Supply Voltage

Errors vs. Temperature

Write Width, tW

TL/H/5688 ± 3

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Block and Connection Diagrams

DAC1006/1007/1008 (20-Pin Parts)	DAC1006/1007/1008
	(20-Pin Parts)
	Dual-In-Line Package

TL/H/5688 ± 28

Top View

See Ordering Information

TL/H/5688 ± 5

DAC1006/1007/1008ÐSimple Hookup for a ``Quick Look''

TL/H/5688 ± 7

Notes:

1.For VREFeb10.240 VDC the output voltage steps are approximately 10 mV each.

2.SW1 is a normally closed switch. While SW1 is closed, the DAC register is latched and new data can be loaded into the input latch via the 10 SW2 switches.

When SW1 is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SW1 again closes.

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1.0DEFINITION OF PACKAGE PINOUTS

1.1Control Signals (All control signals are level actuated.)

CS: Chip Select Ð active low, it will enable WR.

WR: Write Ð The active low WR is used to load the digital data bits (DI) into the input latch. The data in the input latch is latched when WR is high. The 10-bit input latch is split into two latches; one holds 8 bits and the other holds 2 bits. The Byte1/Byte2 control pin is used to select both input

latches when Byte1/Byte2e1 or to overwrite the 2-bit input latch when in the low state.

Byte1/Byte2: Byte Sequence Control Ð When this control is high, all ten locations of the input latch are enabled. When low, only two locations of the input latch are enabled and these two locations are overwritten on the second byte write. On the DAC1006, 1007, and 1008, the Byte1/Byte2 must be low to transfer the 10-bit data in the input latch to the DAC register.

XFER: Transfer Control Signal, active low Ð This signal, in combination with others, is used to transfer the 10-bit data which is available in the input latch to the DAC register Ð see timing diagrams.

1.2 Other Pin Functions

DIi (ie0 to 9): Digital Inputs Ð DI0 is the least significant bit (LSB) and DIg is the most significant bit (MSB).

IOUT1: DAC Current Output 1 Ð IOUT1 is a maximum for a digital input code of all 1s and is zero for a digital input code

of all 0s.

IOUT2: DAC Current Output 2 Ð IOUT2 is a constant minus IOUT1, or

IOUT1aIOUT2e1023 VREF

1024 R where R j 15 kX.

a. End Point Test After Zero and FS Adj.

RFB: Feedback Resistor Ð This is provided on the IC chip for use as the shunt feedback resistor when an external op amp is used to provide an output voltage for the DAC. This on-chip resistor should always be used (not an external resistor) because it matches the resistors used in the on-chip R-2R ladder and tracks these resistors over temperature.

VREF: Reference Voltage Input Ð This is the connection for the external precision voltage source which drives the R-2R ladder. VREF can range from b10 to a10 volts. This is also the analog voltage input for a 4-quadrant multiplying DAC application.

VCC: Digital Supply Voltage Ð This is the power supply pin for the part. VCC can be from a5 to a15 VDC. Operation is optimum for a15V. The input threshold voltages are nearly independent of VCC. (See Typical Performance Characteristics and Description in Section 3.0, T2L compatible logic inputs.)

GND: Ground Ð the ground pin for the part.

1.3 Definition of Terms

Resolution: Resolution is directly related to the number of switches or bits within the DAC. For example, the DAC1006 has 210 or 1024 steps and therefore has 10-bit resolution.

Linearity Error: Linearity error is the maximum deviation from a straight line passing through the endpoints of the DAC transfer characteristic. It is measured after adjusting for zero and full-scale. Linearity error is a parameter intrinsic to the device and cannot be externally adjusted.

National's linearity test (a) and the ``best straight line'' test

(b) used by other suppliers are illustrated below. The ``best straight line'' requires a special zero and FS adjustment for each part, which is almost impossible for user to determine. The ``end point test'' uses a standard zero and FS adjustment procedure and is a much more stringent test for DAC linearity.

Power Supply Sensitivity: Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output (which is the worst case).

b. Best Straight Line

TL/H/5688 ± 8

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Settling Time: Settling time is the time required from a code transition until the DAC output reaches within g(/2 LSB of the final output value. Full-scale settling time requires a zero to full-scale or full-scale to zero output change.

Full-Scale Error: Full scale error is a measure of the output error between an ideal DAC and the actual device output. Ideally, for the DAC1006 series, full-scale is VREFb1 LSB.

For VREFeb10V and unipolar operation, VFULL-SCA- LEe10.0000V b9.8mVe9.9902V. Full-scale error is adjust-

able to zero.

Monotonicity: If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 10-bit DAC with 10-bit monotonicity will produce an increasing analog output when all 10 digital inputs are exercised. A 10-bit DAC with 9-bit monotonicity will be monotonic when only the most significant 9 bits are exercised. Similarly, 8-bit monotonicity is guaranteed when only the most significant 8 bits are exercised.

2.0 DOUBLE BUFFERING

These DACs are double-buffered, microprocessor compatible versions of the DAC1020 10-bit multiplying DAC. The addition of the buffers for the digital input data not only allows for storage of this data, but also provides a way to assemble the 10-bit input data word from two write cycles when using an 8-bit data bus. Thus, the next data update for the DAC output can be made with the complete new set of 10-bit data. Further, the double buffering allows many DACs in a system to store current data and also the next data. The updating of the new data for each DAC is also not time critical. When all DACs are updated, a common strobe signal can then be used to cause all DACs to switch to their new analog output levels.

3.0 TTL COMPATIBLE LOGIC INPUTS

To guarantee TTL voltage compatibility of the logic inputs, a novel bipolar (NPN) regulator circuit is used. This makes the input logic thresholds equal to the forward drop of two diodes (and also matches the temperature variation) as occurs naturally in TTL. The basic circuit is shown in Figure 1 . A curve of digital input threshold as a function of power supply voltage is shown in the Typical Performance Characteristics section.

4.0 APPLICATION HINTS

The DC stability of the VREF source is the most important factor to maintain accuracy of the DAC over time and temperature changes. A good single point ground for the analog signals is next in importance.

These MICRO-DAC converters are CMOS products and reasonable care should be exercised in handling them prior to final mounting on a PC board. The digital inputs are protected, but permanent damage may occur if the part is subjected to high electrostatic fields. Store unused parts in conductive foam or anti-static rails.

4.1 Power Supply Sequencing & Decoupling

Some IC amplifiers draw excessive current from the Analog inputs to Vb when the supplies are first turned on. To prevent damage to the DAC Ð an external Schottky diode con-

nected from IOUT1 or IOUT2 to ground may be required to prevent destructive currents in IOUT1 or IOUT2. If an LM741

or LF356 is used Ð these diodes are not required.

The standard power supply decoupling capacitors which are used for the op amp are adequate for the DAC.

TL/H/5688 ± 9

FIGURE 1. Basic Logic Threshold Loop

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