NSC COPEK988V, COPEK988N, COPEK984N, COPEK888V, COPEK888N Datasheet

OBSOLETE

January 2000

COP888EK

8-Bit CMOS ROM Based Microcontrollers with 8k Memory, Comparator, and Single-slope A/D Capability

General Description

The COP888EK ROM based microcontrollers are highly integrated COP8™ Feature core devices with 8k memory and advanced features including a Multi-Input Comparator and Single-slope A/D capability. These single-chip CMOS devices are suited for applications requiring a full featured, low EMI controller with an analog comparator, current source, and voltage reference. The COP87L88EK/RK Family devices are pin and software compatible (different VCC range) 16k or 32k OTP (One Time Programmable) versions for preproduction, and for use with a range of COP8 software and hardware development tools.

Family features include an 8-bit memory mapped architecture, 10 MHz CKI with 1µs instruction cycle, three multifunction 16-bit timer/counters with PWM, MICROWIRE/ PLUS™ serial I/O, one analog comparator with seven input multiplexor, an analog current source and VCC reference, two power saving HALT/IDLE modes, idle timer, MIWU, high current outputs, software selectable I/O options, WATCHDOG™ timer and Clock Monitor, Low EMI 2.5V to 6.0V operation and 28/40/44 pin packages.

Devices included in this datasheet are:

Device	Memory (bytes)	RAM (bytes)	I/O Pins		Packages	Temperature		Comments
COP684EK	8k ROM	256	24	28	DIP/SOIC	-55 to +125ÊC	4.5V	- 5.5V
COP884EK	8k ROM	256	24	28	DIP/SOIC	-40 to +85ÊC
COP984EK	8k ROM	256	24	28	DIP/SOIC	0 to +70ÊC	2.5V	- 4.0V, EKH=4.0V - 6.0V
COP688EK	8k ROM	256	36/40	40	DIP, 44 PLCC	-55 to +125ÊC	4.5V	- 5.5V
COP888EK	8k ROM	256	36/40	40	DIP, 44 PLCC	-40 to +85ÊC
COP988EK	8k ROM	256	36/40	40	DIP, 44 PLCC	0 to +70ÊC	2.5V	- 4.0V, EKH=4.0V - 6.0V

Key Features

nAnalog function block with

ÐAnalog comparator with seven input multiplexor

ÐConstant current source and V CC/2 reference

nThree 16-bit timers, each with two 16-bit registers supporting:

ÐProcessor Independent PWM mode

ÐExternal Event counter mode

ÐInput Capture mode

n8 kbytes of on-chip ROM

n256 bytes of on-chip RAM

Additional Peripheral Features

nIdle Timer

nMulti-Input Wake Up (MIWU) with optional interrupts (8)

nWATCHDOG and Clock Monitor logic

nMICROWIRE/PLUS serial I/O

I/O Features

nSoftware selectable I/O options (TRI-STATE™ Output, Push-Pull Output, Weak Pull-Up Input, High Impedance Input)

nHigh current outputs

nSchmitt trigger inputs on Port G and L

nPackages: 44 PLCC with 40 I/O pins, 40 DIP with 36 I/O pins, and 28 DIP/SO with 24 I/O pins

CPU/Instruction Set Feature

n1 µs instruction cycle time

nTwelve multi-source vectored interrupts servicing

ÐExternal Interrupt with selectable edge

ÐIdle Timer T0

ÐThree Timers (Each with 2 interrupts)

ÐMICROWIRE/PLUS

ÐMulti-Input Wake Up

ÐSoftware Trap

ÐDefault VIS (default interrupt)

nVersatile and easy to use instruction set

n8-bit Stack Pointer (SP) Ð stack in RAM

nTwo 8-bit Register Indirect Data Memory Pointers (B, X)

Fully Static CMOS

nSingle supply operation: 2.5V to 6.0V

nTemperature ranges: 0ÊC to +70ÊC, −40ÊC to +85ÊC, and −55ÊC to +125ÊC

COP8™ , MICROWIRE/PLUS™ , and WATCHDOG™ are trademarks of National Semiconductor Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation.

iceMASTER® is a registered trademark of MetaLink Corporation.

slope-Single	8 COP888EK
A/D	Bit-
Capability	ROM CMOS
	and Comparator, Memory, 8k with Microcontrollers Based

© 2000 National Semiconductor Corporation

DS012094

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COP888EK

Development Support		n Real time emulation and full program debug offered by
n Emulation and OTP devices		MetaLink Development System
Block Diagram

DS012094-1

FIGURE 1. Block Diagram

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2

Connection Diagrams

Plastic Chip Carrier	Dual-In-Line Package

DS012094-2

Top View

Order Number COP688EK-XXX/V, COP888EK-XXX/V,

COP988EK-XXX/V or COP988EKH-XXX/V

See NS Plastic Chip Package Number V44A

DS012094-3

Top View

Order Number COP688EK-XXX/N, COP888EK-XXX/N,

COP988EK-XXX/N or COP988EKH-XXX/N

See NS Molded Package Number N40A

Dual-In-Line Package

DS012094-4

Top View

Order Number COP684EK-XXX/N, COP884EK-XXX/N, COP984EK-XXX/N or COP984EKH-XXX/N See NS Molded Package Number N28B

Order Number COP684EK-XXX/WM, COP884EK-XXX/WM, COP984EK-XXX/WM or COP984EKH-XXX/WM See NS Molded Package Number M28B

FIGURE 2. Connection Diagrams

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COP888EK

Connection Diagrams (Continued)

Pinouts for 28-, 40and 44-Pin Packages

	Port		Type	Alt. Fun	Alt. Fun	28-Pin	40-Pin	44-Pin
						Pack.	Pack.	Pack.
	L0		I/O	MIWU		11	17	17
	L1		I/O	MIWU		12	18	18
	L2		I/O	MIWU		13	19	19
	L3		I/O	MIWU		14	20	20
	L4		I/O	MIWU	T2A	15	21	25
	L5		I/O	MIWU	T2B	16	22	26
	L6		I/O	MIWU	T3A	17	23	27
	L7		I/O	MIWU	T3B	18	24	28
	G0		I/O	INT		25	35	39
	G1		WDOUT			26	36	40
	G2		I/O	T1B		27	37	41
	G3		I/O	T1A		28	38	42
	G4		I/O	SO		1	3	3
	G5		I/O	SK		2	4	4
	G6		I	SI		3	5	5
	G7		I/CKO	HALT Restart		4	6	6
	D0		O			19	25	29
	D1		O			20	26	30
	D2		O			21	27	31
	D3		O			22	28	32
	I0		I	COMPIN1+		7	9	9
	I1		I	COMPIN−/Current		8	10	10
				Source Out
	I2		I	COMPIN0+		9	11	11
	I3		I	COMPOUT/COMPIN2+		10	12	12
	I4		I	COMPIN3+			13	13
	I5		I	COMPIN4+			14	14
	I6		I	COMPIN5+			15	15
	I7		I	COMPOUT			16	16
	D4		O				29	33
	D5		O				30	34
	D6		O				31	35
	D7		O				32	36
	C0		I/O				39	43
	C1		I/O				40	44
	C2		I/O				1	1
	C3		I/O				2	2
	C4		I/O					21
	C5		I/O					22
	C6		I/O					23
	C7		I/O					24
	VCC					6	8	8
	GND					23	33	37
	CKI					5	7	7
						24	34	38
	RESET

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4

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (VCC)	7V
Voltage at Any Pin	−0.3V to V CC + 0.3V

Total Current into VCC Pin (Source)	100 mA
Total Current out of GND Pin (Sink)	110 mA
Storage Temperature Range	−65ÊC to +140ÊC

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics 98xEK:

0ÊC ≤ TA ≤ + 70ÊC unless otherwise specified

		Parameter	Conditions	Min	Typ	Max	Units
	Operating Voltage COP98XEK			2.5		4.0	V
	COP98XEKH			4.0		6.0	V
	Power Supply Ripple (Note 3)		Peak-to-Peak			0.1 VCC	V
	Supply Current (Note 4)
	CKI = 10 MHz		VCC = 6.0V, tc = 1 µs			10.0	mA
	CKI = 4 MHz		VCC = 2.5V, tc = 2.5 µs			1.7	mA
	HALT Current (Note 5)		VCC = 6.0V, CKI = 0 MHz		<4	8	µA
			VCC = 4.0V, CKI = 0 MHz		<3	4	µA
	IDLE Current (Note 4)
	CKI = 10 MHz		VCC = 6.0V, tc = 1 µs		0.4	1.7	mA
	CKI = 4 MHz		VCC = 2.5V, tc = 2.5 µs		0.2	0.5	mA
	Input Levels (VIH, VIL)
	RESET
	Logic High			0.8 VCC			V
	Logic Low					0.2 VCC	V
	CKI, All Other Inputs
	Logic High			0.7 VCC			V
	Logic Low					0.2 VCC	V
	Hi-Z Input Leakage		VCC = 6.0V	−1		+1	µA
	Input Pullup Current		VCC = 6.0V, VIN = 0V	−40		−250	µA
	G and L Port Input Hysteresis (Note 8)					0.35 VCC	V
	Output Current Levels
	D Outputs
	Source		VCC = 4.0V, VOH = 3.3V	−0.4			mA
			VCC = 2.5V, VOH = 1.8V	−0.2			mA
	Sink		VCC = 4.0V, VOL = 1V	10			mA
			VCC = 2.5V, VOL = 0.4V	2.0			mA
	All Others
	Source (Weak Pull-Up Mode)		VCC = 4.0V, VOH = 2.7V	−10		−110	µA
			VCC = 2.5V, VOH = 1.8V	−2.5		−33	µA
	Source (Push-Pull Mode)		VCC = 4.0V, VOH = 3.3V	−0.4			mA
			VCC = 2.5V, VOH = 1.8V	−0.2			mA
	Sink (Push-Pull Mode)		VCC = 4.0V, VOL = 0.4V	1.6			mA
			VCC = 2.5V, VOL = 0.4V	0.7			mA
	TRI-STATE Leakage		VCC = 6.0V	−1		+1	µA
	Allowable Sink/Source Current per Pin
	(Note 8)
	D Outputs (Sink)					15	mA
	All others					3	mA
	Maximum Input Current		Room Temp			±100	mA
	without Latchup (Note 6)
	RAM Retention Voltage, Vr		500 ns Rise and Fall Time (Min)	2			V

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COP888EK

DC Electrical Characteristics 98xEK: (Continued)

0ÊC £ TA £ + 70ÊC unless otherwise specified

Parameter	Conditions	Min	Typ	Max	Units
Input Capacitance				7	pF
Load Capacitance on D2				1000	pF

AC Electrical Characteristics 98xEK:

0ÊC £ TA£ + 70ÊC unless otherwise specified

Parameter		Conditions	Min	Typ	Max	Units
Instruction Cycle Time (tc)
Crystal, Resonator,	4.0V	£ VCC £ 6.0V	1.0		DC	µs
	2.5V	£ VCC < 4.0V	2.5		DC	µs
R/C Oscillator	4.0V	£ VCC £ 6.0V	3.0		DC	µs
	2.5V	£ VCC < 4.0V	7.5		DC	µs
Inputs
tSETUP	4.0V	£ VCC £ 6.0V	200			ns
	2.5V	£ VCC < 4.0V	500			ns
tHOLD	4.0V	£ VCC £ 6.0V	60			ns
	2.5V	£ VCC < 4.0V	150			ns
Output Propagation Delay (Note 7)	RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK	4.0V	£ VCC £ 6.0V			0.7	µs
	2.5V	£ VCC < 4.0V			1.75	µs
All Others	4.0V	£ VCC £ 6.0V			1	µs
	2.5V	£ VCC < 4.0V			2.5	µs
MICROWIRE™ Setup Time (tUWS) (Note 7)	VCC ³ 4.0V		20			ns
MICROWIRE Hold Time (tUWH) (Note 7)	VCC ³ 4.0V		56			ns
MICROWIRE Output Propagation Delay (tUPD)	VCC ³ 4.0V				220	ns
Input Pulse Width (Note 8)
Interrupt Input High Time			1.0			tc
Interrupt Input Low Time			1.0			tc
Timer 1, 2, 3 Input High Time			1.0			tc
Timer 1, 2, 3 Input Low Time			1.0			tc
Reset Pulse Width			1.0			µs

Note 2: tc = Instruction Cycle Time

Note 3: Maximum rate of voltage change must be < 0.5 V/ms.

Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180Ê out of phase with CKI, inputs connected to VCC and outputs driven low but not connected to a load.

Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L, C, and G0±G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal clock mode.

Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages > VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.

Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 8: Parameter characterized but not tested.

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6

Absolute Maximum Ratings (Note 9)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (VCC)	7V
Voltage at Any Pin	−0.3V to V CC + 0.3V

Total Current into VCC Pin (Source)	100 mA
Total Current out of GND Pin (Sink)	110 mA
Storage Temperature Range	−65ÊC to +140ÊC

Note 9: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics 88xEK:

−40ÊC ≤ TA ≤ +85ÊC unless otherwise specified

		Parameter	Conditions	Min	Typ	Max	Units
	Operating Voltage			2.5		6.0	V
	Power Supply Ripple (Note 11)		Peak-to-Peak			0.1 VCC	V
	Supply Current (Note 12)
	CKI = 10 MHz		VCC = 6.0V, tc = 1 µs			10.0	mA
	CKI = 4 MHz		VCC = 2.5V, tc = 2.5 µs			1.7	mA
	HALT Current (Note 13)		VCC = 6.0V, CKI = 0 MHz		<4	10	µA
	IDLE Current (Note 12)
	CKI = 10 MHz		VCC = 6.0V, tc = 1 µs		0.4	1.7	mA
	CKI = 4 MHz		VCC = 6.0V, tc = 2.5 µs		0.2	0.5	mA
	Input Levels (VIH, VIL)
	RESET
	Logic High			0.8 VCC			V
	Logic Low					0.2 VCC	V
	CKI, All Other Inputs
	Logic High			0.7 VCC			V
	Logic Low					0.2 VCC	V
	Hi-Z Input Leakage		VCC = 6.0V	−2		+2	µA
	Input Pullup Current		VCC = 6.0V, VIN = 0V	−40		−250	µA
	G and L Port Input Hysteresis (Note 16)					0.35 VCC	V
	Output Current Levels
	D Outputs
	Source		VCC = 4.0V, VOH = 3.3V	−0.4			mA
			VCC = 2.5V, VOH = 1.8V	−0.2			mA
	Sink		VCC = 4.0V, VOL = 1V	10			mA
			VCC = 2.5V, VOL = 0.4V	2.0			mA
	All Others
	Source (Weak Pull-Up Mode)		VCC = 4.0V, VOH = 2.7V	−10		−100	µA
			VCC = 2.5V, VOH = 1.8V	−2.5		−33	µA
	Source (Push-Pull Mode)		VCC = 4.0V, VOH = 3.3V	−0.4			mA
			VCC = 2.5V, VOH = 1.8V	−0.2			mA
	Sink (Push-Pull Mode)		VCC = 4.0V, VOL = 0.4V	1.6			mA
			VCC = 2.5V, VOL = 0.4V	0.7			mA
	TRI-STATE Leakage		VCC = 6.0V	−2		+2	µA
	Allowable Sink/Source Current per Pin
	(Note 16)
	D Outputs (Sink)					15	mA
	All others					3	mA
	Maximum Input Current		Room Temp			±100	mA
	without Latchup (Note 14)
	RAM Retention Voltage, Vr		500 ns Rise	2			V
			and Fall Time (min)
	Input Capacitance					7	pF

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COP888EK

DC Electrical Characteristics 88xEK: (Continued)

−40ÊC ≤ TA ≤ +85ÊC unless otherwise specified

Parameter	Conditions	Min	Typ	Max	Units
Load Capacitance on D2				1000	pF

AC Electrical Characteristics 88xEK:

−40ÊC ≤ TA ≤ +85ÊC unless otherwise specified

Parameter		Conditions	Min	Typ	Max	Units
Instruction Cycle Time (tc)
Crystal, Resonator,	4.0V	≤ VCC ≤ 6.0V	1.0		DC	µs
	2.5V	≤ VCC < 4.0V	2.5		DC	µs
R/C Oscillator	4.0V	≤ VCC ≤ 6.0V	3.0		DC	µs
	2.5V	≤ VCC ≤ 4.0V	7.5		DC	µs
Inputs
tSETUP	4.0V	≤ VCC ≤ 6.0V	200			ns
	2.5V	≤ VCC < 4.0V	500			ns
tHOLD	4.0V	≤ VCC ≤ 6.0V	60			ns
	2.5V	≤ VCC < 4.0V	150			ns
Output Propagation Delay (Note 15)	RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK	4.0V	≤ VCC ≤ 6.0V			0.7	µs
	2.5V	≤ VCC < 4.0V			1.75	µs
All Others	4.0V	≤ VCC ≤ 6.0V			1.0	µs
	2.5V	≤ VCC < 4.0V			2.5	µs
MICROWIRE Setup Time (tUWS) (Note 15)			20			ns
MICROWIRE Hold Time (tUWH) (Note 15)			56			ns
MICROWIRE Output Propagation Delay (tUPD)					220	ns
Input Pulse Width (Note 16)
Interrupt Input High Time			1.0			tc
Interrupt Input Low Time			1.0			tc
Timer 1, 2, 3 Input High Time			1.0			tc
Timer 1, 2, 3 Input Low Time			1.0			tc
Reset Pulse Width			1.0			µs

Note 10: tc = Instruction Cycle Time

Note 11: Maximum rate of voltage change must be < 0.5 V/ms.

Note 12: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180Ê out of phase with CKI, inputs connected to VCC and outputs driven low but not connected to a load.

Note 13: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L, C, G0, and G2±G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal clock mode.

Note 14: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages > VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.

Note 15: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 16: Parameter characterized but not tested.

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8

Absolute Maximum Ratings (Note 17)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (VCC)	7V
Voltage at Any Pin	−0.3V to V CC + 0.3V

Total Current into VCC Pin (Source)	100 mA
Total Current out of GND Pin (Sink)	110 mA
Storage Temperature Range	−65ÊC to +140ÊC

Note 17: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics 68xEK:

−55ÊC ≤ TA ≤ +125ÊC unless otherwise specified

		Parameter	Conditions	Min	Typ	Max	Units
	Operating Voltage			4.5		5.5	V
	Power Supply Ripple (Note 19)		Peak-to-Peak			0.1 VCC	V
	Supply Current (Note 22)		VCC = 5.5V, tc = 1 µs			12.5	mA
	CKI = 10 MHz
	HALT Current (Note 21)		VCC = 5.5V, CKI = 0 MHz		<10	30	µA
	IDLE Current (Note 22)
	CKI = 10 MHz		VCC = 5.5V, tc = 1 µs			1.7	mA
	Input Levels (VIH, VIL)
	RESET
	Logic High			0.8 VCC			V
	Logic Low					0.2 VCC	V
	CKI, All Other Inputs
	Logic High			0.7 VCC			V
	Logic Low					0.2 VCC	V
	Hi-Z Input Leakage		VCC = 5.5V	−5		+5	µA
	Input Pullup Current		VCC = 5.5V, VIN = 0V	−35		−400	µA
	G and L Port Input Hysteresis (Note 24)					0.35 VCC	V
	Output Current Levels
	D Outputs
	Source		VCC = 4.5V, VOH = 3.3V	−0.4			mA
	Sink		VCC = 4.5V, VOL = 1.0V	9.0			mA
	All Others
	Source (Weak Pull-Up Mode)		VCC = 4.5V, VOH = 2.7V	−9.0		−110	µA
	Source (Push-Pull Mode)		VCC = 4.5V, VOH = 3.3V	−0.4			mA
	Sink (Push-Pull Mode)		VCC = 4.5V, VOL = 0.4V	1.6			mA
	TRI-STATE Leakage		VCC = 5.5V	−5.0		+5	µA
	Allowable Sink/Source Current per Pin
	D Outputs (Sink)					12	mA
	All others					2.5	mA
	Maximum Input Current		Room Temp			±100	mA
	without Latchup (Note 22)
	RAM Retention Voltage, Vr		500 ns Rise and	2	1.5		V
			and Fall Time (min)
	Input Capacitance					7	pF
	Load Capacitance on D2					1000	pF

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COP888EK

AC Electrical Characteristics 68xEK:

−55ÊC £ TA £ +125ÊC unless otherwise specified

Parameter		Conditions	Min	Typ	Max	Units
Instruction Cycle Time (tc)
Crystal, Resonator	4.5V	£ VCC £ 5.5V	1.0		DC	µs
R/C Oscillator	4.5V	£ VCC < 5.5V	3.0		DC	µs
Inputs
tSETUP	4.5V	£ VCC £ 5.5V	200			ns
tHOLD	4.5V	£ VCC £ 5.5V	60			ns
Output Propagation Delay (Note 23)	RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK	4.5V	£ VCC £ 5.5V			0.7	µs
All Others	4.5V	£ VCC £ 5.5V			1.0	µs
MICROWIRE Setup Time (tUWS) (Note 23)	VCC ³ 4.5V		20			ns
MICROWIRE Hold Time (tUWH) (Note 23)	VCC ³ 4.5V		56			ns
MICROWIRE Output Propagation Delay (tUPD)	VCC ³ 4.5V				220	ns
Input Pulse Width (Note 24)
Interrupt Input High Time			1.0			tc
Interrupt Input Low Time			1.0			tc
Timer 1, 2, 3 Input High Time			1.0			tc
Timer 1, 2, 3 Input Low Time			1.0			tc
Reset Pulse Width			1.0			µs

Note 18: tc = Instruction Cycle Time

Note 19: Maximum rate of voltage change must be < 0.5 V/ms.

Note 20: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180Ê out of phase with CKI, inputs connected to VCC and outputs driven low but not connected to a load.

Note 21: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L, C, G0, and G2±G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal clock mode.

Note 22: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages > VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.

Note 23: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 24: Parameter characterized but not tested.

Analog Function Block AC and DC Characteristics

VCC = 5.0V, −40ÊC £ TA £ +85ÊC

Parameter		Conditions	Min	Typ	Max	Units
Input Offset Voltage	0.4V	< VIN < VCC − 1.5V		±10	±25	mV
Input Common Mode Voltage Range			0.4		VCC − 1.5	V
(Note 26)
VCC/2 Reference	4.0V	< VCC < 6.0V	0.5 VCC − 0.04	0.5 V CC	0.5 VCC + 0.04	V
DC Supply Current for	VCC = 6.0V				250	µA
Comparator (when enabled)
DC Supply Current for	VCC = 6.0V			50	80	µA
VCC/2 Reference (when enabled)
DC Supply Current for	VCC = 6.0V				200	µA
Constant Current Source (when enabled)
Constant Current Source	4.0V	< VCC < 6.0V	10	20	40	µA
Current Source Variation over	4.0V	< VCC < 6.0V			±2	µA
Common Mode Range	Temp = Constant
Current Source Enable Time				1.5	2	µs

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Analog Function Block AC and DC Characteristics (Continued)

VCC = 5.0V, −40ÊC ≤ TA ≤ +85ÊC

Parameter	Conditions	Min	Typ	Max	Units
Comparator Response Time	100 mV Overdrive,			1	µs
	100 pF Load

Note 25: While performance characteristics are given at VCC = 5.0V, the analog function block will operate over the entire 2.5V±6.0V VCC range. Accuracy of the VCC/2 reference and the constant current source is not guaranteed beyond the specified limits.

Note 26: The device is capable of operating over a common mode voltage range of 0 to VCC − 1.5V, however increased offset voltage will be observed between 0V and 0.4V.

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FIGURE 3. MICROWIRE/PLUS Timing

Typical Performance Characteristics (−55ÊC ≤ TA = +125ÊC)

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Typical Performance Characteristics (−55ÊC ≤ TA = +125ÊC) (Continued)

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Typical Performance Characteristics (−55ÊC ≤ TA = +125ÊC) (Continued)

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Pin Descriptions

VCC and GND are the power supply pins. All VCC and GND pins must be connected.

CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with CKO). See Oscillator Description section.

RESET is the master reset input. See Reset Description section.

The device contains three bidirectional 8-bit I/O ports (C, G and L), where each individual bit may be independently configured as an input (Schmitt Trigger inputs on ports L and G), output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA register. A memory mapped address is also reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O ports.) Figure 4 shows the I/O port configurations. The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below:

CONFIGURA-	DATA	Port Set-Up
TION
Register	Register
0	0	Hi-Z Input
		(TRI-STATE Output)
0	1	Input with Weak Pull-Up
1	0	Push-Pull Zero Output
1	1	Push-Pull One Output

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs.

The Port L supports Multi-Input Wake Up on all eight pins. L4 and L5 are used for the timer input functions T2A and T2B. L6 and L7 are used for the timer input functions T3A and T3B.

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The Port L has the following alternate features:

L7 MIWU or T3B

L6 MIWU or T3A

L5 MIWU or T2B

L4 MIWU or T2A

L3 MIWU

L2 MIWU

L1 MIWU

L0 MIWU

Port G is an 8-bit port with 5 I/O pins (G0, G2±G5), an input pin (G6), and a dedicated output pin (G7). Pins G0 and G2±G6 all have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WDOUT WATCHDOG output, while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO clock output. With the single-pin R/C oscillator mask option selected, G7 serves as a general purpose input pin but is also used to bring the device out of HALT mode with a low to high transition on G7. There are two registers associated with the G Port, a data register and a configuration register. Therefore, each of the 5 I/O bits (G0, G2±G5) can be individually configured under software control.

Since G6 is an input only pin and G7 is the dedicated CKO clock output pin (crystal clock option) or general purpose input (R/C clock option), the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined on the next page. Reading the G6 and G7 data bits will return zeros.

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Pin Descriptions (Continued)

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FIGURE 4. I/O Port Configurations

Note that the chip will be placed in the HALT mode by writing a ª1º to bit 7 of the Port G Data Register. Similarly the chip will be placed in the IDLE mode by writing a ª1º to bit 6 of the Port G Data Register.

Writing a ª1º to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay after HALT when the R/C clock configuration is used.

	Config Reg.	Data Reg.
G7	CLKDLY	HALT
G6	Alternate SK	IDLE

Port G has the following alternate features:

G6 SI (MICROWIRE Serial Data Input)

G5 SK (MICROWIRE Serial Clock)

G4 SO (MICROWIRE Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

G0 INTR (External Interrupt Input)

Port G has the following dedicated functions:

G7 CKO Oscillator dedicated output or general purpose input

G1 WDOUT WATCHDOG and/or Clock Monitor dedicated output

Port C is an 8-bit I/O port. The 40-pin device does not have a full complement of Port C pins. The unavailable pins are not terminated. A read operation for these unterminated pins will return unpredicatable values.

PORT I is an eight-bit Hi-Z input port. The 28-pin device does not have a full complement of Port I pins. The unavailable pins are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable values. The user must ensure that the software takes this into account by either masking or restricting the accesses to bit operations. The unterminated Port I pins will draw power only when addressed.

Port I is an eight-bit Hi-Z input port.

Port I0±I7 are used for the analog function block.

The Port I has the following alternate features:

I7 COMPOUT (Comparator Output)

I6 COMPIN5+ (Comparator Positive Input 5)

I5 COMPIN4+ (Comparator Positive Input 4)

I4 COMPIN3+ (Comparator Positive Input 3)

I3 COMPOUT/COMPIN2+ (Comparator Output/

Comparator Positive Input 2))

I2 COMPIN0+ (Comparator Positive Input 0)

I1 COMPIN− (Comparator Negative Input/Current

Source Out)

I0 COMPIN1+ (Comparator Positive Input 1)

Port D is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.

Note: Care must be exercised with the D2 pin operation. At RESET, the external loads on this pin must ensure that the output voltages stay above 0.8 VCC to prevent the chip from entering special modes. Also keep the external loading on D2 to <1000 pF.

Functional Description

The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on Harvard architecture, permits transfer of data from ROM to RAM.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (tc) cycle time.

There are six CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.

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