NSC COPKG888V, COPHG888V, COPHG888N, COPGG888V, COPGG888N Datasheet

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COP888xG/CS Family

8-Bit CMOS ROM Based Microcontrollers with 4k to 24k

Memory, Comparators and USART

General Description

Note: COP8SG devices are form-fit-function compatible su-

persets of the COP888xG/CL/CS Family devices, and are

replacements for these in new designs, and design up-

grades with minimum effort.

The COP888xGROM based microcontrollers are highly inte-

grated COP8

™

Feature core devices with larger memory (4k

to 24k) and advanced features including two Analog com-

parators. These single-chip CMOS devices are suited for

more complexapplications requiring a full featured controller

with a range of memory sizes, low EMI (except EG), com-

parators, and a full-duplex USART. Pin and software com-

patible (different V

range) 8k toor 32k OTP (One Time

Programmable) versions are available (COP8SGx7 Family).

Erasable windowed versions are available for use with a

range of software and hardware development tools.

Family features include an 8-bit memory mapped architec-

ture, 10 MHz CKI with 1µs instruction cycle, three multi-

function 16-bit timer/counters, full-duplex USART,

MICROWIRE/PLUS

™

serial I/O, two Analog comparators,

two power saving HALT/IDLE modes, idle timer, MIWU, high

current outputs, software selectable I/O options, WATCH-

DOG

™

timer and Clock Monitor, lowEMI 2.5Vto 5.5Vopera-

tion, and 28/40/44 pin packages.

Devices included in this datasheet are:

Device

Memory

(bytes)

RAM

(bytes)

I/O

Pins

Packages Temperature Comments

COP684CS 4k ROM 192 24 28 DIP/SOIC -55 to +125˚C 4.5V - 5.5V

COP884CS 4k ROM 192 24 28 DIP/SOIC -40 to +85˚C

COP984CS 4k ROM 192 24 28 DIP/SOIC -0 to +70˚C 2.5V - 4.0V, CSH=4.0V - 6.0V

COP688CS 4k ROM 192 36/40 40 DIP, 44 PLCC -55 to +125˚C 4.5V - 5.5V

COP888CS 4k ROM 192 36/40 40 DIP, 44 PLCC -40 to +85˚C

COP988CS 4k ROM 192 36/40 40 DIP, 44 PLCC -0 to +70˚C 2.5V - 4.0V, CSH=4.0V - 6.0V

COP884CG 4k ROM 128 24 28 DIP/SOIC -40 to +85˚C 2.5V - 6.0V

COP888CG 4k ROM 128 34/38 40 DIP, 44 PLCC -40 to +85˚C 2.5V - 6.0V

COP684EG 4k ROM 256 24 28 DIP, SOIC -55 to +125˚C 4.5V - 5.5V

COP884EG 4k ROM 256 24 28 DIP, SOIC -40 to +85˚C

COP984EG 4k ROM 256 24 28 DIP, SOIC 0 to +70˚C 2.5V - 4.0V, EGH=4.0 - 6.0V

COP688EG 8k ROM 256 36/40 40 DIP, 44 PLCC -55 to +125˚C 4.5V - 5.5V

COP888EG 8k ROM 256 36/40 40 DIP, 44

PLCC/PQFP

-40 to +85˚C

COP988EG 8k ROM 256 36/40 40 DIP, 44 PLCC 0 to +70˚C 2.5V - 4.0V, EGH=4.0 - 6.0V

COP688GG 16k ROM 512 36/40 40 DIP, 44

PLCC/PQFP

-55 to +125˚C 4.5V - 5.5V

COP888GG 16k ROM 512 36/40 40 DIP, 44

PLCC/PQFP

-40 to +85˚C

COP688HG 20k ROM 512 36/40 40 DIP, 44 PLCC -55 to +125˚C 4.5V - 5.5V

COP888HG 20k ROM 512 36/40 40 DIP, 44 PLCC -40 to +85˚C

COP688KG 24k ROM 512 36/40 40 DIP, 44 PLCC -55 to +125˚C 4.5V - 5.5V

COP888KG 24k ROM 512 36/40 40 DIP, 44 PLCC -40 to +85˚C

Key Features

n Full duplex USART

n Three 16-bit timers, each with two 16-bit registers

supporting:

— Processor Independent PWM mode

— External Event counter mode

— Input Capture mode

n Quiet design (low radiated emissions)

n 4 to 24 kbytes on-board ROM

n 128 to 512 bytes on-board RAM

COP8

™

, MICROWIRE/PLUS

™

, and WATCHDOG

™

are trademarks of National Semiconductor Corporation.

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

iceMASTER

is a registered trademark of MetaLink Corporation.

July 1999

COP888xG/CS Family, 8-Bit CMOS ROM Based Microcontrollers with 4k to 24k Memory,

Comparators and USART

Key Features (Continued)

Additional Peripheral Features

n Idle Timer

n Multi-Input Wake-Up (MIWU) with optional interrupts (8)

n Two analog comparators (one for the CS series)

n WATCHDOG and Clock Monitor logic

n MICROWIRE/PLUS serial I/O

I/O Features

n Memory mapped I/O

n Software selectable I/O options (TRI-STATE

Output,

Push-Pull Output, Weak Pull-Up Input, High Impedance

Input)

n Up to 8 high current outputs

n Schmitt trigger inputs on ports G and L

n Packages:

— 44 PQFP with 40 I/O pins

— 44 PLCC with 40 I/O pins

— 40 DIP with 36 I/O pins

— 28 DIP/SOIC with 24 I/O pins

CPU/Instruction Set Features

n 1 µs instruction cycle time

n Versatile and easy to use instruction set

n Up to fourteen multi-source vectored interrupts servicing

— External Interrupt with selectable edge

— Idle Timer T0

— Three Timers (one timer for the CS series)(each with

2 interrupts)

— MICROWIRE/PLUS

— Multi-Input Wake-Up

— Software Trap

— USART (2)

— Default VIS (default interrupt)

n 8-bit Stack Pointer SP— (stack in RAM)

n Two 8-bit Register Indirect Data Memory Pointers

(B and X)

Fully Static CMOS

n Two power saving modes: HALT and IDLE

n Low current drain (typically

1 µA)

n Single supply operation: 2.5V–5.5V (COP88x)

n Temperature ranges:

0˚C to +70˚C, −40˚C to +85˚C, and −55˚C to +125˚C

Development Support

n Emulation and OTP devices

n Real time emulation and full program debug offered by

MetaLink’s Development System

Block Diagram

DS012829-1

FIGURE 1. COP888xG Block Diagram

www.national.com 2

Connection Diagrams

DS012829-4

Top View

Order Number COP884CS-XXX/WM,

COP984CS-XXX/WM,

COP984CSH-XXX/WM, COP684CS-XXX/WM,

COP884CG-XXX/WM,

COP884EG-XXX/WM or

COP884CS-XXX/N, COP984CS-XXX/N,

COP984CSH-XXX/N, COP884CG-XXX/N,

COP884EG-XXX/N

See NS Package Number M28B or N28A

Dual-In-Line Package

DS012829-3

Top View

Order Number COP888CS-XXX/N, COP988CS-XXX/N,

COP688CS-XXX/N,

COP988CSH-XXX/N, COP888CG-XXX/N,

COP688EG-XXX/N, COP888GG-XXX/N,

COP688GG-XXX/N, COP888GG-XXX/N,

COP688HG-XXX/N, COP888HG-XXX/N,

COP688KG-XXX/N, or COP888KG-XXX/N

See NS Package Number N40A

Plastic Chip Carrier

DS012829-2

Top View

Order Number COP688CS-XXX/V, COP888CS-XXX/V,

COP988CS/CSH-XXX/V, COP688EG-XXX/V,

COP888EG-XXX/V, COP988EG-XXX/V,

COP888CG-XXX/V,

COP688GG-XXX/V, COP888GG-XXX/V,

COP688HG-XXX/V, COP888HG-XXX/V,

COP688KG-XXX/V, or COP888KG-XXX/V

See NS Package Number V44A

DS012829-43

Top View

Order Number COP888EG-XXX/VEJ,

COP688GG-XXX/VEJ, COP888GG-XXX/VEJ,

See NS Package Number VEJ44A

FIGURE 2. Connection Diagrams

www.national.com3

Connection Diagrams (Continued)

Pinouts for 28-, 40- and 44-Pin Packages

Port Type Alt. Fun Alt. Fun

28-Pin 40-Pin 44-Pin 44-Pin

DIP/SO DIP PLCC PQFP

L0 I/O MIWU 11 17 17 11

L1 I/O MIWU CKX 12 18 18 12

L2 I/O MIWU TDX 13 19 19 13

L3 I/O MIWU RDX 14 20 20 14

L4 I/O MIWU T2A* 15 21 25 19

L5 I/O MIWU T2B* 16 22 26 20

L6 I/O MIWU T3A* 17 23 27 21

L7 I/O MIWU T3B* 18 24 28 22

G0 I/O INT 25 35 39 33

G1 WDOUT 26 36 40 34

G2 I/O T1B 27 37 41 35

G3 I/O T1A 28 38 42 36

G4 I/O SO 1 3 3 41

G5 I/O SK 2 4 4 42

G6 I SI 3 5 5 43

G7 I/CKO HALT Restart 4 6 6 44

D0O 19252923

D1O 20263024

D2O 21273125

D3O 22283226

D4 O 29 33 7

D5 O 30 34 8

D6 O 31 35 9

D7O 323610

I0 I 7 9 9 27

I1 I COMP1IN− 8 10 10 28

I2 I COMP1IN+ 9 11 11 29

I3 I COMP1OUT 10 12 12 30

I4 I COMP2IN−* 13 13 3

I5 I COMP2IN+* 14 14 4

I6 I COMP2OUT* 15 15 5

I7 I 16 16 6

C0 I/O 39 43 37

C1 I/O 40 44 38

C2 I/O 1 1 39

C3 I/O 2 2 40

C4 I/O 21 15

C5 I/O 22 16

C6 I/O 23 17

C7 I/O 24 18

6882

GND 23 33 37 31

CKI 5 7 7 1

RESET

24 34 38 32

Note 1:

Not available on the CS series

www.national.com 4

Absolute Maximum Ratings (Note 4)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)7V

Voltage at Any Pin −0.3V to V

+ 0.3V

Total Current into V

Pin (Source) 100 mA

Total Current out of GND Pin (Sink) 110 mA

Storage Temperature Range −65˚C to +140˚C

Note 2:

Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

DC Electrical Characteristics 98xEG and 98xCS:

0˚C ≤ T

≤ +70˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

Operating Voltage

COP98xCS, COP98xEG 2.5 4.0 V

COP98xCSH, COP98xEGH 4.0 6.0 V

Power Supply Ripple (Note 6) Peak-to-Peak 0.1 V

Supply Current (Note 7)

CKI

10 MHz V

6.0V, t

1 µs 12.5 mA

CKI

4 MHz V

6.0V, t

2.5 µs 5.5 mA

CKI

4 MHz V

4V, t

2.5 µs 2.5 mA

CKI

1 MHz V

4V, t

10 µs 1.4 mA

HALT Current (Note 8) V

6.0V, CKI

0 MHz

0.7 8 µA

4V, CKI

0 MHz

0.3 4 µA

IDLE Current

CKI

10 MHz V

6.0V, t

1 µs 3.5 mA

CKI

4 MHz V

6.0V, t

2.5 µs 2.5 mA

CKI

1 MHz V

4V, t

10 µs 0.7 mA

Input Levels (V

)

RESET

Logic High 0.8 V

Logic Low 0.2 V

CKI (External adn Crystal Osc.

Modes)

Logic High 0.7 V

Logic Low 0.2 V

All Other Inputs

Logic High 0.7 V

Logic Low 0.2 V

Hi-Z Input Leakage V

6.0V, V

0V −1 +1 µA

Input Pullup Current V

6.0V, V

0V −40 −250 µA

G and L Port Input Hysteresis (Note 10) 0.35 V

Output Current Levels

D Outputs

Source V

4V, V

3.3V −0.4 mA

2.5V, V

1.8V −0.2 mA

Sink V

4V, V

1V 10 mA

2.5V, V

0.4V 2.0 mA

All Others

Source (Weak Pull-Up Mode) V

4V, V

2.7V −10 −100 µA

2.5V, V

1.8V −2.5 −33 µA

Source (Push-Pull Mode) V

4V, V

3.3V −0.4 mA

2.5V, V

1.8V −0.2 mA

Sink (Push-Pull Mode) V

4V, V

0.4V 1.6 mA

2.5V, V

0.4V 0.7 mA

www.national.com5

DC Electrical Characteristics 98xEG and 98xCS: (Continued)

0˚C ≤ T

≤ +70˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

TRI-STATE Leakage V

6.0V −1 +1 µA

Allowable Sink/Source

Current per Pin

D Outputs (Sink) 15 mA

All others 3mA

Maximum Input Current

without Latchup (Notes 9, 10) T

= 25˚

100 mA

RAM Retention Voltage, V

500 ns Rise and Fall Time (min) 2 V

Input Capacitance 7pF

Load Capacitance on D2 1000 pF

AC Electrical Characteristics 98xEG and 98xCS:

0˚C ≤ T

≤ +70˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

Instruction Cycle Time (t

)

Crystal, Resonator 4V ≤ V

≤ 6.0V 2.5 DC µs

2.5V ≤ V

4V 1.0 DC µs

R/C Oscillator 4V ≤ V

≤ 6.0V 7.5 DC µs

2.5V ≤ V

4V 3.0 DC µs

Inputs

SETUP

4V ≤ V

≤ 6.0V 200 ns

2.5V ≤ V

4V 500 ns

HOLD

4V ≤ V

≤ 6.0V 60 ns

2.5V ≤ V

4V 150 ns

Output Propagation Delay R

2.2k, C

100 pF

PD1

PD0

SO, SK 4V ≤ V

≤ 6.0V 0.7 µs

2.5V ≤ V

4V 1.75 µs

All Others 4V ≤ V

≤ 6.0V 1 µs

2.5V ≤ V

4V 2.5 µs

MICROWIRE Setup Time (t

UWS

) (Note 10) 20 ns

MICROWIRE Hold Time (t

UWH

) (Note 10) 56 ns

MICROWIRE Output Propagation Delay (t

UPD

) 220 ns

Input Pulse Width (Note 11)

Interrupt Input High Time 1 t

Interrupt Input Low Time 1 t

Timer 1, 2, 3 Input High Time 1 t

Timer 1, 2, 3 Input Low Time 1 t

Reset Pulse Width 1 µs

www.national.com 6

Absolute Maximum Ratings (Note 4)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)7V

Voltage at Any Pin −0.3V to V

+ 0.3V

Total Current into V

Pin (Source) 100 mA

Total Current out of GND Pin (Sink) 110 mA

Storage Temperature Range −65˚C to +140˚C

Note 3:

Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

DC Electrical Characteristics 88xCG, 88xCS, and 88xEG:

−40˚C ≤ T

≤ +85˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

Operating Voltage

Power Supply Ripple (Note 6) Peak-to-Peak 0.1 V

Supply Current (Note 7)

CKI

10 MHz V

6.0V, t

1 µs 12.5 mA

CKI

4 MHz V

6.0V, t

2.5 µs 5.5 mA

CKI

4 MHz

(88xCG & 88xEG only)

4V, t

2.5 µs 2.5 mA

CKI

1 MHz

(88xCG & 88xEG only)

4V, t

10 µs 1.4 mA

HALT Current (Note 8) V

6.0V, CKI

0 MHz

1.0 8 µA

(88xCG & 88xEG only) V

4V, CKI

0 MHz

0.5 4 µA

IDLE Current

CKI

10 MHz V

6.0V, t

1 µs 3.5 mA

CKI

4 MHz V

6.0V, t

2.5 µs 2.5 mA

CKI

1 MHz

(88xCG & 88xEG only)

4V, t

10 µs 0.7 mA

Input Levels (V

)

RESET

Logic High 0.8 V

Logic Low 0.2 V

CKI (External adn Crystal Osc.

Modes)

Logic High 0.7 V

Logic Low 0.2 V

All Other Inputs

Logic High 0.7 V

Logic Low 0.2 V

Hi-Z Input Leakage V

6.0V −2 +2 µA

Input Pullup Current V

6.0V, V

0V −40 −250 µA

G and L Port Input Hysteresis (Note 10) 0.35 V

Output Current Levels

D Outputs

Source V

4V, V

3.3V −0.4 mA

2.5V, V

1.8V −0.2 mA

Sink V

4V, V

1V 10 mA

2.5V, V

0.4V 2.0 mA

All Others

Source (Weak Pull-Up Mode) V

4V, V

2.7V −10 −100 µA

2.5V, V

1.8V −2.5 −33 µA

Source (Push-Pull Mode) V

4V, V

3.3V −0.4 mA

2.5V, V

1.8V −0.2 mA

Sink (Push-Pull Mode) V

4V, V

0.4V 1.6 mA

www.national.com7

DC Electrical Characteristics 88xCG, 88xCS, and 88xEG: (Continued)

−40˚C ≤ T

≤ +85˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

2.5V, V

0.4V 0.7 mA

TRI-STATE Leakage V

6.0V −1 +1 µA

Allowable Sink/Source

Current per Pin

D Outputs (Sink) 15 mA

All others 3mA

Maximum Input Current

without Latchup (Notes 9, 10) T

= 25˚

100 mA

RAM Retention Voltage, V

500 ns Rise and Fall Time (min) 2 V

Input Capacitance 7pF

Load Capacitance on D2 1000 pF

AC Electrical Characteristics 888EG, 88xCS, and 88xCG:

−40˚C ≤ T

≤ +85˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

Instruction Cycle Time (t

)

Crystal, Resonator 4V ≤ V

≤ 6.0V 1.0 DC µs

2.5V ≤ V

4V 2.5 DC µs

R/C Oscillator 4V ≤ V

≤ 6.0V 3.0 DC µs

2.5V ≤ V

4V 7.5 DC µs

Inputs

SETUP

4V ≤ V

≤ 6.0V 200 ns

2.5V ≤ V

4V 500 ns

HOLD

4V ≤ V

≤ 6.0V 60 ns

2.5V ≤ V

4V 150 ns

Output Propagation Delay R

2.2k, C

100 pF

PD1

PD0

SO, SK 4V ≤ V

≤ 6.0V 0.7 µs

2.5V ≤ V

4V 1.75 µs

All Others 4V ≤ V

≤ 6.0V 1 µs

2.5V ≤ V

4V 2.5 µs

MICROWIRE Setup Time (t

UWS

) (Note 10) 20 ns

MICROWIRE Hold Time (t

UWH

) (Note 10) 56 ns

MICROWIRE Output Propagation Delay (t

UPD

) 220 ns

Input Pulse Width (Note 11)

Interrupt Input High Time 1 t

Interrupt Input Low Time 1 t

Timer 1, 2, 3 Input High Time 1 t

Timer 1, 2, 3 Input Low Time 1 t

Reset Pulse Width 1 µs

www.national.com 8

Absolute Maximum Ratings (Note 4)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)7V

Voltage at Any Pin −0.3V to V

+ 0.3V

Total Current into V

Pin (Source) 100 mA

Total Current out of GND Pin (Sink) 110 mA

Storage Temperature Range −65˚C to +140˚C

Note 4:

Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

DC Electrical Characteristics 888GG, 888HG, and 888KG:

−40˚C ≤ T

≤ +85˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

Operating Voltage 2.5 5.5 V

Power Supply Ripple (Note 6) Peak-to-Peak 0.1 V

Supply Current (Note 7)

CKI

10 MHz V

5.5V, t

1 µs 12.5 mA

CKI

4 MHz V

5.5V, t

2.5 µs 5.5 mA

CKI

4 MHz V

4V, t

2.5 µs 2.5 mA

CKI

1 MHz V

4V, t

10 µs 1.4 mA

HALT Current (Note 8) V

5.5V, CKI

0 MHz

110 µA

4V, CKI

0 MHz

0.5 6 µA

IDLE Current

CKI

10 MHz V

5.5V, t

1 µs 3.5 mA

CKI

4 MHz V

5.5V, t

2.5 µs 2.5 mA

CKI

1 MHz V

4V, t

10 µs 0.7 mA

Input Levels (V

)

RESET

Logic High 0.8 V

Logic Low 0.2 V

CKI, All Other Inputs

Logic High 0.7 V

Logic Low 0.2 V

Hi-Z Input Leakage V

5.5V, V

0V −2 +2 µA

Input Pullup Current V

5.5V, V

0V −40 −250 µA

G and L Port Input Hysteresis (Note 10) 0.35 V

Output Current Levels

D Outputs

Source V

4V, V

3.3V −0.4 mA

2.5V, V

1.8V −0.2 mA

Sink V

4V, V

1V 10 mA

2.5V, V

0.4V 2.0 mA

All Others

Source (Weak Pull-Up Mode) V

4V, V

2.7V −10 −100 µA

2.5V, V

1.8V −2.5 −33 µA

Source (Push-Pull Mode) V

4V, V

3.3V −0.4 mA

2.5V, V

1.8V −0.2 mA

Sink (Push-Pull Mode) V

4V, V

0.4V 1.6 mA

2.5V, V

0.4V 0.7 mA

TRI-STATE Leakage V

5.5V −2 +2 µA

Allowable Sink/Source

Current per Pin

D Outputs (Sink) 15 mA

All others 3mA

Maximum Input Current

www.national.com9

DC Electrical Characteristics 888GG, 888HG, and 888KG: (Continued)

−40˚C ≤ T

≤ +85˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

without Latchup (Notes 9, 10) Room Temperature

100 mA

RAM Retention Voltage, V

500 ns Rise and Fall Time (min) 2 V

Input Capacitance 7pF

Load Capacitance on D2 (Note 10) 1000 pF

AC Electrical Characteristics 888GG, 888HG, and 888KG:

−40˚C ≤ T

≤ +85˚C unless otherwise specified

Parameter

(88xCG & 88xEG only)

Conditions Min Typ Max Units

Instruction Cycle Time (t

)

Crystal, Resonator 2.5V ≤ V

4V 1.0 DC µs

4V ≤ V

≤ 5.5V 2.5 DC µs

R/C Oscillator 2.5V ≤ V

4V 3.0 DC µs

4V ≤ V

≤ 5.5V 7.5 DC µs

Inputs

SETUP

4V ≤ V

≤ 5.5V 200 ns

2.5V ≤ V

4V 500 ns

HOLD

4V ≤ V

≤ 5.5V 60 ns

2.5V ≤ V

4V 150 ns

Output Propagation Delay R

2.2k, C

100 pF

PD1

PD0

SO, SK 4V ≤ V

≤ 5.5V 0.7 µs

2.5V ≤ V

4V 1.75 µs

All Others 4V ≤ V

≤ 5.5V 1 µs

2.5V ≤ V

4V 2.5 µs

MICROWIRE Setup Time (t

UWS

) (Note 10) V

≥ 4V 20 ns

MICROWIRE Hold Time (t

UWH

) (Note 10) V

≥ 4V 56 ns

MICROWIRE Output Propagation Delay (t

UPD

≥ 4V 220 ns

Input Pulse Width (Note 11)

Interrupt Input High Time 1 t

Interrupt Input Low Time 1 t

Timer 1, 2, 3 Input High Time 1 t

Timer 1, 2, 3 Input Low Time 1 t

Reset Pulse Width 1 µs

www.national.com 10

Absolute Maximum Ratings (Note 5)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)7V

Voltage at Any Pin −0.3V to V

+ 0.3V

Total Current into V

Pin (Source) 100 mA

Total Current out of GND Pin (Sink) 110 mA

Storage Temperature Range −65˚C to +140˚C

Note 5:

Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

DC Electrical Characteristics 68xCS and 68xxG:

−55˚C ≤ T

≤ +125˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

Operating Voltage 4.5 5.5 V

Power Supply Ripple (Note 6) Peak-to-Peak 0.1 V

Supply Current (Note 7)

CKI

10 MHz V

5.5V, t

1 µs 12.5 mA

CKI

4 MHz V

5.5V, t

2.5 µs 5.5 mA

HALT Current (Note 8) V

5.5V, CKI

0 MHz

10 30 µA

IDLE Current

CKI

10 MHz V

5.5V, t

1 µs 3.5 mA

CKI

4 MHz V

5.5V, t

2.5 µs 2.5 mA

Input Levels (V

)

RESET

Logic High 0.8 V

Logic Low 0.2 V

CKI (68xCS & 68xEG only)

Logic High 0.7 V

Logic Low 0.2 V

All Other Inputs

Logic High 0.7 V

Logic Low 0.2 V

Hi-Z Input Leakage V

5.5V, V

0V −5 +5 µA

Input Pullup Current V

5.5V, V

0V −35 −400 µA

G and L Port Input Hysteresis (Note 10) 0.35 V

Output Current Levels

D Outputs

Source V

4.5V, V

3.3V −0.4 mA

Sink V

4.5V, V

1V 9 mA

All Others

Source (Weak Pull-Up Mode) V

4.5V, V

2.7V −9 −140 µA

Source (Push-Pull Mode) V

4.5V, V

3.3V −0.4 mA

Sink (Push-Pull Mode) V

4.5V, V

0.4V 1.4 mA

TRI-STATE Leakage V

5.5V −5 +5 µA

Allowable Sink/Source

Current per Pin

D Outputs (Sink) 12 mA

All others 2.5 mA

Maximum Input Current

without Latchup (Notes 9, 10) Room Temp

100 mA

RAM Retention Voltage, V

500 ns Rise and Fall Time (min) 2 V

Input Capacitance (Note 10) 7 pF

Load Capacitance on D2 (Note 10) 1000 pF

www.national.com11

AC Electrical Characteristics 68xCS and 68xxG:

−55˚C ≤ T

≤ +125˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

Instruction Cycle Time (t

)

Crystal, Resonator V

≥ 4.5V 1.0 DC µs

R/C Oscillator

68xCS & 68xEG only)

≥ 4.5V 3.0 DC µs

Inputs

SETUP

≥ 4.5V 200 ns

HOLD

≥ 4.5V 60 ns

Output Propagation Delay R

2.2k, C

100 pF

PD1

PD0

SO, SK V

≥ 4.5V 0.7 µs

All Others V

≥ 4.5V 1 µs

MICROWIRE

™

Setup Time (t

UWS

) (Note 10) 20 ns

MICROWIRE Hold Time (t

UWH

) (Note 10) 56 ns

MICROWIRE Output Propagation Delay (t

UPD

) 220 ns

Input Pulse Width (Note 11)

Interrupt Input High Time 1 t

Interrupt Input Low Time 1 t

Timer 1, 2, 3 Input High Time 1 t

Timer 1, 2, 3 Input Low Time 1 t

Reset Pulse Width 1 µs

Note 6: Maximum rate of voltage change must be less than 0.5 V/ms.

Note 7: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.

Note 8: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of IDD HALT is done with device neither sourcing or

sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V

;

clock monitor and comparatorsdisabled. Parameter refers toHALTmode entered via setting bit 7 of theG Port data register.Partwill pull up CKIduring HALTin crys-

tal clock mode.

Note 9: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V

and the pins will have sink current

to V

when biased atvoltages greater thanV

(the pins donot have sourcecurrent when biasedat a voltagebelow V

). The effective resistance to V

is 750Ω

(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltagesin excess of 14V will cause damage to the

pins. This warning excludes ESD transients.

Note 10: Parameter characterized but not tested.

Note 11: t

Instruction Cycle Time

Comparators AC and DC Characteristics

5V, −40˚C ≤ T

≤ +85˚C.

Parameter Conditions Min Typ Max Units

Input Offset Voltage 0.4V ≤ V

≤ V

− 1.5V

25 mV

Input Common Mode Voltage Range 0.4 V

− 1.5 V

Voltage Gain 300k V/V

Low Level Output Current V

0.4V 1.6 mA

High Level Output Current V

4.6V 1.6 mA

DC Supply Current per Comparator (When Enabled) 250 µA

Response Time 100 mV Overdrive, 1 µs

100 pF Load

www.national.com 12

Comparators AC and DC Characteristics (Continued)

Typical Performance Characteristics (−55˚C ≤ T

+125˚C)

DS012829-4

FIGURE 3. MICROWIRE/PLUS Timing

DS012829-30 DS012829-31

DS012829-32 DS012829-33

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Typical Performance Characteristics (−55˚C ≤ T

+125˚C) (Continued)

DS012829-34

DS012829-35

DS012829-36 DS012829-37

DS012829-38 DS012829-39

www.national.com 14

Typical Performance Characteristics (−55˚C ≤ T

+125˚C) (Continued)

Pin Descriptions

and GND are the power supply pins. All V

and GND

pins must be connected.

CKI isthe clock input. This can come from an R/C generated

oscillator, or a crystal oscillator (in conjunction with CKO).

See Oscillator Description section.

RESET is the master reset input. See ResetDescription sec-

tion.

The device contains three bidirectional 8-bit I/O ports (C, G

and L), where each individual bit may be independently con-

figured asan input (Schmitt Trigger inputs on ports L and G),

output or TRI-STATE under program control. Three data

memory address locations are allocated for each of these

I/O ports. Each I/O port has two associated 8-bit memory

mapped registers, the CONFIGURATION register and the

output DATAregister. A memory mapped address is also re-

served for the input pins of each I/O port. (See the memory

map for the various addresses associated with theI/O ports.)

Figure 4

shows the I/O port configurations. The DATA and

CONFIGURATION registers allow for each port bit to be in-

dividually configured under software control as shown below:

CONFIGURATION DATA Port Set-Up

0 0 Hi-Z Input

(TRI-STATE Output)

0 1 Input with Weak Pull-Up

1 0 Push-Pull Zero Output

1 1 Push-Pull One Output

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers

on the inputs.

The Port L supports Multi-Input WakeUp on all eight pins. L1

is used for the USART external clock. L2 andL3 are used for

the USARTtransmit and receive. L4 and L5 are used for the

timer input functions T2A and T2B. L6 and L7 are used for

the timer input functions T3Aand T3B (execpt on the CS se-

ries).

The Port L has the following alternate features:

L7 MIWU or T3B

L6 MIWU or T3A

L5 MIWU or T2B

L4 MIWU or T2A

L3 MIWU or RDX

L2 MIWU or TDX

L1 MIWU or CKX

L0 MIWU

Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input

pin (G6), and a dedicated output pin (G1). Pins G0 and

G2–G6 all have Schmitt Triggers on their inputs. Pin G1

serves as the dedicated WDOUT WATCHDOG output, while

pin G7 is either input or output depending on the oscillator

mask option selected. With the crystal oscillator option se-

lected, G7 serves as the dedicated output pin for the CKO

clock output. With the single-pin R/C oscillator mask option

selected, G7 serves as a general purpose input pin but is

also used to bring the device out of HALT mode with a low to

high transition on G7. There are two registers associated

with the G Port, a data register and a configuration register.

Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi-

vidually configured under software control.

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin (crystal clock option) or general purpose in-

put (R/C clock option), the associated bits in the data and

configuration registers for G6 and G7 are used for special

purpose functions as outlined on the next page. Reading the

G6 and G7 data bits will return zeros.

Note thatthe chip will be placed in the HALT modeby writing

a “1” to bit 7 of the Port G Data Register. Similarly the chip

will beplaced in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register en-

ables the MICROWIRE/PLUS to operate with the alternate

DS012829-40

DS012829-41

DS012829-5

FIGURE 4. I/O Port Configurations

www.national.com15

Pin Descriptions (Continued)

phase of the SK clock. The G7 configuration bit, if set high,

enables the clock start up delay after HALT when the R/C

clock configuration is used.

Config Reg. Data Reg.

G7 CLKDLY HALT

G6 Alternate SK IDLE

Port G has the following alternate features:

G6 SI (MICROWIRE Serial Data Input)

G5 SK (MICROWIRE Serial Clock)

G4 SO (MICROWIRE Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

G0 INTR (External Interrupt Input)

Port G has the following dedicated functions:

G7 CKO Oscillator dedicated output or general purpose

input

G1 WDOUT WATCHDOG and/or Clock Monitor dedi-

cated output

Port C is an 8-bit I/O port. The 40-pin device does not have

a full complement of Port C pins. The unavailable pins are

not terminated.A read operation for these unterminated pins

will return unpredicatable values.

Port I is an eight-bit Hi-Z input port.

Port I1–I3 are used forComparator 1.Port I4–I6 are used for

Comparator 2.

The Port I has the following alternate features:

I6 COMP2OUT (Comparator 2 Output)

I5 COMP2+IN (Comparator 2 Positive Input)

I4 COMP2−IN (Comparator 2 Negative Input)

I3 COMP1OUT (Comparator 1 Output)

I2 COMP1+IN (Comparator 1 Positive Input)

I1 COMP1−IN (Comparator 1 Negative Input)

Port D is an 8-bit output port that ispreset high when RESET

goes low. The user can tie two or more D port outputs (ex-

cept D2) together in order to get a higher drive.

Functional Description

The architecture of the device is modified Harvard architec-

ture. With the Harvard architecture, the control store pro-

gram memory (ROM) is separated from the data store

memory (RAM). Both ROM and RAM have their own sepa-

rate addressing space with separate address buses. The ar-

chitecture, though based on Harvard architecture, permits

transfer of data from ROM to RAM.

CPU REGISTERS

The CPU can doan 8-bit addition, subtraction, logicalor shift

operation in one instruction (t

) cycle time.

There are six CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). The SP is initialized to RAM ad-

dress 06F with reset.

S is the 8-bit Data SegmentAddress Register used to extend

the lower half of the address range (00 to 7F) into 256 data

segments of 128 bytes each.

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

PROGRAM MEMORY

The program memory consists of up to 24 kbytes of ROM.

These bytes may hold program instructions or constant data

(data tablesfor the LAID instruction, jump vectors for the JID

instruction, and interrupt vectors for the VIS instruction). The

program memory is addressed by the 15-bit program

counter (PC). All interrupts in the devices vector to program

memory location 0FF Hex.

DATA MEMORY

The data memory address space includes the on-chip RAM

and data registers, theI/O registers (Configuration, Data and

Pin), the control registers, the MICROWIRE/PLUS SIO shift

with the timers (with the exception of the IDLE timer). Data

memory is addressed directly by the instruction or indirectly

by the B, X, SP pointers and S register.

The data memory consists of up to 512 bytes of RAM. Six-

teen bytes of RAM are mapped as “registers” at addresses

0F0 to0FF Hex. These registers can be loaded immediately,

and also decremented and tested withthe DRSZ(decrement

registers X,SP,B and S are memorymapped into thisspace

at address locations 0FC to 0FF Hex respectively, with the

other registers being available for general usage.

The instructionset permits anybit in memoryto be set,reset

or tested. All I/O and registers (except A and PC) are

memory mapped; therefore, I/O bits and register bits can be

directly andindividually set, reset and tested. The accumula-

tor (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

Data Memory Segment RAM

Extension

Data memory address 0FF is used as a memory mapped lo-

cation for the Data Segment Address Register (S).

The data store memory is either addressed directly by a

single byte address within the instruction, or indirectly rela-

tive to the reference of the B, X, or SP pointers (each con-

tains a single-byte address). This single-byte address allows

an addressingrange of 256 locations from 00 to FF hex. The

upper bit of this single-byte address divides the data store

memory into two separate sections as outlined previously.

With the exception of the RAM register memory from ad-

dress locations 00F0 to 00FF, all RAM memory is memory

mapped with the upper bit of the single-byte address being

equal to zero. This allows the upper bit of the single-byte ad-

dress to determine whether or not the base address range

(from 0000 to 00FF) is extended. If this upper bit equals one

(representing address range 0080 to 00FF), then address

extension does not take place. Alternatively, if this upper bit

equals zero, then the data segment extension register S is

used to extend the base address range (from 0000 to 007F)

from XX00 to XX7F,where XX represents the 8 bits from the

S register. Thus the 128-byte data segment extensions are

located from addresses 0100 to 017F for data segment 1,

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