NSC COP87L88CLV-XE, COP87L88CLN-XE, COP87L84CLN-XE, COP87L84CLM-XE Datasheet

PRELIMINARY

September 1996

COP87L88CL/COP87L84CL 8-Bit

One-Time Programmable (OTP) Microcontroller

General Description	Y	Packages:
		Ð 44	PLCC with 39 I/O pins
The COP87L88CL/COP87L84CL OTP microcontrollers are
		Ð 40	DIP with 33 I/O pins
members of the COP8TM feature family using an 8-bit core
		Ð 28	DIP with 24 I/O pins
architecture. It is pin and software compatible to the mask
		Ð 28	SO with 24 I/O pins (contact local sales office for

ROM COP888CL/COP884CL product family.	availability)
	(Continued)

Key Features

Y Two 16-bit timers, each with two 16-bit registers supporting:

ÐProcessor independent PWM mode

ÐExternal event counter mode

ÐInput capture mode

Y4 kbytes on-board EPROM with security feature

Y128 bytes on-board RAM

Additional Peripheral Features

YIdle timer

YMulti-Input Wake-Up (MIWU) with optional interrupts (8)

YWATCHDOGTM and clock monitor logic

YMICROWIRE/PLUSTM serial I/O

I/O Features

YMemory mapped I/O

YSoftware selectable I/O options (TRI-STATEÉ output, push-pull output, weak pull-up input, high impedance input)

YSchmitt trigger inputs on ports G and L

CPU/Instruction Set Features

Y1 ms instruction cycle time

YTen multi-source vectored interrupts servicing

ÐExternal interrupt

ÐIdle timer T0

ÐTwo timers (each with 2 Interrupts)

ÐMICROWIRE/PLUS

ÐMulti-Input Wake Up

ÐSoftware trap

ÐDefault VIS (default interrupt)

YVersatile and easy to use instruction set

Y8-bit Stack Pointer SPÐstack in RAM

Y Two 8-bit register indirect data memory pointers (B and X)

Fully Static CMOS

YTwo power saving modes: HALT and IDLE

YSingle supply operation: 2.7V ± 5.5V

YTemperature range: b40§C to a85§C

Development Support

YEmulation device for the COP888CL/COP884CL

YReal time emulation and full program debug offered by MetaLink Development System

Block Diagram

TL/DD/12524 ± 16

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

MICROWIRE/PLUSTM, WATCHDOGTM, MICROWIRETM and COP8TM are trademarks of National Semiconductor Corporation. PCÉ is a registered trademark of International Business Machines Corporation.

iceMASTERTM is a trademark of MetaLink Corporation.

C1996 National Semiconductor Corporation

TL/DD12524

RRD-B30M106/Printed in U. S. A.

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Microcontroller (OTP) Programmable Time-One Bit-8 COP87L88CL/COP87L84CL

General Description (Continued)

The device is a fully static part, fabricated using double-met- al silicon gate microCMOS technology. Features include an 8-bit memory mapped architecture, MICROWIRE/PLUSTM serial I/O, two 16-bit timer/counters supporting three modes (Processor Independent PWM generation, External

Connection Diagrams

Plastic Chip Carrier

TL/DD/12524 ± 1

Top View

Order Number COP87L88CLV-XE

See NS Package Number V44A

Note: -X Crystal Oscillator

-E Halt Enable

Event counter, and Input Capture mode capabilities). Each I/O pin has software selectable configurations. The devices operates over a voltage range of 2.7V to 5.5V. High throughput is achieved with an efficient, regular instruction set operating at a maximum of 1 ms per instruction rate.

Dual-In-Line Package

TL/DD/12524 ± 2

Top View

Order Number COP87L84CLN-XE

See NS Package Number N40A

Dual-In-Line Package

TL/DD/12524 ± 3

Top View

Order Number COP87L84CLN-XE or COP87L84CLM-XE

See NS Package Number M28B or N28B

FIGURE 1. COP87L88CL/COP87L84CL Connection Diagrams

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Connection Diagrams (Continued)

Pinouts for 28-, 40and 44-Pin Packages

	Port		Type	Alt. Fun	Alt. Fun	28-Pin	40-Pin	44-Pin
						Pkg.	Pkg.	Pkg.
	L0		I/O	MIWU		11	17	17
	L1		I/O	MIWU		12	18	18
	L2		I/O	MIWU		13	19	19
	L3		I/O	MIWU		14	20	20
	L4		I/O	MIWU	T2A	15	21	25
	L5		I/O	MIWU	T2B	16	22	26
	L6		I/O	MIWU		17	23	27
	L7		I/O	MIWU		18	24	28
	G0		I/O	INT		25	35	39
	G1		WDOUT			26	36	40
	G2		I/O	T1B		27	37	41
	G3		I/O	T1A		28	38	42
	G4		I/O	SO		1	3	3
	G5		I/O	SK		2	4	4
	G6		I	SI		3	5	5
	G7		I/CKO	Halt Restart		4	6	6
	D0		O			19	25	29
	D1		O			20	26	30
	D2		O			21	27	31
	D3		O			22	28	32
	I0		I			7	9	9
	I1		I			8	10	10
	I2		I				11	11
	I3		I				12	12
	I4		I			9	13	13
	I5		I			10	14	14
	I6		I					15
	I7		I					16
	D4		O				29	33
	D5		O				30	34
	D6		O				31	35
	D7		O				32	36
	C0		I/O				39	43
	C1		I/O				40	44
	C2		I/O				1	1
	C3		I/O				2	2
	C4		I/O					21
	C5		I/O					22
	C6		I/O					23
	C7		I/O					24
	Unused*						16
	Unused*						15
	VCC					6	8	8
GND						23	33	37
CKI						5	7	7
	RESET					24	34	38

* e On the 40-pin package, Pins 15 and 16 must be connected to GND.

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Absolute Maximum Ratings (Note)

If Military/Aerospace	specified	devices are required,	Total Current out of GND Pin (Sink)	110 mA
please contact the	National	Semiconductor Sales	Storage Temperature Range	b65§C to a140§C
Office/Distributors for availability and specifications.			Note: Absolute maximum ratings indicate limits beyond which damage to the
Supply Voltage (VCC)		7V	device may occur. DC and AC electrical specifications are not ensured when
Voltage at Any Pin		b0.3V to VCC a 0.3V	operating the device at absolute maximum ratings.
Total Current into VCC Pin (Source)		100 mA

DC Electrical Characteristics b40§C s TA s a85§C unless otherwise specified

	Parameter	Conditions	Min	Typ	Max	Units
	Operating Voltage		2.7		5.5	V
	Power Supply Ripple (Note 1)	Peak-to-Peak			0.1 VCC	V
	Supply Current (Note 2)
	CKI e 10 MHz	VCC e 5.5V, tc e 1 ms			16.5	mA
	CKI e 4 MHz	VCC e 4.0V, tc e 2.5 ms			6.5	mA
	HALT Current (Note 3)	VCC e 5.5V, CKI e 0 MHz			12	mA
	IDLE Current, CKI e 10 MHz	VCC e 5.5V, tc e 1 ms			3.5	mA
	CKI e 1 MHz	VCC e 4.0V, tc e 10 ms			0.7	mA
	Input Levels
	RESET
	Logic High		0.8 VCC
	Logic Low				0.2 VCC
	CKI (External and Crystal Osc. Modes)					V
	Logic High		0.7 VCC
	Logic Low				0.2 VCC
	All Other Inputs
	Logic High		0.7 VCC
	Logic Low				0.2 VCC
	Hi-Z Input Leakage	VCC e 5.5V	b2		a2	mA
	Input Pullup Current	VCC e 5.5V	40		250	mA
	G and L Port Input Hysteresis			0.05 VCC	0.35 VCC	V
	Output Current Levels
	D Outputs
	Source	VCC e 4.5V, VOH e 3.3V	0.4			mA
	Sink (Note 4)	VCC e 4.5V, VOL e 1V	10			mA
	All Others
	Source (Weak Pull-Up Mode)	VCC e 4.5V, VOH e 2.7V	10		100	mA
	Source (Push-Pull Mode)	VCC e 4.5V, VOH e 3.3V	0.4			mA
	Sink (Push-Pull Mode)	VCC e 4.5V, VOL e 0.4V	1.6			mA
	TRI-STATE Leakage	VCC e 5.5V	b2		a2	mA
	Allowable Sink/Source
	Current per Pin					mA
	D Outputs (Sink)				15
	All others				3
	Maximum Input Current	TA e 25§C			g100	mA
without Latchup (Note 5)
	RAM Retention Voltage, Vr	500 ns Rise	2			V
		and Fall Time (Min)
	Input Capacitance				7	pF
	Load Capacitance on D2				1000	pF

Note 1: Rate of voltage change must be less then 0.5V/ms.

Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.

Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Test conditions: All inputs tied to VCC, L and G ports in the TRI-STATE mode and tied to ground, all outputs low and tied to ground. The clock monitor is disabled.

Note 4: The user must guarantee that D2 pin does not source more than 10 mA during RESET. If D2 sources more than 10 mA during RESET, the device will go into programming mode.

Note 5: Pins G5 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.

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AC Electrical Characteristics b40§C s TA s a85§C unless otherwise specified

Parameter	Conditions	Min	Typ	Max	Units
Instruction Cycle Time (tc)
Crystal or Resonator		1		DC	ms
R/C Oscillator		3		DC
Inputs
tSETUP		200			ns
tHOLD		60
Output Propagation Delay	RL e 2.2k, CL e 100 pF
tPD1, tPD0					ms
SO, SK	4V s VCC s 6V			0.7
All Others	4V s VCC s 6V			1
MICROWIRETM Setup Time (tUWS)		20
MICROWIRE Hold Time (tUWH)		56			ns
MICROWIRE Output Propagation Delay (tUPD)				220
Input Pulse Width
Interrupt Input High Time		1
Interrupt Input Low Time		1			tc
Timer Input High Time		1
Timer Input Low Time		1
Reset Pulse Width		1			ms

TL/DD/12524 ± 4

FIGURE 2. MICROWIRE/PLUS Timing

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Pin Descriptions

VCC and GND are the power supply pins.

CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with CKO). See Oscillator Description section.

RESET is the master reset input. See Reset Description section.

The device contains three bidirectional 8-bit I/O ports (C, G and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports G and L), output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA register. A memory mapped address is also reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O ports.) Figure 3 shows the I/O port configurations. The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below:

	CONFIGURATION	DATA	Port Set-Up
	Register	Register
	0	0	Hi-Z Input
			(TRI-STATE Output)
	0	1	Input with Weak Pull-Up
	1	0	Push-Pull Zero Output
	1	1	Push-Pull One Output

TL/DD/12524 ± 5

FIGURE 3. I/O Port Configurations

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs.

Port L supports Multi-Input Wakeup (MIWU) on all eight pins. L4 and L5 are used for the timer input functions T2A and T2B.

Port L has the following alternate features:

L0 MIWU

L1 MIWU

L2 MIWU

L3 MIWU

L4 MIWU or T2A

L5 MIWU or T2B

L6 MIWU

L7 MIWU

Port G is an 8-bit port with 5 I/O pins (G0, G2 ± G5), an input pin (G6), and two dedicated output pins (G1 and G7). Pins G0 and G2 ± G6 all have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WDOUT WATCHDOG output, while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO clock output. With the single-pin R/C oscillator mask option selected, G7 serves as a general purpose input pin, but is also used to bring the device out of HALT mode with a low to high transition. There are two registers associated with the G Port, a data register and a configuration register. Therefore, each of the 5 I/O bits (G0, G2 ± G5) can be individually configured under software control.

Since G6 is an input only pin and G7 is the dedicated CKO clock output pin or general purpose input (R/C clock configuration), the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will return zeros.

Note that the chip will be placed in the HALT mode by writing a ``1'' to bit 7 of the Port G Data Register. Similarly the chip will be placed in the IDLE mode by writing a ``1'' to bit 6 of the Port G Data Register.

Writing a ``1'' to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay after HALT when the R/C clock configuration is used.

	Config Reg.	Data Reg.
G7	CLKDLY	HALT
G6	Alternate SK	IDLE

Port G has the following alternate features:

G0 INTR (External Interrupt Input)

G2 T1B (Timer T1 Capture Input)

G3 T1A (Timer T1 I/O)

G4 SO (MICROWIRE Serial Data Output)

G5 SK (MICROWIRE Serial Clock)

G6 SI (MICROWIRE Serial Data Input)

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Pin Descriptions (Continued)

Port G has the following dedicated functions:

G1 WDOUT WATCHDOG and/or Clock Monitor dedicated output

G7 CKO Oscillator dedicated output or general purpose input

Port C is an 8-bit I/O port. The 28-pin device does not have a full complement of Port C pins. The unavailable pins are not terminated. A read operation for these unterminated pins will return unpredictable values.

Port I is an 8-bit Hi-Z input port. The 28-pin device does not have a full complement of Port I pins. The unavailable pins are not terminated (i.e. they are floating). A read operation from these unterminated pins will return unpredictable values. The user should ensure that the software takes this into account by either masking out these inputs, or else restricting the accesses to bit operations only. If unterminated, Port I pins will draw power only when addressed. The I port leakage current may be higher in 28-pin devices.

Port D is a recreated 8-bit output port that is preset high when RESET goes low. D port recreation is one clock cycle behind the normal port timing. The user can tie two or more D port outputs (except D2 pin) together in order to get a higher drive.

Functional Description

The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on Harvard architecture, permits transfer of data from ROM to RAM.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (tc) cycle time.

There are five CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.

All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).

PROGRAM MEMORY

Program memory consists of 4 kbytes of OTP EPROM. These bytes may hold program instructions or constant data (data tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit program counter (PC). All interrupts vector to program memory location 0FF Hex.

The device can be configured to inhibit external reads of the program memory. This is done by programming the Security Byte.

SECURITY FEATURE

The program memory array has an associate Security Byte that is located outside of the program address range. This byte can be addressed only from programming mode by a programmer tool.

Security is an optional feature and can only be asserted after the memory array has been programmed and verified. A secured part will read all 00(hex) by a programmer. The part will fail Blank Check and will fail Verify operations. A Read operation will fill the programmer's memory with 00(hex). The Security Byte itself is always readable with a value of 00(hex) if unsecure and FF(hex) if secure.

DATA MEMORY

The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer). Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers.

The device has 128 bytes of RAM. Sixteen bytes of RAM are mapped as ``registers'' at addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP, and B are memory mapped into this space at address locations 0FC to 0FE Hex respectively, with the other registers (other than reserved register 0FF) being available for general usage.

The instruction set permits any bit in memory to be set, reset or tested. All I/O and registers on the device (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.

Reset

The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is pulled low. Upon initialization, the data and configuration registers for Ports L, G, and C are cleared, resulting in these Ports being initialized to the TRI-STATE mode. Pin G1 of the G Port is an exception (as noted below) since pin G1 is dedicated as the WATCHDOG and/or Clock Monitor error output pin. Port D is initialized high with RESET. The PC, PSW, CNTRL, ICNTRL, and T2CNTRL control registers are cleared. The Multi-Input Wakeup registers WKEN, WKEDG, and WKPND are cleared. The Stack Pointer, SP, is initialized to 06F Hex.

The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, and with both the WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock Monitor detector circuits are inhibited during reset. The WATCHDOG service window bits are initialized to the maximum WATCHDOG service window of 64k tc clock cycles. The Clock Monitor bit is initialized high, and will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor

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Reset (Continued)

error will cause an active low error output on pin G1. This error output will continue until 16 ± 32 tc clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE mode.

The external RC network shown in Figure 4 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes.

Note: In continual state of reset, the device will draw excessive current.

TL/DD/12524 ± 6

RC l 5 c Power Supply Rise Time

FIGURE 4. Recommended Reset Circuit

Oscillator Circuits

The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz. The CKO output clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction cycle clock (1/tc).

Figure 5 shows the Crystal and R/C diagrams.

TL/DD/12524 ± 7

FIGURE 5. Crystal and R/C Oscillator Diagrams

CRYSTAL OSCILLATOR

CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator.

Table I shows the component values required for various standard crystal values.

TABLE I. Crystal Oscillator Configuration, TA e 25§C

	R1	R2	C1	C2		CKI Freq	Conditions
	(kX)	(MX)	(pF)	(pF)		(MHz)
	0	1	30	30	± 36	10	VCC e 5V
	0	1	30	30	± 36	4	VCC e 5V
	0	1	200	100	± 150	0.455	VCC e 5V

R/C OSCILLATOR

By selecting CKI as a single pin oscillator input, a single pin R/C oscillator circuit can be connected to it. CKO is available as a general purpose input, and/or HALT restart pin.

Table II shows the variation in the oscillator frequencies as functions of the component (R and C) values.

TABLE II. R/C Oscillator Configuration, TA e 25§C

	R	C	CKI Freq	Instr. Cycle	Conditions
	(kX)	(pF)	(MHz)	(ms)
	3.3	82	2.2 ± 2.7	3.7 ± 4.6	VCC e 5V
	5.6	100	1.1 ± 1.3	7.4 ± 9.0	VCC e 5V
	6.8	100	0.9 ± 1.1	8.8 ± 10.8	VCC e 5V

Note: 3k s R s 200k, 50 pF s C s 200 pF

Control Registers

CNTRL Register (Address XÊ00EE)

The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits:

SL1 & SL0 Select the MICROWIRE/PLUS clock divide

	by (00 e 2, 01 e 4, 1x e 8)
IEDG	External interrupt edge polarity select
	(0 e Rising edge, 1 e Falling edge)
MSEL	Selects G5 and G4 as MICROWIRE/PLUS
	signals
	SK and SO respectively

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Control Registers (Continued)

T1C0		Timer T1 Start/Stop control in timer
		Timer T1 Underflow Interrupt Pending Flag in
		timer mode 3
T1C1		Timer T1 mode control bit
T1C2		Timer T1 mode control bit
T1C3		Timer T1 mode control bit
T1C3		T1C2	T1C1	T1C0	MSEL	IEDG	SL1	SL0
Bit 7								Bit 0

PSW Register (Address XÊ00EF)

The PSW register contains the following select bits:

GIE	Global interrupt enable (enables interrupts)
EXEN	Enable external interrupt
BUSY	MICROWIRE/PLUS busy shifting flag
EXPND	External interrupt pending
T1ENA	Timer T1 Interrupt Enable for Timer Underflow
	or T1A Input capture edge

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3)

CCarry Flag

HC		Half Carry Flag
HC	C	T1PNDA	T1ENA	EXPND	BUSY	EXEN	GIE
Bit 7							Bit 0

The Half-Carry bit is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and RC (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC, SUBC, RRC and RLC instructions affect the carry and Half Carry flags.

ICNTRL Register (Address XÊ00E8)

The ICNTRL register contains the following bits:

T1ENB Timer T1 Interrupt Enable for T1B Input capture edge

T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge

WEN		Enable MICROWIRE/PLUS interrupt
WPND		MICROWIRE/PLUS interrupt pending
T0EN		Timer T0 Interrupt Enable (Bit 12 toggle)
T0PND		Timer T0 Interrupt pending
LPENL		Port Interrupt Enable (Multi-Input Wak-
		eup/Interrupt)
		Bit 7 could be used as a flag
T2CNTRL		Register (Address XÊ00C6)
Unused	LPEN		T0PND	T0EN	WPND	WEN	T1PNDB	T1ENB
Bit 7								Bit 0

The T2CNTRL register contains the following bits:

T2ENB Timer T2 Interrupt Enable for T2B Input capture edge

T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge

T2ENA Timer T2 Interrupt Enable for Timer Underflow or T2A Input capture edge

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)

T2C0 Timer T2 Start/Stop control in timer modes 1 and 2 Timer T2 Underflow Interrupt Pending Flag in timer mode 3

T2C1 Timer T2 mode control bit

T2C2 Timer T2 mode control bit

T2C3 Timer T2 mode control bit

T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB

Bit 7

Bit 0

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Timers

The device contains a very versatile set of timers (T0, T1, T2). All timers and associated autoreload/capture registers power up containing random data.

TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining real time and low power with the IDLE mode. This IDLE mode support is furnished by the IDLE timer T0, which is a 16-bit timer. The Timer T0 runs continuously at the fixed rate of the instruction cycle clock, tc. The user cannot read or write to the IDLE Timer T0, which is a count down timer.

The Timer T0 supports the following functions:

Exit out of the Idle Mode (See Idle Mode description) WATCHDOG logic (See WATCHDOG description) Start up delay out of the HALT mode

The IDLE Timer T0 can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the T0PND pending flag, and will occur every 4 ms at the maximum clock frequency (tc e 1 ms). A control flag T0EN allows the interrupt from the thirteenth bit of Timer T0 to be enabled or disabled. Setting T0EN will enable the interrupt, while resetting it will disable the interrupt.

TIMER T1 AND TIMER T2

The device has a set of two powerful timer/counter blocks, T1 and T2. The associated features and functioning of a timer block are described by referring to the timer block Tx. Since the two timer blocks, T1 and T2, are identical, all comments are equally applicable to either timer block.

Each timer block consists of a 16-bit timer, Tx, and two supporting 16-bit autoreload/capture registers, RxA and RxB. Each timer block has two pins associated with it, TxA and TxB. The pin TxA supports I/O required by the timer block, while the pin TxB is an input to the timer block. The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Capture mode.

The control bits TxC3, TxC2, and TxC1 allow selection of the different modes of operation.

Mode 1. Processor Independent PWM Mode

As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention.

The user only has to define the parameters of the PWM signal (ON time and OFF time). Once begun, the timer block will continuously generate the PWM signal completely independent of the microcontroller. The user software services the timer block only when the PWM parameters require updating.

In this mode the timer Tx counts down at a fixed rate of tc. Upon every underflow the timer is alternately reloaded with the contents of supporting registers, RxA and RxB. The very first underflow of the timer causes the timer to reload from the register RxA. Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register RxB.

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the timer for PWM mode operation.

Figure 6 shows a block diagram of the timer in PWM mode.

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FIGURE 6. Timer in PWM Mode

The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.

Underflows from the timer are alternately latched into two pending flags, TxPNDA and TxPNDB. The user must reset these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be reloaded into the timer. Resetting the timer enable flags will disable the associated interrupts.

Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose to interrupt on both edges of the PWM output.

Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent PWM mode described above. The main difference is that the timer, Tx, is clocked by the input signal from the TxA pin. The Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to be clocked either on a positive or negative edge from the TxA pin. Underflows from the timer are latched into the TxPNDA pending flag. Setting the TxENA control flag will cause an interrupt when the timer underflows.

In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB control flag is set. The occurrence of a positive edge on the TxB input pin is latched into the TxPNDB flag.

Figure 7 shows a block diagram of the timer in External Event Counter mode.

Note: The PWM output is not available in this mode since the TxA pin is being used as the counter input clock.

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Timers (Continued)

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FIGURE 7. Timer in External Event Counter Mode

Mode 3. Input Capture Mode

The device can precisely measure external frequencies or time external events by placing the timer block, Tx, in the input capture mode.

In this mode, the timer Tx is constantly running at the fixed tc rate. The two registers, RxA and RxB, act as capture registers. Each register acts in conjunction with a pin. The register RxA acts in conjunction with the TxA pin and the register RxB acts in conjunction with the TxB pin.

The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control bits, TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate interrupts. The occurrence of the specified trigger condition on the TxA and TxB pins will be respectively latched into the pending flags, TxPNDA and TxPNDB. The control flag TxENA allows the interrupt on TxA to be either enabled or disabled. Setting the TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the TxA pin. Similarly, the flag TxENB controls the interrupts from the TxB pin.

Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxC0 pending flag (the TxC0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is enabled with the TxENA control flag. When a TxA interrupt occurs in the Input Capture mode, the user must check both whether a TxA input capture or a timer underflow (or both) caused the interrupt.

Figure 8 shows a block diagram of the timer in Input Capture mode.

TIMER CONTROL FLAGS

The timers T1 and T2 have indentical control structures. The control bits and their functions are summarized below.

TxC0	Timer Start/Stop control in Modes 1 and 2
	(Processor Independent PWM and External
	Event Counter), where 1 e Start, 0 e Stop
	Timer Underflow Interrupt Pending Flag in
	Mode 3 (Input Capture)
TxPNDA	Timer Interrupt Pending Flag
TxPNDB	Timer Interrupt Pending Flag
TxENA	Timer Interrupt Enable Flag
TxENB	Timer Interrupt Enable Flag
	1 e Timer Interrupt Enabled
	0 e Timer Interrupt Disabled
TxC3	Timer mode control
TxC2	Timer mode control
TxC1	Timer mode control

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FIGURE 8. Timer in Input Capture Mode

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