MC1496P1
Device
Operating
Temperature Range
Package
SEMICONDUCTOR
TECHNICAL DATA
BALANCED
MODULATORS/DEMODULA T ORS
ORDERING INFORMATION
MC1496D
MC1496P
T
A
= 0°C to +70°C
SO–14
Plastic DIP
PIN CONNECTIONS
Order this document by MC1496/D
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
P SUFFIX
PLASTIC PACKAGE
CASE 646
Signal Input
1
2
3
4
5
6
7
10
11
14
13
12
9
N/C
Output
Bias
Signal Input
Gain Adjust
Gain Adjust
Input Carrier
8
V
EE
N/C
Output
N/C
Carrier Input
N/C
14
1
14
1
MC1496BP Plastic DIPT
A
= –40°C to +125°C
1
MOTOROLA ANALOG IC DEVICE DATA
These devices were designed for use where the output voltage is a
product of an input voltage (signal) and a switching function (carrier). Typical
applications include suppressed carrier and amplitude modulation,
synchronous detection, FM detection, phase detection, and chopper
applications. See Motorola Application Note AN531 for additional design
information.
• Excellent Carrier Suppression –65 dB typ @ 0.5 MHz
Excellent Carrier Suppression –50 dB typ @ 10 MHz
• Adjustable Gain and Signal Handling
• Balanced Inputs and Outputs
• High Common Mode Rejection –85 dB typical
This device contains 8 active transistors.
Figure 1. Suppressed
Carrier Output
Waveform
Figure 2. Suppressed
Carrier Spectrum
Figure 3. Amplitude
Modulation Output
Waveform
Figure 4. Amplitude–Modulation Spectrum
I
C
= 500 kHz, I
S
= 1.0 kHz
I
C
= 500 kHz
I
S
= 1.0 kHz
60
40
20
0
Log Scale Id
499 kHz 500 kHz 501 kHz
I
C
= 500 kHz
I
S
= 1.0 kHz
I
C
= 500 kHz
I
S
= 1.0 kHz
499 kHz 500 kHz 501 kHz
Linear Scale
10
8.0
6.0
4.0
2.0
0
Motorola, Inc. 1996 Rev 4
MC1496, B
2
MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
(T
A
= 25°C, unless otherwise noted.)
Rating
Symbol Value Unit
Applied Voltage
(V6 – V8, V10 – V1, V12 – V8, V12 – V10, V8 – V4,
V8 – V1, V10 – V4, V6 – V10, V2 – V5, V3 – V5)
∆V 30 Vdc
Differential Input Signal V8 – V10
V4 – V1
+5.0
±(5+I5R
e
)
Vdc
Maximum Bias Current I
5
10 mA
Thermal Resistance, Junction–to–Air
Plastic Dual In–Line Package
R
θJA
100 °C/W
Operating Temperature Range T
A
0 to +70
°C
Storage Temperature Range T
stg
–65 to +150
°C
NOTE: ESD data available upon request.
ELECTRICAL CHARACTERISTICS (V
CC
= 12 Vdc, V
EE
= –8.0 Vdc, I5 = 1.0 mAdc, R
L
= 3.9 kΩ, R
e
= 1.0 kΩ, T
A
= T
low
to T
high
,
all input and output characteristics are single–ended, unless otherwise noted.)
Characteristic
Fig. Note Symbol Min Typ Max Unit
Carrier Feedthrough
V
C
= 60 mVrms sine wave and
offset adjusted to zero
V
C
= 300 mVpp square wave:
offset adjusted to zero
offset not adjusted
f
C
= 1.0 kHz
f
C
= 10 MHz
f
C
= 1.0 kHz
f
C
= 1.0 kHz
5 1 V
CFT
–
–
–
–
40
140
0.04
20
–
–
0.4
200
µVrms
mVrms
Carrier Suppression
f
S
= 10 kHz, 300 mVrms
f
C
= 500 kHz, 60 mVrms sine wave
f
C
= 10 MHz, 60 mVrms sine wave
5 2 V
CS
40
–
65
50
–
–
dB
k
Transadmittance Bandwidth (Magnitude) (R
L
= 50 Ω)
Carrier Input Port, V
C
= 60 mVrms sine wave
f
S
= 1.0 kHz, 300 mVrms sine wave
Signal Input Port, V
S
= 300 mVrms sine wave
|V
C
| = 0.5 Vdc
8 8 BW
3dB
–
–
300
80
–
–
MHz
Signal Gain (V
S
= 100 mVrms, f = 1.0 kHz; |V
C
|= 0.5 Vdc) 10 3 A
VS
2.5 3.5 – V/V
Single–Ended Input Impedance, Signal Port, f = 5.0 MHz
Parallel Input Resistance
Parallel Input Capacitance
6 –
r
ip
c
ip
–
–
200
2.0
–
–
kΩ
pF
Single–Ended Output Impedance, f = 10 MHz
Parallel Output Resistance
Parallel Output Capacitance
6 –
r
op
c
oo
–
–
40
5.0
–
–
kΩ
pF
Input Bias Current
7 –
µA
I
bS
+
I1
)
I4
2
;I
bC
+
I8
)
I10
2
I
bS
I
bC
–
–
12
12
30
30
Input Offset Current
I
ioS
= I1–I4; I
ioC
= I8–I10
7 –
I
ioS
I
ioC
–
–
0.7
0.7
7.0
7.0
µA
Average Temperature Coefficient of Input Offset Current
(T
A
= –55°C to +125°C)
7 – TC
Iio
– 2.0 – nA/°C
Output Offset Current (I6–I9) 7 – I
oo
– 14 80 µA
Average Temperature Coefficient of Output Offset Current
(T
A
= –55°C to +125°C)
7 – TC
Ioo
– 90 – nA/°C
Common–Mode Input Swing, Signal Port, f
S
= 1.0 kHz 9 4 CMV – 5.0 – Vpp
Common–Mode Gain, Signal Port, f
S
= 1.0 kHz, |V
C
|= 0.5 Vdc 9 – ACM – –85 – dB
Common–Mode Quiescent Output V oltage (Pin 6 or Pin 9) 10 – V
out
– 8.0 – Vpp
Differential Output Voltage Swing Capability 10 – V
out
– 8.0 – Vpp
Power Supply Current I6 +I12
Power Supply Current I14
7 6 I
CC
I
EE
–
–
2.0
3.0
4.0
5.0
mAdc
DC Power Dissipation 7 5 P
D
– 33 – mW
MC1496, B
3
MOTOROLA ANALOG IC DEVICE DATA
GENERAL OPERATING INFORMATION
Carrier Feedthrough
Carrier feedthrough is defined as the output voltage at
carrier frequency with only the carrier applied (signal
voltage = 0).
Carrier null is achieved by balancing the currents in the
differential amplifier by means of a bias trim potentiometer
(R1 of Figure 5).
Carrier Suppression
Carrier suppression is defined as the ratio of each
sideband output to carrier output for the carrier and signal
voltage levels specified.
Carrier suppression is very dependent on carrier input
level, as shown in Figure 22. A low value of the carrier does
not fully switch the upper switching devices, and results in
lower signal gain, hence lower carrier suppression. A higher
than optimum carrier level results in unnecessary device and
circuit carrier feedthrough, which again degenerates the
suppression figure. The MC1496 has been characterized
with a 60 mVrms sinewave carrier input signal. This level
provides optimum carrier suppression at carrier frequencies
in the vicinity of 500 kHz, and is generally recommended for
balanced modulator applications.
Carrier feedthrough is independent of signal level, V
S
.
Thus carrier suppression can be maximized by operating
with large signal levels. However, a linear operating mode
must be maintained in the signal–input transistor pair – or
harmonics of the modulating signal will be generated and
appear in the device output as spurious sidebands of the
suppressed carrier. This requirement places an upper limit on
input–signal amplitude (see Figure 20). Note also that an
optimum carrier level is recommended in Figure 22 for good
carrier suppression and minimum spurious sideband
generation.
At higher frequencies circuit layout is very important in
order to minimize carrier feedthrough. Shielding may be
necessary in order to prevent capacitive coupling between
the carrier input leads and the output leads.
Signal Gain and Maximum Input Level
Signal gain (single–ended) at low frequencies is defined
as the voltage gain,
A
VS
+
V
o
V
S
+
R
L
R
e
)
2r
e
where r
e
+
26 mV
I5(mA)
A constant dc potential is applied to the carrier input terminals
to fully switch two of the upper transistors “on” and two
transistors “off” (V
C
= 0.5 Vdc). This in effect forms a cascode
differential amplifier.
Linear operation requires that the signal input be below a
critical value determined by R
E
and the bias current I5.
V
S
p
I5 R
E
(Volts peak)
Note that in the test circuit of Figure 10, V
S
corresponds to a
maximum value of 1.0 V peak.
Common Mode Swing
The common–mode swing is the voltage which may be
applied to both bases of the signal differential amplifier,
without saturating the current sources or without saturating
the differential amplifier itself by swinging it into the upper
switching devices. This swing is variable depending on the
particular circuit and biasing conditions chosen.
Power Dissipation
Power dissipation, P
D
, within the integrated circuit package
should be calculated as the summation of the voltage–current
products at each port, i.e. assuming V12 = V6, I5 = I6 = I12
and ignoring base current, P
D
=
2 I5 (V6 – V14) + I5)
V5 – V14 where subscripts refer to pin numbers.
Design Equations
The following is a partial list of design equations needed to
operate the circuit with other supply voltages and input
conditions.
A. Operating Current
The internal bias currents are set by the conditions at Pin 5.
Assume:
I5 = I6 = I12,
I
B
tt
I
C
for all transistors
then :
R5
+
V
*
*
f
I5
*
500
W
where: R5 is the resistor between
where: Pin 5 and ground
where: φ = 0.75 at T
A
= +25°C
The MC1496 has been characterized for the condition
I
5
= 1.0 mA and is the generally recommended value.
B. Common–Mode Quiescent Output Voltage
V6 = V12 = V+ – I5 R
L
Biasing
The MC1496 requires three dc bias voltage levels which
must be set externally. Guidelines for setting up these three
levels include maintaining at least 2.0 V collector–base bias
on all transistors while not exceeding the voltages given in
the absolute maximum rating table;
30 Vdc
w
[(V6, V12) – (V8, V10)]
w
2 Vdc
30 Vdc
w
[(V8, V10) – (V1, V4)]
w
2.7 Vdc
30 Vdc
w
[(V1, V4) – (V5)]
w
2.7 Vdc
The foregoing conditions are based on the following
approximations:
V6 = V12, V8 = V10, V1 = V4
Bias currents flowing into Pins 1, 4, 8 and 10 are transistor
base currents and can normally be neglected if external bias
dividers are designed to carry 1.0 mA or more.
Transadmittance Bandwidth
Carrier transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
g
21C
+
i
o
(each sideband)
v
s
(signal)
V
o
+
0
Signal transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
g
21S
+
i
o
(signal)
v
s
(signal)
V
c
+
0.5 Vdc, V
o
+
0
MC1496, B
4
MOTOROLA ANALOG IC DEVICE DATA
Coupling and Bypass Capacitors
Capacitors C1 and C2 (Figure 5) should be selected for a
reactance of less than 5.0 Ω at the carrier frequency.
Output Signal
The output signal is taken from Pins 6 and 12 either
balanced or single–ended. Figure 1 1 shows the output levels
of each of the two output sidebands resulting from variations
in both the carrier and modulating signal inputs with a
single–ended output connection.
Negative Supply
V
EE
should be dc only. The insertion of an RF choke in
series with V
EE
can enhance the stability of the internal
current sources.
Signal Port Stability
Under certain values of driving source impedance,
oscillation may occur. In this event, an RC suppression
network should be connected directly to each input using
short leads. This will reduce the Q of the source–tuned
circuits that cause the oscillation.
Signal Input
(Pins 1 and 4)
510
10 pF
An alternate method for low–frequency applications is to
insert a 1.0 kΩ resistor in series with the input (Pins 1, 4). In
this case input current drift may cause serious degradation of
carrier suppression.
TEST CIRCUITS
NOTE: Shielding of input and output leads may be needed
to properly perform these tests.
Figure 5. Carrier Rejection and Suppression
Figure 6. Input–Output Impedance
Figure 7. Bias and Offset Currents
Figure 8. Transconductance Bandwidth
0.01
µ
F
2.0 k
–8.0 Vdc
I6
I9
1.0 k
I7
I8
6.8 k
Z
out
+V
o
+
+V
o
I9
3
R
L
3.9 k
V
CC
12 Vdc
8
C1
0.1
µ
F
MC1496
1.0 k
2
R
e
1.0 k
C
2
0.1
µ
F
51
10 k
Modulating
Signal Input
Carrier
Input
V
C
Carrier Null
515110 k
50 k
R1
V
S
–V
o
R
L
3.9 k
I6
I4
6
14 5
12
–
2
R
e
= 1.0 k
3
Z
in
0.5 V
8
10
I1
4
1
–V
o
10
1
6
4
14 5
12
6.8 k
V
–
I10
I5
–8.0 Vdc
V
EE
1.0 k
MC1496
MC1496
MC1496
6
14 5
12
I10
6.8 k
–8.0 Vdc
V
EE
V
CC
12 Vdc
2
R
e
= 1.0 k
3
1.0 k
Modulating
Signal Input
Carrier
Input
V
C
V
S
0.1
µ
F
0.1
µ
F
1.0 k
51
1.0 k
14
5
6
12
1.0 k
23
R
e
V
CC
12 Vdc
2.0 k
+V
o
–V
o
6.8 k
10 k
Carrier Null
5110 k
50 k
V
–
–8.0 Vdc
V
EE
50 50
8
10
4
1
8
10
4
1
51
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