Motorola MC14599BCL, MC14599BCP, MC14099BCL, MC14099BCP, MC14099BDW Datasheet

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MOTOROLA CMOS LOGIC DATAMC14099B MC14599B

246

  

The MC14099B and MC14599B are 8–bit addressable latches. Data is

entered in serial form when the appropriate latch is addressed (via address

pins A0, A1, A2) and write disable is in the low state. Chip enable must be

high for w riting into MC14599B. F or the MC14599B the data pin is a

bidirectional data port and for the MC14099B the input is a unidirectional

write only port. The Write/Read

line controls this port in the MC14599B.

The d ata is p resented in p arallel a t the output of t he eight latches

independently of the state of Write Disable, Write/Read

or Chip Enable.

A Master Reset capability is available on both parts.

• Serial Data Input

• Parallel Output

• Master Reset

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–Power

Schottky TTL Load over the Rated Temperature Range

• MC14099B pin for pin compatible with CD4099B

MAXIMUM RATINGS* (Voltages Referenced to V

)

Symbol

Parameter

Value

Unit

DC Supply Voltage

– 0.5 to + 18.0

, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to V

+ 0.5

, I

out

Input or Output Current (DC or Transient),

per Pin

± 10

Power Dissipation, per Package†

500

stg

Storage Temperature

– 65 to + 150

Lead Temperature (8–Second Soldering)

260

*Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

C From 65

C To 125

Ceramic “L” Packages: – 12 mW/

C From 100

C To 125

MC14099B MC14599B

125

WRITE

DISABLE

DATA

RESET

DATA

RESET

WRITE

DISABLE

WRITE/

READ

PIN ASSIGNMENT

CHIP ENABLE

WRITE/READ

WRITE DISABLE

DATA

RESET

DECODER

LATCHES

DECODER

WRITE DISABLE

DATA

RESET

= 18

= 9

= 16

= 8



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 0

1/94



  





L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14099BCP Plastic

MC14099BCL Ceramic

MC14099BDW SOIC

= – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

L SUFFIX

CERAMIC

CASE 726

ORDERING INFORMATION

MC14599BCP Plastic

MC14599BCL Ceramic

P SUFFIX

PLASTIC

CASE 707

This device contains protection circuitry to

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

ages to this high–impedance circuit. For proper

operation, V

and V

out

should be constrained

to the range V

or V

out

)

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either V

or V

). Unused outputs must be left open.

= – 55° to 125°C for all packages.

MOTOROLA CMOS LOGIC DATA

247

MC14099B MC14599B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

– 55

125

Characteristic

Symbol

Vdc

Min

Max

Min

Typ #

Max

Min

ÎÎÎ

Max

Unit

Output Voltage

“0” Level

= V

or 0

5.0

—

0.05

—

0.05

—

ÎÎÎ

0.05

Vdc

“1” Level

= 0 or V

5.0

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

—

4.95

9.95

14.95

ÎÎÎ

—

Vdc

Input Voltage

“0” Level

= 4.5 or 0.5 Vdc)

= 9.0 or 1.0 Vdc)

= 13.5 or 1.5 Vdc)

5.0

—

1.5

3.0

4.0

—

2.25

4.50

6.75

1.5

3.0

4.0

—

ÎÎÎ

1.5

3.0

4.0

Vdc

“1” Level

= 0.5 or 4.5 Vdc)

= 1.0 or 9.0 Vdc)

= 1.5 or 13.5 Vdc)

5.0

3.5

7.0

—

3.5

7.0

2.75

5.50

8.25

—

3.5

7.0

ÎÎÎ

—

Vdc

Output Drive Current

= 2.5 Vdc) Source

= 4.6 Vdc)

= 9.5 Vdc)

= 13.5 Vdc)

5.0

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

—

mAdc

= 0.4 Vdc) Sink

= 0.5 Vdc)

= 1.5 Vdc)

5.0

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

ÎÎÎ

—

mAdc

Input Current

—

± 0.1

—

±0.00001

± 0.1

—

ÎÎÎ

± 1.0

µAdc

Input Capacitance

= 0)

—

5.0

7.5

—

ÎÎÎ

—

Input Capacitance

MC14599B — Data (pin 3)

= 0)

—

22.5

—

ÎÎÎ

—

Quiescent Current

(Per Package)

5.0

—

5.0

—

0.005

0.010

0.015

5.0

—

ÎÎÎ

150

300

600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent,

Per Package)

= 50 pF on all outputs, all

buffers switching)

5.0

= (1.5 µA/kHz) f + I

= (3.0 µA/kHz) f + I

= (4.5 µA/kHz) f + I

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

**The formulas given are for the typical characteristics only at 25

†To calculate total supply current at loads other than 50 pF:

) = I

(50 pF) + (C

– 50) Vfk

where: I

is in µA (per package), C

in pF, V = (V

– V

) in volts, f in kHz is input frequency, and k = 0.004.

MOTOROLA CMOS LOGIC DATAMC14099B MC14599B

248

SWITCHING CHARACTERISTICS* (C

= 50 pF, T

= 25

Characteristic

ÎÎÎÎ

Symbol

Vdc

ÎÎÎÎ

Min

Typ #

Max

Unit

Output Rise and Fall Time

TLH

, t

THL

= (1.35 ns/pF) C

+ 32 ns

TLH

, t

THL

= (0.6 ns/pF) C

+ 20 ns

TLH

, t

THL

= (0.4 ns/pF) C

+ 20 ns

ÎÎÎÎ

TLH

THL

5.0

ÎÎÎÎ

—

100

200

100

Propagation Delay Time

Data to Output Q

ÎÎÎÎ

PHL

PLH

5.0

ÎÎÎÎ

—

200

400

150

100

Write Disable to Output Q

ÎÎÎÎ

5.0

ÎÎÎÎ

—

200

400

160

120

Reset to Output Q

ÎÎÎÎ

5.0

ÎÎÎÎ

—

175

350

160

130

CE to Output Q (MC14599B only)

ÎÎÎÎ

5.0

ÎÎÎÎ

—

225

100

450

200

150

Propagation Delay Time, MC14599B only

Chip Enable, Write/Read

to Data

ÎÎÎÎ

PHL

PLH

5.0

ÎÎÎÎ

—

200

400

160

130

Address to Data

ÎÎÎÎ

5.0

ÎÎÎÎ

—

200

400

180

150

Pulse Widths

Reset

ÎÎÎÎ

w(H)

w(L)

5.0

ÎÎÎÎ

150

—

Write Disable

ÎÎÎÎ

5.0

ÎÎÎÎ

320

160

120

160

—

Set Up Time

Data to Write Disable

ÎÎÎÎ

5.0

ÎÎÎÎ

100

—

Hold Time

Write Disable to Data

ÎÎÎÎ

5.0

ÎÎÎÎ

150

—

Set Up Time

Address to Write Disable

ÎÎÎÎ

5.0

ÎÎÎÎ

100

—

Removal Time

Write Disable to Address

ÎÎÎÎ

rem

5.0

ÎÎÎÎ

– 80

– 40

—

*The formulas given are for the typical characteristics only at 25

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

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