August 1986
Revised March 2000
DM74LS393
Dual 4-Bit Binary Counter
General Description
Each of these monolithic circuits contains eight masterslave flip-flops and additional gating to implement two individual four-bit counters in a single package. The DM74LS393 comprises two independent four-bit binary counters each having a clear and a clock input. N-bit binary counters can be implemented with each package providing the capability of divide-by-256. The DM74LS393 has parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system-timing signals.
Features
■Dual version of the popular DM74LS93
■DM74LS393 dual 4-bit binary counter with individual clocks
■Direct clear for each 4-bit counter
■Dual 4-bit versions can significantly improve system densities by reducing counter package count by 50%
■Typical maximum count frequency 35 MHz
■Buffered outputs reduce possibility of collector commutation
Ordering Code:
Order Number |
Package Number |
Package Description |
|
|
|
DM74LS393M |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow |
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|
|
DM74LS373N |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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|
|
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Function Table |
Counter Sequence (Each Counter)
Count |
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Outputs |
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QD |
QC |
QB |
QA |
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0 |
L |
L |
L |
L |
|
1 |
L |
L |
L |
H |
|
2 |
L |
L |
H |
L |
|
3 |
L |
L |
H |
H |
|
4 |
L |
H |
L |
L |
|
5 |
L |
H |
L |
H |
|
6 |
L |
H |
H |
L |
|
7 |
L |
H |
H |
H |
|
8 |
H |
L |
L |
L |
|
9 |
H |
L |
L |
H |
|
10 |
H |
L |
H |
L |
|
11 |
H |
L |
H |
H |
|
12 |
H |
H |
L |
L |
|
13 |
H |
H |
L |
H |
|
14 |
H |
H |
H |
L |
|
15 |
H |
H |
H |
H |
|
|
|
|
|
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|
H = HIGH Logic Level
L = LOW Logic Level
Counter Binary Bit-4 Dual DM74LS393
© 2000 Fairchild Semiconductor Corporation |
DS006434 |
www.fairchildsemi.com |
DM74LS393
Logic Diagram
www.fairchildsemi.com |
2 |
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