June 1986
Revised March 2000
DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig- gered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74LS109AM |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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DM74LS109AN |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Function Table |
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Inputs |
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Outputs |
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PR |
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CLR |
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CLK |
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J |
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K |
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Q |
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Q |
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L |
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H |
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X |
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X |
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X |
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H |
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L |
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H |
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L |
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X |
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X |
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X |
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L |
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H |
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L |
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L |
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X |
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X |
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X |
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H (Note 1) |
H (Note 1) |
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H |
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H |
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− |
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L |
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L |
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L |
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H |
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H |
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H |
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− |
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H |
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L |
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Toggle |
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H |
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H |
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− |
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L |
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H |
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Q0 |
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Q |
0 |
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H |
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H |
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− |
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H |
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H |
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H |
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L |
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H |
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H |
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L |
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X |
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X |
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Q0 |
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Q |
0 |
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H = HIGH Logic Level |
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L = LOW Logic Level |
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X = Either LOW or HIGH Logic Level |
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− = Rising Edge of Pulse |
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Q0 = The output logic level of Q before the indicated input conditions were |
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established. |
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Toggle = Each output changes to the complement of its previous level on |
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each active transition of the clock pulse. |
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Note 1: This configuration is nonstable; that is, it will not persist when pre- |
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set and/or clear inputs return to their inactive (HIGH) state. |
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Outputs Complementary and Clear, Preset, with Flop-Flip K-J Triggered-Edge-Positive Dual DM74LS109A
© 2000 Fairchild Semiconductor Corporation |
DS006368 |
www.fairchildsemi.com |
DM74LS109A
Absolute Maximum Ratings(Note 2)
Supply Voltage |
7V |
Note 2: The “Absolute Maximum Ratings” are those values beyond which |
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the safety of the device cannot be guaranteed. The device should not be |
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Input Voltage |
7V |
operated at these limits. The parametric values defined in the Electrical |
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Characteristics tables are not guaranteed at the absolute maximum ratings. |
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Operating Free Air Temperature Range |
0°C to +70°C |
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The “Recommended Operating Conditions” table will define the conditions |
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Storage Temperature Range |
−65°C to +150°C |
for actual device operation. |
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Recommended Operating Conditions
Symbol |
Parameter |
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Min |
Nom |
Max |
Units |
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VCC |
Supply Voltage |
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4.75 |
5 |
5.25 |
V |
VIH |
HIGH Level Input Voltage |
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2 |
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V |
VIL |
LOW Level Input Voltage |
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0.8 |
V |
IOH |
HIGH Level Output Current |
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−0.4 |
mA |
IOL |
LOW Level Output Current |
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8 |
mA |
fCLK |
Clock Frequency (Note 3) |
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0 |
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25 |
MHz |
fCLK |
Clock Frequency (Note 4) |
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0 |
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20 |
MHz |
tW |
Pulse Width |
Clock HIGH |
18 |
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(Note 3) |
Preset LOW |
15 |
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ns |
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Clear LOW |
15 |
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tW |
Pulse Width |
Clock HIGH |
25 |
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(Note 4) |
Preset LOW |
20 |
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ns |
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Clear LOW |
20 |
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tSU |
Setup Time |
Data HIGH |
30− |
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ns |
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(Note 3)(Note 5) |
Data LOW |
20− |
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tSU |
Setup Time |
Data HIGH |
35− |
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ns |
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(Note 5)(Note 4) |
Data LOW |
25− |
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tH |
Hold Time (Note 6) |
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0− |
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ns |
TA |
Free Air Operating Temperature |
0 |
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70 |
°C |
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Note 3: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. |
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Note 4: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. |
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Note 5: The symbol (−) indicates the rising edge of the clock pulse is used for reference. |
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Note 6: TA = 25°C and VCC = 5V. |
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www.fairchildsemi.com |
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