August 1986
Revised March 2000
DM74LS166
8-Bit Parallel-In/Serial-Out Shift Register
General Description
These parallel-in or serial-in, serial-out shift registers feature gated clock inputs and an overriding clear input. All inputs are buffered to lower the drive requirements to one normalized load, and input clamping diodes minimize switching transients to simplify system design. The load mode is established by the shift/load input. When HIGH, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When LOW, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited.
Clocking is accomplished on the LOW-to-HIGH level edge of the clock pulse through a two-input NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking; holding either LOW enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is HIGH. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74LS166M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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DM74LS166WM |
M16B |
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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DM74LS166N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Register Shift Out-In/Serial-Parallel Bit-8 DM74LS166
© 2000 Fairchild Semiconductor Corporation |
DS006400 |
www.fairchildsemi.com |
DM74LS166
Function Table
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Inputs |
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Internal |
Output |
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Outputs |
QH |
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Clear |
Shift/ |
Clock |
Clock |
Serial |
Parallel |
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Load |
Inhibit |
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A…H |
Q A |
QB |
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L |
X |
X |
X |
X |
X |
L |
L |
L |
H |
X |
L |
L |
X |
X |
QA0 |
QB0 |
QH0 |
H |
L |
L |
− |
X |
a…h |
a |
b |
h |
H |
H |
L |
− |
H |
X |
H |
QAn |
QGn |
H |
H |
L |
− |
L |
X |
L |
QAn |
QGn |
H |
X |
H |
− |
X |
X |
QA0 |
QB0 |
QH0 |
H = HIGH Level (steady state) L = LOW Level (steady state)
X = Don’t Care (any input, including transitions) − = Transition from LOW-to-HIGH level
a…h = The level of steady-state input at inputs A through H, respectively
QA0, QB0, QH0 = The level of QA, QB, QH, respectively, before the indicated steady-state input conditions were established QAn, QGn, = The level of QA, QG, respectively, before the most recent − transition of the clock
Logic Diagram
Timing Diagram
Typical Clear, Shift, Load, Inhibit and Shift Sequences
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