Fairchild Semiconductor DM74LS259WM, DM74LS259N, DM74LS259MX, DM74LS259M, DM74LS259CW Datasheet
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August 1986
Revised March 2000
DM74LS259
8-Bit Addressable Latches
General Description
These 8-bit addressable latches are designed for general purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by controlling the clear and enable inputs as enumerated in the function table. In the addressable-latch mode, data at the datain terminal is written into the addressed latch. The addressed latch will follow the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held HIGH (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output will follow the level of the D input with all other outputs LOW. In the clear mode, all outputs are LOW and unaffected by the address and data inputs.
Features
■8-Bit parallel-out storage register performs serial-to-par- allel conversion with storage
■Asynchronous parallel clear
■Active high decoder
■Enable/disable input simplifies expansion
■Direct replacement for Fairchild DM9334
■Expandable for N-bit applications
■Four distinct functional modes
■Typical propagation delay times:
Enable-to-output |
18 ns |
Data-to-output |
16 ns |
Address-to-output |
21 ns |
Clear-to-output |
17 ns |
■ Fan-out |
|
IOL (sink current) |
8 mA |
IOH (source current) −0.4 mA ■ Typical ICC 22 mA
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74LS259M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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DM74LS259WM |
M16B |
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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DM74LS259N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Latches Addressable Bit-8 DM74LS259
© 2000 Fairchild Semiconductor Corporation |
DS006418 |
www.fairchildsemi.com |
DM74LS259
Connection Diagram
Function Table
Inputs |
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Output of |
Each |
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Addressed |
Other |
Function |
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Latch |
Output |
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Clear |
E |
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H |
L |
D |
Qi0 |
Addressable Latch |
|
H |
H |
Qi0 |
Qi0 |
Memory |
|
L |
L |
D |
L |
8-Line Demultiplexer |
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L |
H |
L |
L |
Clear |
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Latch Selection Table
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Select Inputs |
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Latch |
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Addressed |
C |
B |
A |
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L |
L |
L |
0 |
L |
L |
H |
1 |
L |
H |
L |
2 |
L |
H |
H |
3 |
H |
L |
L |
4 |
H |
L |
H |
5 |
H |
H |
L |
6 |
H |
H |
H |
7 |
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H = HIGH Level
L = LOW Level
D = the Level of the Data Input
Qi0 = the Level of Qi (i = 0, 1,…7, as Appropriate) before the Indicated Steady-State Input Conditions Were Established.
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