August 1986
Revised April 2000
DM74LS169A
Synchronous 4-Bit Up/Down Binary Counter
General Description
This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs all change at the same time when so instructed by the countenable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four masterslave flip-flops on the rising edge of the clock waveform.
This counter is fully programmable; that is, the outputs may each be preset either HIGH or LOW. The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry permits cascading counters for n-bit synchronous applications without additional gating. Both count-enable inputs (P and T) must be LOW to count. The direction of the count is determined by the level of the UP/DOWN input. When the input is HIGH, the counter counts UP; when LOW, it counts DOWN. Input T is fed forward to enable the carry outputs. The carry output thus
enabled will produce a low-level output pulse with a duration approximately equal to the high portion of the QA output when counting UP, and approximately equal to the low portion of the QA output when counting DOWN. This lowlevel overflow carry pulse can be used to enable succes- sively cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design.
This counter features a fully independent clock circuit. Changes at control inputs (enable P, enable T, load, UP/ DOWN), which modify the operating mode, have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
Features
■Fully synchronous operation for counting and programming.
■Internal look-ahead for fast counting.
■Carry output for n-bit cascading.
■Fully independent clock circuit
Ordering Code:
Order Number |
Package Number |
Package Description |
|
|
|
DM74LS169AM |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
|
|
|
DM74LS169AN |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
|
|
|
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Counter Binary Up/Down Bit-4 Synchronous DM74LS169A
© 2000 Fairchild Semiconductor Corporation |
DS006401 |
www.fairchildsemi.com |
DM74LS169A
Logic Diagram
www.fairchildsemi.com |
2 |
Timing Diagram
Typical Load, Count, and Inhibit Sequences
DM74LS169A
3 |
www.fairchildsemi.com |
Loading...