Fairchild Semiconductor DM74LS112AN, DM74LS112AMX, DM74LS112AM, DM74LS112ACW Datasheet

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August 1986

Revised March 2000

DM74LS112A

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description

This device contains two independent negative-edge-trig- gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

Ordering Code:

Order Number	Package Number	Package Description

DM74KS112AM	M16A	16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74LS112AN	N16E	16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

CLR

CLK

H (Note 1)

↓

Toggle

H = HIGH Logic Level

L = LOW Logic Level

X = Either LOW or HIGH Logic Level

↓ = Negative Going Edge of Pulse

Q0 = The output logic level before the indicated input conditions were established.

Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse.

Note 1: This configuration is nonstable; that is, it will not persist when preset and/or clear inputs return to their inactive (HIGH) level.

Outputs	DM74LS112A
	Triggered-Edge-Negative Dual
	Flop-Flip K-J Slave-Master
	Complementary and Clear, Preset, with

DS006382

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DM74LS112A

Absolute Maximum Ratings(Note 2)

Supply Voltage	7V	Note 2: The “Absolute Maximum Ratings” are those values beyond which
		the safety of the device cannot be guaranteed. The device should not be
Input Voltage	7V	operated at these limits. The parametric values defined in the Electrical
		Characteristics tables are not guaranteed at the absolute maximum ratings.
Operating Free Air Temperature Range	0°C to +70°C
		The “Recommended Operating Conditions” table will define the conditions
Storage Temperature Range	−65°C to +150°C	for actual device operation.

Recommended Operating Conditions

Symbol		Parameter		Min	Nom	Max	Units
VCC	Supply Voltage			4.75	5	5.25	V
VIH	HIGH Level Input Voltage			2			V
VIL	LOW Level Input Voltage					0.8	V
IOH	HIGH Level Output Current					−0.4	mA
IOL	LOW Level Output Current					8	mA
fCLK	Clock Frequency (Note 3)			0		30	MHz
fCLK	Clock Frequency (Note 5)			0		25	MHz
tW	Pulse Width		Clock HIGH	20
	(Note 3)		Preset LOW	25			ns

			Clear LOW	25

tW	Pulse Width		Clock HIGH	25
	(Note 5)		Preset LOW	30			ns

			Clear LOW	30

tSU	Setup Time (Note 3)(Note 4)			20↓			ns
tSU	Setup Time (Note 4)(Note 5)			25↓			ns
tH	Hold Time (Note 3)(Note 4)			0↓			ns
tH	Hold Time (Note 4)(Note 5)			5↓			ns
TA	Free Air Operating Temperature			0		70	°C

Note 3: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Note 4: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.

Note 5: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

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