August 1986
Revised April 2000
DM74LS155 • DM74LS156
Dual 2-Line to 4-Line Decoders/Demultiplexers
General Description
These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input C1 is inverted at its outputs and data applied at C2 is true through its outputs. The inverter following the C1 data input permits use as a 3-to-8- line decoder, or 1-to-8-line demultiplexer, without external gating. Input clamping diodes are provided on these circuits to minimize transmission-line effects and simplify system design.
Features
■ Applications:
Dual 2-to-4-line decoder
Dual 1-to-4-line demultiplexer
3-to-8-line decoder
1-to-8-line demultiplexer
■Individual strobes simplify cascading for decoding or demultiplexing larger words
■Input clamping diodes simplify system design
■Choice of outputs:
Totem-pole (DM74LS155)
Open-collector (DM74LS156)
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74LS155M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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DM74LS155N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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DM74LS156M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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DM74LS156N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Decoders/Demultiplexers Line-4 to Line-2 Dual DM74LS156 • DM74LS155
© 2000 Fairchild Semiconductor Corporation |
DS006395 |
www.fairchildsemi.com |
DM74LS155 • DM74LS156
Function Tables
3-Line-to-8-Line Decoder or 1-Line-to-8-Line Demultiplexer
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Inputs |
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Outputs |
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Select |
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Strobe |
(0) |
(1) |
(2) |
(3) |
(4) |
(5) |
(6) |
(7) |
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Or Data |
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C (Note 1) |
B |
A |
G (Note 2) |
2Y0 |
2Y1 |
2Y2 |
2Y3 |
1Y0 |
1Y1 |
1Y2 |
1Y3 |
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X |
X X |
H |
H |
H |
H |
H |
H |
H |
H |
H |
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L |
L |
L |
L |
L |
H |
H |
H |
H |
H |
H |
H |
L |
L H |
L |
H |
L |
H |
H |
H |
H |
H |
H |
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L |
H L |
L |
H |
H |
L |
H |
H |
H |
H |
H |
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L |
H H |
L |
H |
H |
H |
L |
H |
H |
H |
H |
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H |
L |
L |
L |
H |
H |
H |
H |
L |
H |
H |
H |
H |
L H |
L |
H |
H |
H |
H |
H |
L |
H |
H |
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H |
H L |
L |
H |
H |
H |
H |
H |
H |
L |
H |
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H |
H H |
L |
H |
H |
H |
H |
H |
H |
H |
L |
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2-Line-to-4-Line Decoder or 1-Line-to-4-Line Demultiplexer
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Inputs |
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Outputs |
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Select |
Strobe |
Data |
1Y0 |
1Y1 |
1Y2 |
1Y3 |
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B |
A |
G1 |
C1 |
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X |
X |
H |
X |
H |
H |
H |
H |
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L |
L |
L |
H |
L |
H |
H |
H |
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L |
H |
L |
H |
H |
L |
H |
H |
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H |
L |
L |
H |
H |
H |
L |
H |
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H |
H |
L |
H |
H |
H |
H |
L |
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X |
X |
X |
L |
H |
H |
H |
H |
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H = HIGH level
L = LOW level
X = don’t care
Note 1: C = inputs C1 and C2 connected together
Note 2: G = inputs G1 and G2 connected together
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Inputs |
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Outputs |
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Select |
Strobe |
Data |
2Y0 |
2Y1 |
2Y2 |
2Y3 |
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B |
A |
G2 |
C2 |
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X |
X |
H |
X |
H |
H |
H |
H |
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L |
L |
L |
L |
L |
H |
H |
H |
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L |
H |
L |
L |
H |
L |
H |
H |
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H |
L |
L |
L |
H |
H |
L |
H |
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H |
H |
L |
L |
H |
H |
H |
L |
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X |
X |
X |
H |
H |
H |
H |
H |
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Logic Diagram
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2 |
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