August 1986
Revised March 2000
DM74LS153
Dual 1-of-4 Line Data Selectors/Multiplexers
General Description
Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR-invert gates. Separate strobe inputs are provided for each of the two four-line sections.
Features
■Permits multiplexing from N lines to 1 line
■Performs at parallel-to-serial conversion
■Strobe (enable) line provided for cascading (N lines to n lines)
■High fan-out, low impedance, totem pole outputs
■Typical average propagation delay times
From data |
14 ns |
From strobe |
19 ns |
From select |
22 ns |
■ Typical power dissipation 31 mW
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74LS153M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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DM74LS153N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Function Table |
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Select |
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Data Inputs |
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Strobe |
Output |
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Inputs |
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B |
A |
C0 |
C1 |
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C2 |
C3 |
G |
Y |
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X |
X |
X |
X |
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X |
X |
H |
L |
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L |
L |
L |
X |
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X |
X |
L |
L |
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L |
L |
H |
X |
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X |
X |
L |
H |
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L |
H |
X |
L |
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X |
X |
L |
L |
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L |
H |
X |
H |
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X |
X |
L |
H |
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H |
L |
X |
X |
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L |
X |
L |
L |
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H |
L |
X |
X |
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H |
X |
L |
H |
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H |
H |
X |
X |
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X |
L |
L |
L |
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H |
H |
X |
X |
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X |
H |
L |
H |
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Select inputs A and B are common to both sections. |
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H = HIGH Level
L = LOW Level
X = Don't Care
Selectors/Multiplexers Data Line 4-of-1 Dual DM74LS153
© 2000 Fairchild Semiconductor Corporation |
DS006393 |
www.fairchildsemi.com |
DM74LS153
Logic Diagram
www.fairchildsemi.com |
2 |
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