Fairchild Semiconductor DM74LS279N, DM74LS279MX, DM74LS279M Datasheet

August 1986

Revised March 2000

DM74LS279

Quad S-R Latch

General Description

The DM74LS279 consists of four individual and independent Set-Reset Latches with active low inputs. Two of the four latches have an additional S input ANDed with the primary S input. A LOW on any S input while the R input is HIGH will be stored in the latch and appear on the corresponding Q output as a HIGH. A LOW on the R input while the S input is HIGH will clear the Q output to a LOW. Simultaneous transition of the R and S inputs from LOW-to- HIGH will cause the Q output to be indeterminate. Both inputs are voltage level triggered and are not affected by transition time of the input data.

Ordering Code:

Order Number	Package Number	Package Description
DM74LS279M	M16A	16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS279N	N16E	16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram	Function Table
				Inputs			Output
			S (Note 1)		R		Q
				L	L		H (Note 2)
				L	H		H
				H	L		L
				H	H		Q0

H = HIGH Level

L = LOW Level

Q0 = The Level of Q before the indicated input conditions were established.

Note 1: For latches with double S inputs:

H = both S inputs HIGH

L = one or both S inputs LOW

Note 2: This output level is pseudo stable; that is, it may not persist when the S and R inputs return to their inactive (HIGH) level.

Latch R-S Quad DM74LS279

© 2000 Fairchild Semiconductor Corporation

DS006420

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DM74LS279

Absolute Maximum Ratings(Note 3)

	Supply Voltage	7V	Note 3: The “Absolute Maximum Ratings” are those values beyond which
			the safety of the device cannot be guaranteed. The device should not be
	Input Voltage	7V	operated at these limits. The parametric values defined in the Electrical
			Characteristics tables are not guaranteed at the absolute maximum ratings.
	Operating Free Air Temperature Range	0°C to +70°C
			The “Recommended Operating Conditions” table will define the conditions
	Storage Temperature Range	−65°C to +150°C	for actual device operation.

Recommended Operating Conditions

Symbol	Parameter	Min	Nom	Max	Units
VCC	Supply Voltage	4.75	5	5.25	V
VIH	HIGH Level Input Voltage	2			V
VIL	LOW Level Input Voltage			0.8	V
IOH	HIGH Level Output Current			−0.4	mA
IOL	LOW Level Output Current			8	mA
TA	Free Air Operating Temperature	0		70	°C

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

	Symbol	Parameter	Conditions	Min	Typ	Max	Units
					(Note 4)
	VI	Input Clamp Voltage	VCC = Min, II = −18 mA			−1.5	V
	VOH	HIGH Level	VCC = Min, IOH = Max	2.7	3.5		V
		Output Voltage	VIL = Max, VIH = Min
	VOL	LOW Level	VCC = Min, IOL = Max		0.35	0.5
		Output Voltage	VIL = Max, VIH = Min				V
			IOL = 4 mA, VCC = Min		0.25	0.4
	II	Input Current @ Max Input Voltage	VCC = Max, VI = 7V			0.1	mA
	IIH	HIGH Level Input Current	VCC = Max, VI = 2.7V			20	μA
	IIL	LOW Level Input Current	VCC = Max, VI = 0.4V			−0.4	mA
	IOS	Short Circuit Output Current	VCC = Max (Note 5)	−20		−100	mA
	ICC	Supply Current	VCC = Max (Note 6)		3.8	7	mA

Note 4: All typicals are at VCC = 5V, TA = 25°C.

Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 6: ICC is measured with all R inputs grounded, all S inputs at 4.5V and all outputs OPEN.

Switching Characteristics

at VCC = 5V and TA = 25°C
		From (Input)				RL = 2 kΩ
Symbol	Parameter	To (Output)			CL = 15 pF		CL = 50 pF		Units
					Min	Max	Min	Max
tPLH	Propagation Delay Time
			S to Q			22		25	ns
	LOW-to-HIGH Level Output
tPHL	Propagation Delay Time
			S to Q			15		23	ns
	HIGH-to-LOW Level Output
tPHL	Propagation Delay Time
		R to Q				27		33	ns
	HIGH-to-LOW Level Output

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