August 1986
Revised February 1999
DM74LS191
Synchronous 4-Bit Up/Down Counter with Mode Control
General Description
The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change simultaneously when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are triggered on a LOW-to-HIGH level transition of the clock input, if the enable input is LOW. A HIGH at the enable input inhibits counting. Level changes at either the enable input or the down/up input should be made only when the clock input is HIGH. The direction of the count is determined by the level of the down/up input. When LOW, the counter counts up and when HIGH, it counts down.
The counter is fully programmable; that is, the outputs may be preset to either level by placing a LOW on the load input and entering the desired data at the data inputs. The output will change independent of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.
The clock, down/up, and load inputs are buffered to lower the drive requirement; which significantly reduces the number of clock drivers, etc., required for long parallel words.
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.
Features
■Counts binary
■Single down/up count control line
■Count enable control input
■Ripple clock output for cascading
■Asynchronously presettable with load control
■Parallel outputs
■Cascadable for n-bit applications
■Average propagation delay 20 ns
■Typical clock frequency 25 MHz
■Typical power dissipation 100 mW
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74LS191M |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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|
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DM74LS191N |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Control Mode with Counter Up/Down Bit-4 Synchronous DM74LS191
© 1999 Fairchild Semiconductor Corporation |
DS006405.prf |
www.fairchildsemi.com |
DM74LS191
Connection Diagram
Timing Diagram
www.fairchildsemi.com |
2 |
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