Analog Devices OP497FS, OP497CY, OP497AY, OP497GP, OP497FP Datasheet

a	Precision Picoampere Input Current
	Quad Operational Amplifier

FEATURES

Low Offset Voltage: 50 V max

Low Offset Voltage Drift: 0.5 V/ C max

Very Low Bias Current 25 C: 100 pA max

–55 C to +125 C: 450 pA max

Very High Open-Loop Gain: 2000 V/mV min Low Supply Current (per Amplifier): 625 A max Operates from 2 V to 20 V Supplies

High Common-Mode Rejection: 120 dB min

APPLICATIONS

Strain Gage and Bridge Amplifiers

High Stability Thermocouple Amplifiers

Instrumentation Amplifiers

Photo-Current Monitors

High Gain Linearity Amplifiers

Long-Term Integrators/Filters

Sample-and-Hold Amplifiers

Peak Detectors

Logarithmic Amplifiers

Battery-Powered Systems

GENERAL DESCRIPTION

The OP497 is a quad op amp with precision performance in the space-saving, industry standard 16-lead SOlC package. Its combination of exceptional precision with low power and extremely low input bias current makes the quad OP497 useful in a wide variety of applications.

Precision performance of the OP497 includes very low offset, under 50 V, and low drift, below 0.5 V/°C. Open-loop gain exceeds 2000 V/mV ensuring high linearity in every application. Errors due to common-mode signals are eliminated by the OP497’s common-mode rejection of over 120 dB. The OP497’s power supply rejection of over 120 dB minimizes offset voltage changes experienced in battery-powered systems. Supply current of the OP497 is under 625 A per amplifier, and it can operate with supply voltages as low as ±2 V.

The OP497 utilizes a superbeta input stage with bias current cancellation to maintain picoamp bias currents at all temperatures. This is in contrast to FET input op amps whose bias currents start in the picoamp range at 25°C, but double for every 10°C rise in temperature, to reach the nanoamp range above 85°C. Input bias current of the OP497 is under 100 pA at 25°C and is under 450 pA over the military temperature range.

Combining precision, low power, and low bias current, the OP497 is ideal for a number of applications, including instrumentation amplifiers, log amplifiers, photo-diode preamplifiers, and long-term integrators. For a single device, see the OP97; for a dual device, see the OP297.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

OP497

PIN CONNECTIONS

16-Lead Wide Body SOIC

(S-Suffix)

OUT A	1					16	OUT D
–IN A	2	–	+	+	–	15	–IN D
+IN A	3					14	+IN D
V+	4		OP497			13	V–
+IN B	5					12	+IN C
–IN B	6	–	+	+	–	11	–IN C
OUT B	7					10	OUT C
NC	8					9	NC

NC = NO CONNECT

14-Lead Plastic Dip

(P-Suffix)

14-Lead Ceramic Dip

(Y-Suffix)

OUT A	1					14	OUT D
–IN A	2	–	+	+	–	13	–IN D
+IN A	3					12	+IN D
V+	4		OP497			11	V–
+IN B	5					10	+IN C
–IN B	6	–	+	+	–	9	–IN C
OUT B	7					8	OUT C

1000

							VS = 15V
– PA							VCM = 0V
CURRENT	100
INPUT					–IB
						+IB
						IOS
	10
	–75	–50	–25	0	25	50	75	100	125

TEMPERATURE – C

Input Bias, Offset Current vs. Temperature

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2002

OP497–SPECIFICATIONS (@ VS = 15 V, TA = 25 C, unless otherwise noted.)

						A			F			C/G
Parameter		Symbol	Condition		Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
INPUT CHARACTERISTICS														µV
Offset Voltage		Vos	–40°C ≤ +85°C			20	50		40	75		80	150
									70	150		120	250
Average Input Offset			–55°C ≤ +125°C			40	100		80	150		140	300
														µV/°C
Voltage Drift		TCVOS	TMIN – TMAX			0.2	0.5		0.4	1.0		0.6	1.5
Long-Term Input Offset														µV/Mo
Voltage Stability						0.1			0.1			0.1
Input Bias Current		IB	VCM = 0 V			30	100		40	150		60	200	pA
			–40° ≤ TA	≤ +85°C					60	200		80	300
Average Input Bias			–55° ≤ TA	≤ +125°C		80	450		110	600		130	600
			–40° ≤ TA	≤ +85°C
Current Drift		TCIB							0.3			0.3
			–55° ≤ TA	≤ +125°C		0.5			0.7			0.7		pA/°C
Input Offset Current		Ios	VCM = OV			15	100		30	150		50	200	pA
			–40° ≤ TA	≤ +85°C					50	200		80	300
Average Input Offset			–55° ≤ TA	≤ +125°C		35	400		60	600		90	600
														pA/°C
Current Drift		TCIOS				0.2			0.3			0.4
Input Voltage Range1		IVR	TMIN – TMAX		+ 13	+14		+13	tl4		+13	+14		V
					+13	+13.5		+13	+13.5		+13	+13.5
Common-Mode Rejection		CMR	VCM = ± 13 V		120	140		114	135		114	135		dB
			TMIN – TMAX		114	130		108	120		108	120
Large Signal Voltage Gain		AVO	VO = ± 10 V,
			RL = 2 kΩ		2000	6000		1500	4000		1200	4000		V/mV
			–40° ≤ TA	≤ +85°C				800	2000		800	2000
Input Resistance			–55° ≤ TA	≤ +125°C	1200	4000		1000	3000		800	3000
														MΩ
Differential Mode		RIN				30			30			30
Input Resistance														GΩ
Common Mode		RINCM				500			500			500
Input Capacitance		CIN				3			3			3		pF
OUTPUT CHARACTERISTICS			RL = 2 kΩ		± 13	± 13.7		± 13	± 13.7		± 13	± 13.7V
Output Voltage Swing		VO
			RL = 10 kΩ		± 13	± 14		± 13	± 14		± 13	± 14
			TMIN – TMAX
			RL = 10 kΩ		± 13	± 13.5		± 13	± 13.5		± 13	± 13.5
Short Circuit		ISC				± 25			± 25			± 25		mA
POWER SUPPLY			Vs = ± 2 V to ± 20 V
Power Supply		PSRR			120	140		114	135		114	135		dB
Rejection Ratio			Vs = ± 2.5 V to ± 20 V
Supply Current		ISY	TMIN – TMAX		114	130		108	120		108	120		µA
			No Load			525	625		525	625		525	625
(per Amplifier)			TMIN – TMAX			580	750		580	750	580	750
Supply Voltage Range		VS	Operating Range		± 2		± 20	± 2		± 20	± 2		± 20	V
			TMIN – TMAX		± 2.5		± 20	± 2.5		± 20	± 2.5		± 20
DYNAMIC PERFORMANCE														V/µS
Slew Rate		SR			0.05	0.15		0.05	0.15		0.05	0.15
Gain Bandwidth Product		GBW				500			500			500		kHz
Channel Separation		CS	VO = 20 Vp-p,
			fo = 10 Hz			150			150			150		dB
NOISE PERFORMANCE														µV/p-p
Voltage Noise		en p-p	0.1 Hz to 10 Hz			0.3			0.3			0.3
Voltage Noise Density		en = 10 Hz				17			17			17		nV/√Hz
		en = 1 kHz				15			15			15		nV/√Hz
Current Noise Density		in = 10 Hz				20			20			20		fA/√Hz

NOTE

1Guaranteed by CMR Test.

Specifications subject to change without notice.

–2–

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OP497

ABSOLUTE MAXIMUM RATINGS1							±20 V
Supply Voltage . . . . . . . . . .		. . . . . . .	. . .	. . .	. . . .
Input Voltage2 . . . . . . . . . . . . . . . .		. . . . . . . . . .	. . . . .	. . . .	. . . . .	.	. . . . . . . . 20 V
Differential Input Voltage2 . .		. . . . . . . . . .	. . . . .	. . . .	. . . . .	.	. . . . . . . 40 V
Output Short-Circuit Duration . . . . . . . .				. . .	. . .		. . Indefinite
Storage Temperature Range					–65°C to +175°C
Y Package . . . . . . . . . . . .		. . . . . .	. . . .	. .
P, S Package . . . . . . . . . . .		. . . . . .	. . . .	. .	–65°C to +150°C
Operating Temperature Range					–55°C to +125°C
OP497A, C (Y) . . . . . . . .		. . . . . .	. . . .	. .
OP497F, G (Y) . . . . . . . .		. . . . . .	. . . .	. . .	–40°C to +85°C
OP497F, G (P, S) . . . . . .		. . . . . .	. . . .	. . .	–40°C to +85°C
Junction Temperature					–65°C to +175°C
Y Package . . . . . . . . . . . .		. . . . . .	. . . .	. .
P, S Package . . . . . . . . . . .		. . . . . .	. . . .	. .	–65°C to +150°C
Lead Temperature Range (Soldering 60 sec) .					. . .		. . . . 300°C
Package Type		JA3		JC			Unit
14-Pin Cerdip (Y)		94		10			°C/W
14-Pin Plastic DIP (P)		76		33			°C/W
16-Pin SOIC (S)		92		23			°C/W

NOTES

1Absolute Maximum Ratings apply to both DICE and packaged parts, unless otherwise noted.

2For supply voltages less than ± 20 V, the absolute maximum input voltage is equal to the supply voltage.

3HIA is specified for worst-case mounting conditions, i.e., JA is specified for device in socket for cerdip, P-DIP packages; JA is specified for device soldered to printed circuit board for SOIC package.

	–
	1/4	V1	20V p–p @ 10Hz
	OP497
	+

2k

50k

50

–
1/4	V2
OP497

+

CHANNEL SEPARATION = 20 log ( V1 )

V2 /10000

Channel Separation Test Circuit

ORDERING GUIDE

	Temperature	Package	Package
Model	Range	Description	Option
OP497AY*	–55°C to +125°C	14-Lead Cerdip	Q-14
OP497CY*	–55°C to +125°C	14-Lead Cerdip	Q-14
OP497FP	–40°C to +85°C	14-Lead Plastic DIP	N-14
OP497FS	–40°C to +85°C	16-Lead SOIC	R-16
OP497GP	–40°C to +85°C	14-Lead Plastic DIP	N-14
OP497GS	–40°C to +85°C	16-Lead SOIC	R-16

*Not for new design; obsolete April 2002.

For a military processed devices, please refer to the Standard Microcircuit Drawing (SMD) available at www.dscc.dla.mil/ programs.milspec./default.asp.

SMD Part Number	ADI Part Number
5962–9452101M2A*	OP497BRC
5962–9452101MCA	OP497BY

*Not for new designs; obsolete April 2002.

DICE CHARACTERISTICS

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP497 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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–3–

OP497–Typical Performance Characteristics (25 C, Vs = 15 V, unless otherwise noted.)

	50
																		TA = 25 C
																		VS = 15V
	40																	VCM = 0V
UNITS	30
OF
PERCENTAGE	20
	10
	0
	–100 –80 –60 –40 –20													0		20 40 60 80 100
						INPUT OFFSET VOLTAGE – V
	TPC 1. Typical Distribution of
	Input Offset Voltage
	50
																			VS = 15V
																			VCM = 0V
UNITS	40
OF	30
PERCENTAGE	20
	10
	0
				0.1			0.2			0.3				0.4		0.5			0.6				0.7					0.8
	0
										TCVOS – V/ C
	TPC 4. Typical Distribution of
	TCVOS
	3
V																			TA =				25		C
																			VS =						15V
–
																			VCM =						0V
VALUE
	2
FROM FINAL	1
DEVIATION
	0
	0						1			2						3							4					5

TIME AFTER POWER APPLIED – Minutes

TPC 7. Input Offset Voltage

Warm-Up Drift

50

TA = 25 C

VS =

15V

40

VCM = 0V

UNITS

OF

30

PERCENTAGE

20

10

0

0

20

40 60

80

100

–100 –80 –60 –40 –20

INPUT BIAS CURRENT – pA

TPC 2. Typical Distribution of

Input Bias Current

1000

VS = 15V

– pA

VCM = 0V

CURRENT

100

INPUT

–IB

+IB

IOS

10

–75

–50 –25

0

25

50

75

100

125

TEMPERATURE – C

TPC 5. Input Bias, Offset

Current vs. Temperature

10000

BALANCED OR UNBALANCED

V

VS = 15V

–

VCM = 0V

VOLTAGEOFFSET

1000

EFFECTIVE

100

–55 C

TA

125 C

10

TA =

+25 C

10

100

1k

10k

100k

1M

10M

SOURCE RESISTANCE –

TPC 8. Effective Offset Voltage vs. Source Resistance

	60
											TA = 25 C
	50										VS =	15V
UNITS											VCM = 0V
	40
OF
PERCENTAGE	30
	20
	10
	0
	0		10		20		30		40			50		60

INPUT OFFSET CURRENT – pA

	TPC 3. Typical Distribution of
	Input Offset Current
	70
		TA = 25 C
	60	VS = 15V
pA											–IB
–	50
CURRENT
	40
BIAS											+IB
	30
INPUT
	20
	10
	0
					0		5		10		15
	–15 –10 –5

COMMON-MODE VOLTAGE – Volts

TPC 6. Input Bias Current vs. Common-Mode Voltage

C

100

BALANCED OR UNBALANCED

VS =

15V

V/

VCM

= 0V

–

VOLTAGEOFFSET

10

EFFECTIVE

1

0.1

100

1k

10k

100k

1M

10M

100M

SOURCE RESISTANCE –

TPC 9. Effective TCVOS vs.

Source Resistance

–4–

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