Analog Devices PKD01AY, PKD01EP, PKD01EY, PKD01FP, PKD01FY Datasheet

0 (0)

a

Monolithic Peak Detector

with Reset-and-Hold Mode

 

 

 

 

 

PKD01

 

 

 

FEATURES

Monolithic Design for Reliability and Low Cost High Slew Rate: 0.5 V/ s

Low Droop Rate

TA = 25 C: 0.1 mV/ms

TA = 125 C: 10 mV/ms

Low Zero-Scale Error: 4 mV

Digitally Selected Hold and Reset Modes Reset to Positive or Negative Voltage Levels Logic Signals TTL and CMOS Compatible Uncommitted Comparator On-Chip Available in Die Form

GENERAL DESCRIPTION

The PKD01 tracks an analog input signal until a maximum amplitude is reached. The maximum value is then retained as a peak voltage on a hold capacitor. Being a monolithic circuit, the PKD01 offers significant performance and package density advantages over hybrid modules and discrete designs without sacrificing system versatility. The matching characteristics attained in a monolithic circuit provide inherent advantages when charge injection and droop rate error reduction are primary goals.

Innovative design techniques maximize the advantages of monolithic technology. Transconductance (gm) amplifiers were chosen over conventional voltage amplifier circuit building blocks. The gm amplifiers simplify internal frequency compensation, minimize acquisition time and maximize circuit accuracy. Their outputs are easily switched by low glitch current steering circuits. The steered outputs are clamped to reduce charge injection errors upon entering the hold mode or exiting the reset mode. The inherently low zero-scale error is further reduced by active Zener-Zap trimming to optimize overall accuracy.

FUNCTIONAL BLOCK DIAGRAM

+IN –IN

OUTPUT V+

V–

 

 

 

 

 

 

 

 

 

CMP

 

 

 

 

 

 

+

 

 

 

LOGIC

 

 

 

 

V–

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

DET

 

 

 

 

BUFFER

 

 

 

 

GATED

 

 

–IN

 

"gm"

D1

C

OUTPUT

 

AMP

 

+

 

 

 

+

A

 

 

 

+IN

 

 

 

 

 

 

 

 

GATED

 

 

 

–IN

 

"gm"

 

 

 

 

AMP

 

 

 

 

 

+

B

 

 

 

+IN

 

 

 

PKD01

 

 

 

 

 

 

 

RST

 

 

 

 

 

 

RST

DET

OPERATIONAL MODE

 

CH

 

0

0

PEAK DETECT

 

 

0

1

PEAK HOLD

 

 

 

1

1

RESET

 

SWITCHES SHOWN FOR:

 

1

0

INDETERMINATE

 

RST = “0,” DET = “0”

 

The output buffer amplifier features an FET input stage to reduce droop rate error during lengthy peak hold periods. A bias current cancellation circuit minimizes droop error at high ambient temperatures.

Through the DET control pin, new peaks may either be detected or ignored. Detected peaks are presented as positive output levels. Positive or negative peaks may be detected without additional active circuits, since Amplifier A can operate as an inverting or noninverting gain stage.

An uncommitted comparator provides many application options. Status indication and logic shaping/shifting are typical examples.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2001

PKD01–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS (@ VS = 15 V, CH = 1000 pF, TA = 25 C, unless otherwise noted.)

 

 

 

PKD01A/E

PKD01F

 

 

Parameter

Symbol

Conditions

Min

Typ

Max

Min

Typ

Max

Unit

 

 

 

 

 

 

 

 

 

 

gm AMPLIFIERS A, B

 

 

 

 

 

 

 

 

 

Zero-Scale Error

VZS

 

 

2

4

 

3

7

mV

Input Offset Voltage

VOS

 

 

2

3

 

3

6

mV

Input Bias Current

IB

 

 

80

150

 

80

250

nA

Input Offset Current

IOS

RL = 10 kΩ, VO = ± 10 V

 

20

40

 

20

75

nA

Voltage Gain

AV

18

25

 

10

25

 

V/mV

Open-Loop Bandwidth

BW

AV = 1

 

0.4

 

 

0.4

 

MHz

Common-Mode Rejection Ratio

CMRR

–10 V ≤ VCM ≤ +10 V

80

90

 

74

90

 

dB

Power Supply Rejection Ratio

PSRR

± 9 V ≤ VS ≤ ±18 V

86

96

 

76

96

 

dB

Input Voltage Range1

VCM

 

± 10

± 11

 

± 10

± 11

 

V

Slew Rate

SR

∆VIN = 20 V, DET = 1, RST = 0

 

0.5

 

 

0.5

 

V/µs

Feedthrough Error1

 

66

80

 

66

80

 

dB

Acquisition Time to

 

 

 

 

 

 

 

 

µs

0.1% Accuracy1

tAQ

20 V Step, AVCL = +1

 

41

70

 

41

70

Acquisition Time to

tAQ

20 V Step, AVCL = +1

 

45

 

 

45

 

µs

0.01% Accuracy1

 

 

 

 

 

 

 

 

 

COMPARATOR

 

 

 

 

 

 

 

 

 

Input Offset Voltage

VOS

 

 

0.5

1.5

 

1

3

mV

Input Bias Current

IB

 

 

700

1000

 

700

1000

nA

Input Offset Current

IOS

2 kΩ Pull-Up Resistor to 5 V

 

75

300

 

75

300

nA

Voltage Gain

AV

5

7.5

 

3.5

7.5

 

V/mV

Common-Mode Rejection Ratio

CMRR

–10 V ≤ VCM ≤ +10 V

82

106

 

82

106

 

dB

Power Supply Rejection Ratio

PSRR

± 9 V ≤ VS ≤ ±18 V

76

90

 

76

90

 

dB

Input Voltage Range1

VCM

ISINK ≤ 5 mA, Logic GND = 0 V

± 11.5

± 12.5

 

± 11.5

± 12.5

 

V

Low Output Voltage

VOL

–0.2

+0.15 +0.4

–0.2

+0.15

+0.4

V

“OFF” Output Leakage Current

IL

VOUT = 5 V

 

25

80

 

25

80

µA

Output Short-Circuit Current

ISC

VOUT = 5 V

7

12

45

7

12

45

mA

Response Time2

tS

5 mV Overdrive, 2 kΩ Pull-Up

 

150

 

 

150

 

ns

 

 

Resistor to 5 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIGITAL INPUTS – RST, DET2

 

 

 

 

 

 

 

 

 

Logic “1” Input Voltage

VH

 

2

 

 

2

 

 

V

Logic “0” Input Voltage

VL

 

 

 

0.8

 

 

0.8

V

Logic “1” Input Current

IINH

VH = 3.5 V

 

0.02

1

 

0.02

1

µA

Logic “0” Input Current

IINL

VL = 0.4 V

 

1.6

10

 

1.6

10

µA

MISCELLANEOUS

 

TJ = 25°C

 

 

 

 

 

 

 

Droop Rate3

VDR

 

0.01

0.07

 

0.01

0.1

mV/ms

Output Voltage Swing:

VOP

TA = 25°C

 

0.02

0.15

 

0.03

0.20

mV/ms

DET = 1

 

 

 

 

 

 

 

Amplifier C

 

RL = 2.5 kΩ

± 11.5

± 12.5

 

± 11

± 12

 

V

Short-Circuit Current:

 

 

 

 

 

 

 

 

 

Amplifier C

ISC

 

7

15

40

7

15

40

mA

Switch Aperture Time

tAP

 

 

75

 

 

75

 

ns

Switch Switching Time

ts

 

 

50

 

 

50

 

ns

Slew Rate: Amplifier C

SR

RL = 2.5 kΩ

 

2.5

 

 

2.5

 

V/µs

Power Supply Current

ISY

No Load

 

5

7

 

6

9

mA

NOTES

1Guaranteed by design.

2DET = 1, RST = 0.

3Due to limited production test times, the droop current corresponds to junction temperature (TJ). The droop current vs. time (after power-on) curve clarified this point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (TA) also. The warmed-up (TA) droop current specification is correlated to the junction temperature (TJ) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (TA) temperature specifications are not subject to production testing.

Specifications subject to change without notice.

–2–

REV. A

 

 

 

 

 

 

 

 

 

PKD01

 

 

(@ VS = 15 V, CH = 1000 pF, –55 C TA +125 C for PKD01AY, –25 C TA +85 C for

ELECTRICAL CHARACTERISTICS PKD01EY, PKD01FY and 0 C TA +70 C for PKD01EP, PKD01FP, unless otherwise noted.)

 

 

 

PKD01A/E

PKD01F

 

 

 

Parameter

Symbol

Conditions

Min

Typ

Max

Min

Typ

Max

 

Unit

 

 

 

 

 

 

 

 

 

 

 

“gm” AMPLIFIERS A, B

 

 

 

 

 

 

 

 

 

 

Zero-Scale Error

VZS

 

 

4

7

 

6

12

 

mV

Input Offset Voltage

VOS

 

 

3

6

 

5

10

 

mV

Average Input Offset Drift1

TCVOS

 

 

–9

–24

 

–9

–24

 

µV/°C

Input Bias Current

IB

 

 

160

250

 

160

500

 

nA

Input Offset Current

IOS

RL = 10 kΩ, VO = ± 10 V

 

30

100

 

30

150

 

nA

Voltage Gain

AV

7.5

9

 

5

9

 

 

V/mV

Common-Mode Rejection Ratio

CMRR

–10 V ≤ VCM ≤ +10 V

74

82

 

72

80

 

 

dB

Power Supply Rejection Ratio

PSRR

± 9 V ≤ VS ≤ ± 18 V

80

90

 

70

90

 

 

dB

Input Voltage Range1

VCM

 

± 10

± 11

 

± 10

± 11

 

 

V

Slew Rate

SR

 

 

0.4

 

 

0.4

 

 

V/µs

Acquisition Time to 0.1% Accuracy1

tAQ

20 V Step, AVCL = +1

 

60

 

 

60

 

 

µs

COMPARATOR

 

 

 

 

 

 

 

 

 

 

Input Offset Voltage

VOS

 

 

2

2.5

 

2

5

 

mV

Average Input Offset Drift1

TCVOS

 

 

–4

–6

 

–4

–6

 

µV/°C

Input Bias Current

IB

 

 

1000

2000

 

1100

2000

 

nA

Input Offset Current

IOS

2 kΩ Pull-Up Resistor to 5 V

 

100

600

 

100

600

 

nA

Voltage Gain

AV

4

6.5

 

2.5

6.5

 

 

V/mV

Common-Mode Rejection Ratio

CMRR

–10 V ≤ VCM ≤ +10 V

80

100

 

80

92

 

 

dB

Power Supply Rejection Ratio

PSRR

± 9 V ≤ VS ≤ ± 18 V

72

82

 

72

86

 

 

dB

Input Voltage Range1

VCM

ISINK ≤ 5 mA, Logic GND = 0 V

± 11

 

 

± 11

 

 

 

V

Low Output Voltage

VOL

–0.2

+0.15

+0.4

–0.2

+0.15

+0.4

 

V

OFF Output Leakage Current

IL

VOUT = 5 V

 

25

100

 

100

180

 

µA

Output Short-Circuit Current

ISC

VOUT = 5 V

6

10

45

6

10

45

 

mA

Response Time

tS

5 mV Overdrive, 2 kΩ Pull-Up

 

 

 

 

 

 

 

 

 

 

Resistor to 5 V

 

200

 

 

200

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

DIGITAL INPUTS – RST, DET2

 

 

 

 

 

 

 

 

 

 

Logic “1” Input Voltage

VH

 

2

 

 

2

 

 

 

V

Logic “0” Input Voltage

VL

 

 

 

0.8

 

 

0.8

 

V

Logic “1” Input Current

IINH

VH = 3.5 V

 

0.02

1

 

0.02

1

 

µA

Logic “0” Input Current

IINL

VL = 0.4 V

 

2.5

15

 

2.5

15

 

µA

MISCELLANEOUS

 

 

 

 

 

 

 

 

 

 

Droop Rate3

VDR

TJ = Max Operating Temp.

 

1.2

10

 

3

15

 

mV/ms

 

 

TA = Max Operating Temp.

 

 

 

 

 

 

 

 

 

 

DET = 1

 

2.4

20

 

6

20

 

mV/ms

Output Voltage Swing

 

RL = 2.5 kΩ

± 11

± 12

 

± 10.5

± 12

 

 

 

Amplifier C

VOP

 

 

 

V

Short-Circuit Current

 

 

 

 

 

 

 

 

 

 

Amplifier C

ISC

 

6

12

40

6

12

40

 

mA

Switch Aperture Time

tAP

 

 

75

 

 

75

 

 

ns

Slew Rate: Amplifier C

SR

RL = 2.5 kΩ

 

2

 

 

2

 

 

V/µs

Power Supply Current

ISY

No Load

 

5.5

8

 

6.5

10

 

mA

NOTES

1Guaranteed by design.

2DET = 1, RST = 0.

3Due to limited production test times, the droop current corresponds to junction temperature (T J ). The droop current vs. time (after power-on) curve clarifies this point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T A ) also. The warmed-up (TA ) droop current specification is correlated to the junction temperature (TJ) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (TA ) temperature specifications are not subject to production testing.

Specifications subject to change without notice.

REV. A

–3–

PKD01

ABSOLUTE MAXIMUM RATINGS1, 2

±18 V

Supply Voltage . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . .

Input Voltage . . . . . . . . . . . . . . . . . . .

Equal to Supply Voltage

Logic and Logic Ground

 

 

Voltage . . . . . . . . . . . . . . . . . . . . . .

Equal to Supply Voltage

Output Short-Circuit Duration . . . . . .

. . . . . . . . . .

Indefinite

Amplifier A or B Differential Input Voltage . . . . . . . .

. . ±24 V

Comparator Differential Input Voltage

. . . . . . . . . . .

. . ±24 V

Comparator Output Voltage

 

 

. . . . . . . . . . . . . . . . . . . . . . Equal to Positive Supply Voltage

Hold Capacitor Short-Circuit Duration

. . . . . . . . . .

Indefinite

Lead Temperature (Soldering, 60 sec)

. . . . . . . . . . .

. . 300°C

Storage Temperature Range

. . . . . –65°C to +150°C

PKD01AY, PKD01EY, PKD01FY

PKD01EP, PKD01FP . . . . . . . . . .

. . . . . –65°C to +125°C

Operating Temperature Range

–55°C to +125°C

PKD01AY . . . . . . . . . . . . . . . . . . .

PKD01EY, PKD01FY . . . . . . . . . .

. . . . . . –25°C to +85°C

PKD01EP, PKD01FP . . . . . . . . . .

. . . . . . . . . 0°C to 70°C

Junction Temperature . . . . . . . . . . . .

. . . . . –65°C to +150°C

NOTES

1Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted.

2Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

Package Type

JA*

JC

Unit

14-Lead Hermetic DIP (Y)

99

12

°C/W

14-Lead Plastic DIP (P)

76

33

°C/W

JA is specified for worst-case mounting conditions, i.e., θJA is specified for device in socket for cerdip and PDIP packages.

ORDERING GUIDE1

Model2

Temperature

Package

Package

Range

Description

Option

PKD01AY

–55°C to +85°C

Cerdip

Q-14

PKD01EY

–25°C to +85°C

Cerdip

Q-14

PKD01FY

–25°C to +85°C

Cerdip

Q-14

PKD01EP

0°C to 70°C

Plastic DIP

N-14

PKD01FP

0°C to 70°C

Plastic DIP

N-14

 

 

 

 

NOTES

1Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages.

2For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet.

PIN CONFIGURATION

RST

 

 

 

DET

 

 

 

V+

 

 

 

LOGIC GND

 

 

 

OUTPUT

 

PKD01

 

COMP OUT

 

 

CH

 

 

–IN C

 

 

 

–IN A

 

 

 

+IN C

 

 

 

+IN A

 

 

 

–IN B

 

 

 

V–

 

 

 

+IN B

 

 

 

 

 

 

 

 

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the PKD01 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

DICE CHARACTERISTICS

–4–

REV. A

 

 

 

 

PKD01

 

 

 

 

 

WAFER TEST LIMITS (@ VS = 15 V, CH = 1000 pF, TA = 25 C, unless otherwise noted.)

 

 

 

 

 

 

 

 

 

 

PKD01N

 

Parameter

Symbol

Conditions

Limit

Unit

 

 

 

 

 

“gm” AMPLIFIERS A, B

 

 

7

mV max

Zero-Scale Error

VZS

 

Input Offset Voltage

VOS

 

6

mV max

Input Bias Current

IB

 

250

nA max

Input Offset Current

IOS

RL = 10 kΩ, VO = ±10 V

75

nA max

Voltage Gain

AV

10

V/mV min

Common-Mode Rejection Ratio

CMRR

–10 V ≤ VCM ≤ +10 V

74

dB min

Power Supply Rejection Ratio

PSRR

± 9 V ≤ VS ≤ ±18 V

76

dB min

Input Voltage Range1

VCM

∆VIN = 20 V, DET = 1, RST = 0

± 11.5

V min

Feedthrough Error

 

66

dB min

 

 

 

 

 

COMPARATOR

 

 

 

 

Input Offset Voltage

VOS

 

3

mV max

Input Bias Current

IB

 

1000

nA max

Input Offset Current

IOS

2 kΩ Pull-Up Resistor to 5 V

300

nA max

Voltage Gain1

AV

3.5

V/mV min

Common-Mode Rejection Ratio

CMRR

–10 V ≤ VCM ≤ +10 V

82

dB min

Power Supply Rejection Ratio

PSRR

± 9 V ≤ VS ≤ ±18 V

76

dB min

Input Voltage Range1

VCM

ISINK ≤ 5 mA, Logic GND = 5 V

± 11.5

V min

Low Output Voltage

VOL

0.4

V max

 

 

 

–0.2

V min

“OFF” Output Leakage Current

IL

VOUT = 5 V

80

µA max

Output Short-Circuit Current

ISC

VOUT = 5 V

45

mA min

 

 

 

7

mA min

 

 

 

 

 

DIGITAL INPUTS–RST, DET2

 

 

 

 

Logic “1” Input Voltage

VH

 

2

V min

Logic “0” Input Voltage

VL

 

0.8

V max

Logic “1” Input Current

IINH

VH = 3.5 V

1

µA max

Logic “0” Input Current

IINL

VL = 0.4 V

10

µA max

MISCELLANEOUS

 

TJ = 25°C,

 

 

Droop Rate3

VDR

0.1

mV/ms max

 

 

TA = 25°C

0.20

mV/ms max

Output Voltage Swing Amplifier C

VOP

RL = 2.5 kΩ

± 11

V min

Short-Circuit Current Amplifier C

ISC

 

40

mA max

 

 

 

7

mA min

Power Supply Current

ISY

No Load

9

mA max

gm AMPLIFIERS A, B

 

 

 

V/µs

Slew Rate

SR

 

0.5

Acquisition Time1

tA

0.1% Accuracy, 20 V Step, AVCL = 1

41

µs

 

tA

0.01% Accuracy, 20 V Step, AVCL = 1

45

µs

COMPARATOR

 

5 mV Overdrive, 2 kΩ Pull-Up Resistor to 5 V

 

 

Response Time

 

150

ns

 

 

 

 

 

MISCELLANEOUS

 

 

 

 

Switch Aperture Time

tAP

 

75

ns

Switching Time

tS

 

50

ns

Buffer Slew Rate

SR

RL = 2.5 kΩ

2.5

V/µs

NOTES

1Guaranteed by design.

2DET = 1, RST = 0.

3Due to limited production test times, the droop current corresponds to junction temperature (T J). The droop current vs. time (after power-on) curve clarifies this point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T A) also. The warmed-up (TA) droop current specification is correlated to the junction temperature (TJ) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature.

Ambient (TA) temperature specifications are not subject to production testing.

REV. A

–5–

Analog Devices PKD01AY, PKD01EP, PKD01EY, PKD01FP, PKD01FY Datasheet

PKD01–Typical Performance Characteristics

 

18

 

 

 

 

 

V

14

 

 

 

 

 

 

 

 

 

 

 

AMPLIFIER

10

 

 

INPUT + RANGE = V+

6

 

 

–55 C

TA +125 C

 

 

 

 

 

 

2

 

–55 C

 

 

 

OF

 

 

 

 

–2

 

 

+25 C

 

 

RANGE

 

 

 

 

–6

 

 

 

+125 C

 

 

 

 

 

 

 

INPUT

–10

V– SUPPLY

 

 

 

–14

 

 

 

 

 

 

 

 

 

 

 

 

–18

 

9

12

15

 

 

4

6

18

 

 

SUPPLY VOLTAGE +V AND –V –V

 

 

6

 

 

 

 

 

4

 

 

 

 

– mV

2

 

 

 

 

VOLTAGE

 

 

 

 

0

 

 

 

 

 

 

 

 

 

OFFSET

–2

 

 

 

 

 

 

 

 

 

 

–4

 

 

 

 

 

–6

 

 

 

 

 

–75

–50

–25 0 25 50 75

100

125

 

 

 

TEMPERATURE – C

 

 

TPC 1. A and B Input Range vs.

TPC 2. A and B Amplifiers Offset

Supply Voltage

Voltage vs. Temperature

1000

 

 

 

100

Hz

 

 

 

 

 

– nV/

100

 

 

V

10

NOISE VOLTAGE

 

RS = 10k

RMS NOISE –

 

 

 

 

 

RS = 0

 

10

 

 

1

 

 

 

 

INPUT

 

 

 

 

 

 

0

10

100

1k

0

 

1

 

VS =

15V

 

 

 

TA = 25 C

 

 

 

AV = +1

 

 

 

0.1

1

10

100

1000

FREQUENCY – Hz

BANDWIDTH – kHz

TPC 4. Input Spot Noise vs.

TPC 5. Wideband Noise vs.

Frequency

 

 

 

 

Bandwidth

 

 

 

 

1.0

 

 

CH = 1000pF

 

 

18

RL = 10k

 

 

 

 

POLARITY OF

 

 

 

 

 

 

 

 

ERROR MAY BE

 

TA = 25 C

 

 

14

 

 

 

 

 

POSITIVE OR

 

 

 

 

 

V+ SUPPLY

 

 

 

NEGATIVE

 

 

 

 

10

 

+125 C

 

0.5

 

 

 

 

– V

 

 

 

 

–ERRORmV

 

 

 

 

6

 

 

+25 C

 

 

 

 

 

 

SWINGOUTPUT

 

 

 

 

 

 

 

 

2

 

 

–55 C

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–2

 

 

–55 C

 

 

 

 

 

+125 C

 

 

–6

 

 

+25 C

 

 

 

 

 

 

 

 

 

 

 

 

 

–0.5

 

 

+25 C

 

 

–10

V– SUPPLY

 

+125 C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–55 C

 

 

–14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–1.0

 

 

 

 

 

–18

 

9

12

15

 

–10

–5

0

5

10

 

4

6

18

 

 

VIN – V

 

 

 

SUPPLY VOLTAGE +V AND –V – V

 

TPC 7. Amplifier A Charge Injec-

TPC 8. Output Voltage Swing vs.

tion Error vs. Input Voltage and

Supply Voltage (Dual Supply

Temperature

Operation)

 

40

 

 

 

 

 

 

 

 

 

35

 

 

 

 

 

 

 

 

 

30

 

 

 

 

 

 

 

 

– nA

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OS

20

 

 

 

 

 

 

 

 

A,B I

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

0

–25

0

25

50

75

100

125

 

 

–75 –50

150

 

 

 

TEMPERATURE – C

 

 

 

TPC 3. A, B IOS vs. Temperature

 

1.0

 

 

 

 

 

 

 

 

+125 C

 

 

0.5

 

 

+25 C

 

 

 

 

–55 C

 

 

 

 

 

 

– mV

 

 

 

 

 

ERROR

0

 

 

 

 

 

 

 

 

 

 

–0.5

 

 

 

 

 

–1.0

 

 

 

 

 

–10

–5

0

5

10

 

 

 

VIN – V

 

 

TPC 6. Amplifier B Charge Injection Error vs. Input Voltage and Temperature

 

15

+25 C

 

 

12.5

 

 

– Volts

10.0

–55 C

 

7.5

 

 

 

5.0

+125 C

 

SWING

2.5

 

 

 

0

 

 

–2.5

 

 

OUTPUT

 

 

–5.0

–55 C

 

–7.5

 

+25 C

 

–10.0

 

 

 

 

 

 

 

–12.5

 

 

 

–15

+125 C

 

 

 

 

 

1.0

0.1

10.0

 

 

LOAD RESISTOR TO GROUND – k

 

TPC 9. Output Voltage vs. Load Resistance

–6–

REV. A

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