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INTEGRATED CIRCUITS
DATA SHEET
TDA8358J
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
Product specification |
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1999 Dec 22 |
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File under Integrated Circuits, IC02 |
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Philips Semiconductors |
Product specification |
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Full bridge vertical deflection output circuit
TDA8358J
in LVDMOS with east-west amplifier
FEATURES
∙Few external components required
∙High efficiency fully DC coupled vertical bridge output circuit
∙Vertical flyback switch with short rise and fall times
∙Built-in guard circuit
∙Thermal protection circuit
∙Improved EMC performance due to differential inputs
∙East-west output stage.
QUICK REFERENCE DATA
GENERAL DESCRIPTION
The TDA8358J is a power circuit for use in 90° and 110° colour deflection systems for 25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC contains a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge output circuit allows DC coupling of the deflection coil in combination with single positive supply voltages.
The east-west output stage is able to supply the sink current for a diode modulator circuit.
The IC is constructed in a Low Voltage DMOS (LVDMOS) process that combines bipolar, CMOS and DMOS devices. DMOS transistors are used in the output stage because of absence of second breakdown.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Supplies |
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VP |
supply voltage |
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7.5 |
12 |
18 |
V |
VFB |
flyback supply voltage |
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2VP |
45 |
66 |
V |
Iq(P)(av) |
average quiescent supply current |
during scan |
− |
10 |
15 |
mA |
Iq(FB)(av) |
average quiescent flyback supply current |
during scan |
− |
− |
10 |
mA |
PEW |
east-west power dissipation |
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− |
− |
4 |
W |
Ptot |
total power dissipation |
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− |
− |
15 |
W |
Inputs and outputs |
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Vi(dif)(p-p) |
differential input voltage (peak-to-peak value) |
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− |
1000 |
1500 |
mV |
Io(p-p) |
output current (peak-to-peak value) |
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− |
− |
3.2 |
A |
Flyback switch |
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Io(peak) |
maximum (peak) output current |
t ≤ 1.5 ms |
− |
− |
±1.8 |
A |
East-west amplifier |
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Vo |
output voltage |
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− |
− |
68 |
V |
VI(bias) |
input bias voltage |
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2 |
− |
3.2 |
V |
Io |
output current |
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− |
− |
750 |
mA |
Thermal data; in accordance with IEC 747-1 |
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Tstg |
storage temperature |
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−55 |
− |
+150 |
°C |
Tamb |
ambient temperature |
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−25 |
− |
+75 |
°C |
Tj |
junction temperature |
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− |
− |
150 |
°C |
1999 Dec 22 |
2 |
Philips Semiconductors |
Product specification |
|
|
Full bridge vertical deflection output circuit
TDA8358J
in LVDMOS with east-west amplifier
ORDERING INFORMATION
TYPE |
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PACKAGE |
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NUMBER |
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NAME |
DESCRIPTION |
VERSION |
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TDA8358J |
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DBS13P |
plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) |
SOT141-6 |
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BLOCK DIAGRAM |
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Vi(p-p)
VI(bias) |
0 |
Vi(p-p) |
VI(bias) |
0 |
Ii(p-p)
II(av)
0
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COMP |
GUARD |
VP |
VFB |
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13 |
11 |
3 |
9 |
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COMP. |
GUARD |
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CIRCUIT |
CIRCUIT |
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M5 |
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D2 |
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D3 |
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M2 |
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D1 |
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10 |
OUTA |
INA |
1 |
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M4 |
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INPUT |
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12 |
FEEDB |
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AND |
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FEEDBACK |
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CIRCUIT |
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INB |
2 |
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M1 |
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4 |
OUTB |
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M3 |
TDA8358J |
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INEW |
5 |
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M6 |
8 |
OUTEW |
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6 |
7 |
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MGL866 |
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VGND |
EWGND |
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Fig.1 Block diagram.
1999 Dec 22 |
3 |
Philips Semiconductors |
Product specification |
|
|
Full bridge vertical deflection output circuit
TDA8358J
in LVDMOS with east-west amplifier
PINNING
SYMBOL |
PIN |
DESCRIPTION |
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INA |
1 |
input A |
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INB |
2 |
input B |
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VP |
3 |
supply voltage |
OUTB |
4 |
output B |
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INEW |
5 |
east-west input |
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VGND |
6 |
vertical ground |
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EWGND |
7 |
east-west ground |
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OUTEW |
8 |
east-west output |
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VFB |
9 |
flyback supply voltage |
OUTA |
10 |
output A |
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GUARD |
11 |
guard output |
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FEEDB |
12 |
feedback input |
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COMP |
13 |
compensation input |
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handbook, halfpage
INA 1
INB 2
VP 3
OUTB 4
INEW 5
VGND 6
TDA8358J
EWGND 7
OUTEW 8
VFB 9
OUTA 10
GUARD 11
FEEDB 12
COMP 13
MGL867
The die has been glued to the metal block of the package. If the metal block is not insulated from the heatsink, the heatsink shall only be connected directly to pin VGND.
FUNCTIONAL DESCRIPTION
Vertical output stage
The vertical driver circuit has a bridge configuration. The deflection coil is connected between the complimentary driven output amplifiers. The differential
input circuit is voltage driven. The input circuit is specially designed for direct connection to driver circuits delivering a differential signal but it is also suitable for single-ended applications. The output currents of the driver device are converted to voltages by the conversion resistors
RCV1 and RCV2 (see Fig.3) connected to pins INA
and INB. The differential input voltage is compared with the voltage across the measuring resistor RM, providing internal feedback information. The voltage across RM is proportional with the output current. The relationship between the differential input current and the output current is defined by:
2 × Ii(dif)(p-p) × RCV = Io(p-p) × RM
The output current should measure 0.5 to 3.2 A (p-p) and is determined by the value of RM and RCV. The allowable input voltage range is 100 mV to 1.6 V for each input. The formula given does not include internal bondwire resistances. Depending on the value of RM and the internal bondwire resistance (typical value 50 mΩ) the actual value of the current in the deflection coil will be about 5% lower than calculated.
Flyback supply
The flyback voltage is determined by the flyback supply voltage VFB. The principle of two supply voltages (class G) allows to use an optimum supply voltage VP for scan and an optimum flyback supply voltage VFB for flyback, thus very high efficiency is achieved. The available flyback output voltage across the coil is almost equal to VFB, due to the absence of a coupling capacitor which is not required in a bridge configuration. The very short
rise and fall times of the flyback switch are determined mainly by the slew-rate value of more than 300 V/μs.
Protection
The output circuit contains protection circuits for:
∙Too high die temperature
∙Overvoltage of output A.
Fig.2 Pin configuration.
1999 Dec 22 |
4 |
Philips Semiconductors |
Product specification |
|
|
Full bridge vertical deflection output circuit
TDA8358J
in LVDMOS with east-west amplifier
Guard circuit
A guard circuit with output pin GUARD is provided.
The guard circuit generates a HIGH-level during the flyback period. The guard circuit is also activated for one of the following conditions:
∙During thermal protection (Tj ≈ 170 °C)
∙During an open-loop condition.
The guard signal can be used for blanking the picture tube and signalling fault conditions. The vertical synchronization pulses of the guard signal can be used by an On Screen Display (OSD) microcontroller.
Damping resistor compensation
HF loop stability is achieved by connecting a damping resistor RD1 (see Fig.4) across the deflection coil. The current values in RD1 during scan and flyback are significantly different. Both the resistor current and the deflection coil current flow into measuring resistor RM,
resulting in a too low deflection coil current at the start of the scan.
The difference in the damping resistor current values during scan and flyback have to be externally compensated in order to achieve a short settling time.
For that purpose a compensation resistor RCMP is connected between pins OUTA and COMP. The value of RCMP is calculated by:
(VFB –Vloss(FB) –VP) × RD1 × (RS + 300)
R = -------------------------------------------------------------------------------------------------------------
CMP (VFB –Vloss(FB) –Icoil(peak) × Rcoil) × RM
where:
∙Rcoil is the coil resistance
∙Vloss(FB) is the voltage loss between pins VFB and OUTA at flyback.
East-west amplifier
The east-west amplifier is a current driver sinking the current of a diode modulator circuit. A feedback resistor REWF (see Fig.4) has to be connected between
the input and output of the inverting east-west amplifier in order to convert the east-west correction input current into an output voltage. The output voltage of the east-west circuit at pin OUTEW is given by:
Vo ≈ Ii × REWF + Vi
The maximum output voltage is Vo(max) = 68 V, while the maximum output current of the circuit is Io(max) = 750 mA.
1999 Dec 22 |
5 |
Philips Semiconductors |
Product specification |
|
|
Full bridge vertical deflection output circuit
TDA8358J
in LVDMOS with east-west amplifier
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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VP |
supply voltage |
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− |
18 |
V |
VFB |
flyback supply voltage |
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− |
68 |
V |
VVGND-EWGND |
voltage difference between |
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− |
0.3 |
V |
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pins VGND and EWGND |
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Vn |
DC voltage |
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pins OUTA and OUTEW |
note 1 |
− |
68 |
V |
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pin OUTB |
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− |
VP |
V |
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pins INA, INB, INEW, GUARD, |
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−0.5 |
VP |
V |
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FEEDB, and COMP |
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In |
DC current |
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pins OUTA and OUTB |
during scan (p-p) |
− |
3.2 |
A |
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pins OUTA and OUTB |
at flyback (peak); t ≤ 1.5 ms |
− |
±1.8 |
A |
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pins INA, INB, INEW, GUARD, |
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−20 |
+20 |
mA |
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FEEDB, and COMP |
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pin OUTEW |
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− |
750 |
mA |
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Ilu |
latch-up current |
input current into any pin; |
− |
+200 |
mA |
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pin voltage is 1.5 × VP; Tj = 150 °C |
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input current out of any pin; |
−200 |
− |
mA |
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pin voltage is −1.5 × VP; Tj = 150 °C |
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Ves |
electrostatic handling voltage |
machine model; note 2 |
−300 |
+300 |
V |
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human body model; note 3 |
−2000 |
+2000 |
V |
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PEW |
east-west power dissipation |
note 4 |
− |
4 |
W |
Ptot |
total power dissipation |
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− |
15 |
W |
Tstg |
storage temperature |
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−55 |
+150 |
°C |
Tamb |
ambient temperature |
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−25 |
+75 |
°C |
Tj |
junction temperature |
note 5 |
− |
150 |
°C |
Notes
1.When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.
2.Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.
3.Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.
4.For repetitive time durations of t < 0.1 ms or a non repetitive time duration of t < 5 ms the maximum (peak) east-west power dissipation PEW(peak) = 15 W.
5.Internally limited by thermal protection at Tj ≈ 170 °C.
THERMAL CHARACTERISTICS
In accordance with IEC 747-1.
SYMBOL |
PARAMETER |
CONDITIONS |
VALUE |
UNIT |
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Rth(j-c) |
thermal resistance from junction to case |
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4 |
K/W |
Rth(j-a) |
thermal resistance from junction to ambient |
in free air |
40 |
K/W |
1999 Dec 22 |
6 |
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