Philips TDA8001T-C1, TDA8001AT-C1, TDA8001A-C1, TDA8001-C1 Datasheet

INTEGRATED CIRCUITS

TDA8001

Smart card interface

Product specification

1996 Dec 12

Supersedes data of 1995 Feb 01

File under Integrated Circuits, IC02

Philips Semiconductors	Product specification
Smart card interface	TDA8001

FEATURES

∙Protected I/O line

∙VCC regulation (5 V ±5%, 100 mA max. with controlled rise and fall times)

∙VPP generation (12.5, 15 or 21 V ±2.5%, 50 mA max., with controlled rise and fall times) (only at TDA8001 and TDA8001T)

∙Clock generation (up to 10 MHz), with synchronous frequency doubling

∙Overload, thermal and card extraction protections

∙Current limitation in case of short-circuit

∙Idle mode and special circuitry for spikes killing during powering on and off

∙Two voltage supervisors (digital and analog supplies)

∙Automatic activation and deactivation sequences through an independent internal clock

∙Enhanced ESD protections on card side (4 kV min.)

∙Easy chaining for multiple card readers

∙ISO 7816 compatibility.

ORDERING INFORMATION

APPLICATIONS

∙Pay TV (multistandards conditional access system, videoguard, newscript)

∙Multi-application smart card readers (banking, vending machine, electronic payment identification).

GENERAL DESCRIPTION

The TDA8001 is a complete, low-cost analog interface which can be positioned between an asynchronous smart card (ISO 7816) and a microcontroller. It is directly compatible with the new Datacom chip verifier.

The complete supply, protection and control functions are realized with only a few external components, making this product very attractive for consumer applications

(see Chapter “Application information”).

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
TDA8001;	DIP28	plastic dual in-line package; 28 leads (600 mil)	SOT117-1
TDA8001A
TDA8001T;	SO28	plastic small outline package; 28 leads; body width 7.5 mm	SOT136-1
TDA8001AT

1996 Dec 12

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Philips Semiconductors					Product specification
Smart card interface						TDA8001
QUICK REFERENCE DATA
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.		MAX.	UNIT
VDD	supply voltage		6.7	−		18	V
IDD	supply current	idle mode; VDD = 12 V	−	32		−	mA
		active modes; unloaded	−	45		−	mA
Vth2	threshold voltage on VSUP		4.5	−		4.72	V
Vth4	threshold voltage on VDD		6	−		6.5	V
VCC	card supply voltage	including static and dynamic	4.75	5.0		5.25	V
		loads on 100 nF capacitor
ICC	card supply current	operating	−	−		−100	mA
		detection	−	−150		−	mA
		limitation	−	−		−200	mA
VH	high voltage supply for		−	−		30	V
	VPP
VPP	card programming	including static and dynamic	P − 2.5%	−		P + 2.5%	V
	voltage (only at TDA8001	loads on 100 nF capacitor
	and TDA8001T)
	(P = 5, 12.5, 15 and 21 V)
IPP	programming current	operating	−	−		−50	mA
	(read or write mode)	detection	−	−75		−	mA
		limitation	−	−		−100	mA
SR	slew rate on VCC and VPP	maximum load capacitor 150 nF	−	0.38		−	V/μs
	(rise and fall)
tde	deactivation cycle duration		75	100		125	μs
fclk	clock frequency		0	−		8	MHz
Ptot	continuous total power	TDA8001; Tamb = +70 °C;	−	−		0.92	W
	dissipation	see Fig.10
		TDA8001T; Tamb = +70 °C;	−	−		2	W
		see Fig.11
Tamb	operating ambient		0	−		+70	°C
	temperature

1996 Dec 12

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Philips Semiconductors	Product specification
Smart card interface	TDA8001
BLOCK DIAGRAM

		VSUP	DELAY	VDD	GND1
		15	16	13	12
ALARM	17
		VOLTAGE			MAIN	22
	18	SUPERVISOR		SUPPLY		CVNC
ALARM
I/O(μC)	28					3
			PROTECTIONS			I/O
	26			AND		4
RSTIN			ENABLE
						RST
				TDA8001		9
						PRES
OFF	19	LOGIC				8
	2					PRES
DETECT		INTERNAL		PROTECTIONS
		CLOCK
CMDVCC	20				VCC	14
	27			GENERATOR		VCC
CMD7
GND2	25					5
		CLOCK			CLOCK
	23					CLK
CMD3.5		CIRCUITRY			ENABLE
CLKOUT2	24
VPP12.5	6
					VPP	10
	7
VPP15				GENERATOR		VPP
VPP21	21
		OSCILLATOR
		1			11
		XTAL				MBH813
					VH

Fig.1 Block diagram.

1996 Dec 12

4

Philips Semiconductors

Product specification

Smart card interface

TDA8001

PINNING

PIN

SYMBOL

DESCRIPTION

TDA8001

TDA8001A

TDA8001T

TDA8001AT

XTAL

1

1

crystal connection

2

2

card extraction open collector output (active LOW)

DETECT

I/O

3

3

data line to/from the card

RST

4

4

card reset output

CLK

5

5

clock output to the card

6

−

control input for applying the 12.5 V programming voltage (active LOW)

VPP12.5

n.c.

−

6

not connected

7

−

control input for applying the 15 V programming voltage (active LOW)

VPP15

n.c.

−

7

not connected

8

8

card presence contact input (active LOW)

PRES

PRES

9

9

card presence contact input (active HIGH)

VPP

10

−

card programming voltage output

n.c.

−

10

not connected

VH

11

11

HIGH voltage supply for VPP generation

GND1

12

12

ground 1

VDD

13

13

positive supply voltage

VCC

14

14

card supply output voltage

VSUP

15

15

voltage supervisor input

DELAY

16

16

external capacitor connection for delayed reset timing

ALARM

17

17

open-collector reset output for the microcontroller (active HIGH)

18

18

open-collector reset output for the microcontroller (active LOW)

ALARM

19

19

open-collector interrupt output to the microcontroller (active LOW)

OFF

20

20

control input for applying supply voltage to the card (active LOW)

CMDVCC

21

−

control input for applying the 21 V programming voltage (active LOW)

VPP21

n.c.

−

21

not connected

CVNC

22

22

internally generated 5 V reference, present when VDD is on; to be

decoupled externally (100 nF)

23

23

control input for having the crystal frequency divided-by-4 at pin CLK

CMD3.5

or CDMTC

CLKOUT2

24

24

clock output to the microcontroller, or any other R4590

(crystal frequency divided by two)

GND2

25

25

ground 2

RSTIN

26

26

card reset input from the microcontroller (active HIGH)

27

27

control input for having the crystal frequency divided by 2 at pin CLK

CMD7

or CDMS

I/O(μC)

28

28

data line to/from the microcontroller

1996 Dec 12

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Philips Semiconductors	Product specification
Smart card interface	TDA8001

handbook, halfpage								I/O(μC)								handbook, halfpage								I/O(μC)
			XTAL		1		28											XTAL			1		28
DETECT					2		27	CMD7 or CDMS								DETECT					2		27	CMD7 or CDMS
			I/O					RSTIN										I/O						RSTIN
					3		26														3		26
			RST		4		25	GND2										RST			4		25	GND2
			CLK		5		24	CLKOUT2										CLK			5		24	CLKOUT2
																		n.c.
	VPP12.5				6		23	CMD3.5 or CDMTC													6		23	CMD3.5 or CDMTC
	VPP15				7	TDA8001	22	CVNC										n.c.			7	TDA8001A	22	CVNC
						TDA8001T																TDA8001AT
			PRES		8		21	VPP21										PRES			8		21	n.c.
		PRES															PRES
					9		20	CMDVCC													9		20	CMDVCC
			VPP															n.c.
					10		19	OFF													10		19	OFF
			VH		11		18	ALARM										VH			11		18	ALARM
		GND1			12		17	ALARM									GND1				12		17	ALARM
			VDD															VDD
					13		16	DELAY													13		16	DELAY
			VCC					VSUP										VCC						VSUP
					14		15														14		15
						MBH811																MBH812

Fig.2 Pin configuration.

Fig.3 Pin configuration.

1996 Dec 12

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Philips Semiconductors		Product specification
Smart card interface		TDA8001

FUNCTIONAL DESCRIPTION

Power supply

The circuit operates within a supply voltage range of 6.7 to 18 V. VDD and GND are the supply pins. All card contacts remain inactive during power up or down.

POWER UP

The logic part is powered first and is in the reset condition until VDD reaches Vth1. The sequencer is blocked until VDD reaches Vth4 + Vhys4.

POWER DOWN

When VDD falls below Vth4, an automatic deactivation of the contacts is performed.

Voltage supervisor

This block surveys the 5 V supply of the microcontroller (VSUP) in order to deliver a defined reset pulse and to avoid any transients on card contacts during power up or down of VSUP. The voltage supervisor remains active even if VDD is powered-down.

POWER ON

As long as VSUP is below Vth2 + Vhys2 the capacitor CDEL, connected to pin DELAY, will be discharged. When VSUP

rises to the threshold level, CDEL will be recharged.

ALARM and ALARM remain active, and the sequencer is blocked until the voltage on the DELAY line reaches Vth3.

POWER DOWN (see Fig.4)

If VSUP falls below Vth2, CDEL will be discharged, ALARM and ALARM become active, and an automatic deactivation of the contacts is performed.

CMD3.5 and internal ENRST are sampled in order to give the first clock pulse the correct width, and to avoid false pulses during frequency change.

The CLKOUT2 pins may be used to clock a microcontroller or an other TDA8001. The signal 1¤2 fxtal is available when the circuit is powered up.

State diagram

Once activated, the circuit has six possible modes of operation:

·Idle

·Activation

·Read

·Write

·Deactivation

·Fault.

Figure 6 shows the way these modes are accessible.

IDLE MODE

After reset, the circuit enters the IDLE state. A minimum number of circuits are active while waiting for the microcontroller to start a session.

·All card contacts are inactive

·I/O(mC) is high impedance

·Voltage generators are stopped

·Oscillator or XTAL input is running, delivering CLKOUT2

·Voltage supervisors are active.

The DETECT line is HIGH if a card is present (PRES and PRES active) and LOW if a card is not present. The OFF line is HIGH if no hardware problem is detected.

ACTIVATION SEQUENCE

Clock circuitry (see Fig.5)

The clock signal (CLK) can be applied to the card in two different methods:

1.Generation by a crystal oscillator: the crystal, or the ceramic resonator (4 to 16 MHz) is connected to the XTAL pin.

2.Use of a signal frequency (up to 20 MHz), already present in the system and connected to the XTAL pin via a 10 nF capacitor (see Fig.14). In both cases the frequency is first divided-by-two.

If CMD7 (respectively CMD3.5) is LOW, the clock signal (its frequency again divided by two) is enabled and buffered before being fed to the CLK pin.

From the IDLE mode, the circuit enters the ACTIVATION mode when the microcontroller sets the CMDVCC line (active LOW). The I/O(mC) signal must not be LOW. The internal circuitry is activated, the internal clock starts and the sequence according to ISO7816 is performed:

·VCC rises from 0 to 5 V

·VPP rises from 0 to 5 V and I/O is enabled

·CLK and RST are enabled.

The time interval between steps 1 and 2 is 16 ms, and 64 ms between steps 2 and 3 (see Fig.7).

1996 Dec 12

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Philips Semiconductors	Product specification
Smart card interface	TDA8001

READ MODE

When the activation sequence is completed and, after the card has replied its Answer-to-Reset, the TDA8001 will be in the READ mode. Data is exchanged between the card and the microcontroller via the I/O line.

WRITE MODE

Cards with EPROM memory need a programming voltage (VPP). When it is required to write to the internal memory

of the card, the microcontroller sets one of the VPP12.5, VPP15 and VPP21 lines LOW, according to the programming value given in the Answer-to-Reset.

VPP rises from 5 V to the selected value with a typical slew rate of 0.38 V/μs. In order to respect the ISO 7816 slopes, the circuit generates VPP by charging and discharging an internal capacitor. The voltage on this capacitor is then amplified by a power stage gain of 5, powered via an external supply pin VH (30 V max).

DEACTIVATION SEQUENCE (see Fig.8)

When the session is completed, the microcontroller sets the CMDVCC line to its HIGH state. The circuit then executes an automatic deactivation sequence by counting the sequencer back:

∙RST falls to LOW and CLK is stopped

∙I/O(μC) becomes high impedance and VPP falls to 0 V

∙VCC falls to 0 V.

The circuit returns to the IDLE mode on the next rising edge of the clock.

PROTECTIONS

Main fault conditions are monitored by the circuit:

∙Short-circuit or overcurrent on VCC

∙Short-circuit or overcurrent on VPP

∙Card extraction during transaction

∙Overheating problem

∙VSUP drop-out

∙VDD drop-out.

When one of these fault conditions is detected, the circuit pulls the interrupt line OFF to its active LOW state and returns to the FAULT mode. The current on I/O is internally limited to 5 mA.

FAULT MODE (see Fig.9)

When a fault condition is written to the microcontroller via the OFF line, the circuit initiates a deactivation sequence. After the deactivation sequence has been completed, the OFF line is reset to its HIGH state after the microcontroller has reset the CMDVCC line HIGH.

Vth2 + Vhys2

Vth2

VSUP

Vth3

VDELAY

td

ALARM

MGG818

Fig.4 Alarm and delay as a function of VSUP (CDEL fixes the pulse width).

1996 Dec 12

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