Philips TDA8362, TDA8361, TDA8360 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

TDA8360; TDA8361; TDA8362

Integrated PAL and PAL/NTSC TV processors

Objective specification	March 1994
File under Integrated Circuits, IC02

Philips Semiconductors

Philips Semiconductors	Objective specification

Integrated PAL and PAL/NTSC TV

TDA8360; TDA8361; TDA8362

processors

FEATURES

Available in TDA8360, TDA8361

and TDA8362

∙Vision IF amplifier with high sensitivity and good differential gain and phase

∙Multistandard FM sound demodulator (4.5 MHz to 6.5 MHz)

∙Integrated chrominance trap and bandpass filters (automatically calibrated)

∙Integrated luminance delay line

∙RGB control circuit with linear RGB inputs and fast blanking

∙Horizontal synchronization with two control loops and alignment-free horizontal oscillator without external components

∙Vertical count-down circuit

(50/60 Hz) and vertical preamplifier

∙Low dissipation (700 mW)

∙Small amount of peripheral components compared with competition ICs

∙Only one adjustment (vision IF demodulator)

∙The supply voltage for the ICs is 8 V. They are mounted in a shrink DIL envelope with 52 pins and are pin compatible.

Additional features

TDA8360

∙Alignment-free PAL colour decoder for all PAL standards, including PAL-N and PAL-M.

TDA8361

∙PAL/NTSC colour decoder with automatic search system

∙Source selection for external audio/video (A/V) inputs (separate Y/C signals can also be applied).

TDA8362

∙Multistandard vision IF circuit (positive and negative modulation)

∙PAL/NTSC colour decoder with automatic search system

∙Source selection for external A/V inputs (separate Y/C signals can also be applied)

∙Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications.

GENERAL DESCRIPTION

The TDA8360, TDA8361 and TDA8362 are single-chip TV processors which contain nearly all small signal functions that are required for a colour television receiver. For a complete receiver the following circuits need to be added: a base-band delay line (TDA4661), a tuner and output stages for audio, video and horizontal and vertical deflection.

Because of the different functional contents of the ICs the set maker can make the optimum choice depending on the requirements for the receiver.

The TDA8360 is intended for simple PAL receivers (all PAL standards, including PAL-N and PAL-M are possible).

The TDA8361 contains a PAL/NTSC decoder and has an A/V switch.

For real multistandard applications the TDA8362 is available. In addition to the extra functions which are available in the TDA8361, the TDA8362 can handle signals with positive modulation and it supplies the signals which are required for the SECAM decoder TDA8395.

ORDERING INFORMATION

EXTENDED TYPE			PACKAGE
NUMBER	PINS	PIN POSITION		MATERIAL	CODE
TDA8360	52	shrink DIL		plastic	SOT247AG
TDA8361	52	shrink DIL		plastic	SOT247AG
TDA8362	52	shrink DIL		plastic	SOT247AG

March 1994

2

Philips Semiconductors	Objective specification

Integrated PAL and PAL/NTSC TV

TDA8360; TDA8361; TDA8362

processors

QUICK REFERENCE DATA

SYMBOL		PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
VP		supply voltage		7.2	8.0	8.8	V
IP		supply current		−	80	−	mA
Input voltages
V45,46(rms)		video IF amplifier sensitivity (RMS value)		−	70	100	μV
V5(rms)		sound IF amplifier sensitivity (RMS value)		−	1	−	mV
V6(rms)		external audio input (RMS value)	TDA8361, TDA8362	−	350	−	mV
V15(p-p)		external CVBS input (peak-to-peak value)	TDA8361, TDA8362	−	1	−	V
V22,23,24(p−p)		RGB inputs (peak-to-peak value)		−	0.7	−	V
Output signals
VO(p-p)		demodulated CVBS output		−	2.4	−	V
		(peak-to-peak value)
I47		tuner AGC control current		0	−	5	mA
V44		AFC output voltage swing		−	6	−	V
V50(rms)		audio output voltage (RMS value)		−	700	−	mV
V18,19,20(p-p)		RGB output signal amplitudes		−	4	−	V
		(peak-to-peak value)
I37		horizontal output current		10	−	−	mA
I43		vertical output current		1	−	−	mA
Control voltages
Vcontrol		control voltages for Volume, Contrast,		0	−	5	V
		Saturation, Brightness, Hue and Peaking

March 1994

3

March1994

flyback

sandcastle

processors

IntegratedPAL

SemiconductorsPhilips

VRAMP

PH1LF

PH2LF

FBI/SCO

DEC AGC

XTAL1

XTAL2

TUNE ADJ

VOUT

AGCOUT

VFB

VSTART

HOUT

and

47

49

48

43

41

42

40

36

39

38

37

34

35

IFIN1

45

IF

VERTICAL

XTAL

PAL/NTSC

AGC

PHASE 1

PHASE 2

46

AMPLIFIER

OUTPUT

OSCILLATOR

IFIN2

IFDEM1

2

AFC AND

VERTICAL

LINE

COLOUR

PHASE

DEMODULATOR

SAMPLE-

TUNING

DIVIDER

OSCILLATOR

KILLERS

DETECTOR

33

3

AND-HOLD

IFDEM2

44

DET

AFCOUT

TV

7

30

R-Y output

IFOUT

VIDEO

VIDEO

H AND V

COINCIDENCE

ACC

PAL

DEMODULATOR

31

to

AMPLIFIER

IDENTIFICATION

SEPARATION

DETECTOR

AMPLIFIER

IDENTIFICATION

TDA4661

4

4

B-Y output

IDENT

26

8

SAT

DECDIG

28

B-Y input

NOISE

POWER

CHROMINANCE

CLAMPS

from

TEST

SUPPLY

MATRIX

29

DETECTOR

RESET

BANDPASS

SET

TDA4661

AUDEEM

R-Y input

TDA8360;

1

50

22

RIN

AUOUT

PREAMPLIFIER

TRAP AND

Y DELAY

LUMINANCE

CLAMP

23

VOLUME

TUNING

GIN

MUTE

BYPASS

PEAKING

MATRIX

SWITCH

24

BIN

DEC DEM

51

21

RGBIN

18

BOUT

TDA8362 TDA8361;

TDA8360

OUTPUT

19

LIMITER

PLL

PWL

GOUT

5

STAGES

20

ROUT

SOIF

11

9

10

52

12

13

14

25

17

MLA621 - 1

volume

CVBS INT

PEAKIN

CON

BRI

specification Objective

GND2

GND1

VP

control

DEC FT

DEC BG

Fig.1

Block diagram for TDA8360.

1994 March

flayback

sandcastle

processors

PALIntegrated

SemiconductorsPhilips

VRAMP

PH1LF

PH2LF

FBI/SCO

DEC AGC

XTAL1

XTAL2

TUNE ADJ

VOUT

AGCOUT

VFB

VSTART

HOUT

and

IFIN1

47

49

48

43

41

42

40

36

39

38

37

34

35

45

IF

AGC

VERTICAL

PHASE 1

PHASE 2

XTAL

HUE

27

HUE

PAL/NTSC

46

AMPLIFIER

OUTPUT

OSCILLATOR

CONTROL

IFIN2

44

IFDEM1

2

AFC AND

VERTICAL

LINE

COLOUR

PHASE

DEMODULATOR

SAMPLE-

TUNING

DIVIDER

OSCILLATOR

KILLERS

DETECTOR

33

3

AND-HOLD

IFDEM2

DET

AFCOUT

TV

30

R-Y output

7

VIDEO

VIDEO

H AND V

COINCIDENCE

ACC

SYSTEM

to

IFOUT

DEMODULATOR

31

AMPLIFIER

IDENTIFICATION

SEPARATION

DETECTOR

AMPLIFIER

MANAGER

TDA4661

4

B-Y output

5

IDENT

26

8

SAT

DECDIG

28

B-Y input

NOISE

POWER

CHROMINANCE

CLAMPS

from

TEST

SUPPLY

MATRIX

29

DETECTOR

RESET

BANDPASS

SET

TDA4661

AUDEEM

1

R-Y input

TDA8360;

EXTAU

6

18

22

RIN

50

PREAMPLIFIER

TRAP AND

Y DELAY

LUMINANCE

CLAMP

23

AUOUT

VOLUME

TUNING

GIN

MUTE

BYPASS

PEAKING

MATRIX

SWITCH

24

BIN

DEC DEM

51

21

RGBIN

TDA8361

LUMINANCE

CHROMINANCE

OUTPUT

19

BOUT

TDA8362TDA8361;

LIMITER

PLL

PWL

GOUT

specificationObjective

5

SWITCH

SWITCH

STAGES

20

ROUT

SOIF

11

9

10

52

12

13

15

14

16

25

17

MLA622 - 1

volume

CVBS INT

CVBSEXT

CHROMA

CON

BRI

control

GND2

GND1

VP

PEAKIN

DEC FT

DEC BG

Fig.2

Block diagram for TDA8361.

1994 March

flyback sandcastle

VRAMP PH1LF	FBI/SCO
	PH2LF

AUOUT

DEC AGC

XTAL1

XTAL2

VOUT

IDENT

AGCOUT

AFCOUT

VFB

VSTART

HOUT

XTALOUT

HUE

4

50

47

48

44

43

41

42

40

36

39

38

37

34

35

32

27

IFIN1

45

IF

VERTICAL

XTAL

HUE

AGC

PHASE 1

PHASE 2

46

AMPLIFIER

OUTPUT

OSCILLATOR

CONTROL

IFIN2

TUNE ADJ

49

IFDEM1

2

AFC AND

VERTICAL

LINE

SYSTEM

PHASE

DEMODULATOR

SAMPLE-

TUNING

33

DIVIDER

OSCILLATOR

MANAGER

DETECTOR

3

AND-HOLD

IFDEM2

DET

IFOUT

7

30

R-Y output

VIDEO

VIDEO

POWER

H AND V

COINCIDENCE

COLOUR

to

DEMODULATOR

31

IDENTIFICATION

AMPLIFIER

RESET

SEPARATION

DETECTOR

KILLERS

TDA4661

B-Y output

6

1

AUDEEM

6

28

B-Y input

EXTAU

SWITCH

PREAMPLIFIER

TDA8362

NOISE

ACC

CLAMPS

from

MATRIX

29

VOLUME

MUTE

DETECTOR

AMPLIFIER

SET

TDA4661

R-Y input

DEC DEM

51

22

RIN

TRAP AND

CHROMINANCE

CHROMINANCE

LUMINANCE

CLAMP

23

5

LIMITER

PLL

GIN

BYPASS

SWITCH

BANDPASS

MATRIX

SWITCH

24

SOIF

BIN

volume

control

18

BOUT

8

LUMINANCE

Y DELAY

OUTPUT

19

SUPPLY

TEST

TUNING

PWL

GOUT

SWITCH

PEAKING

STAGES

20

DECDIG

ROUT

11

9

10

52

12

16

13

15

14

26

21

25

17

MBC214 - 1

CVBS INT CVBSEXT

PEAKIN

CON

BRI

GND2

GND1

VP

CHROMA

SAT RGBIN

DEC FT

DEC BG

Fig.3 Block diagram for TDA8362.

TV PAL/NTSC and PAL Integrated processors

TDA8362 TDA8361; TDA8360;

Semiconductors Philips

specification Objective

Philips Semiconductors	Objective specification

Integrated PAL and PAL/NTSC TV

TDA8360; TDA8361; TDA8362

processors

PINNING (TDA8362)

				DEC BG
AUDEEM	1		52
				DEC DEM
IFDEM1	2		51
IFDEM2				AUOUT
	3		50
				TUNEADJ
IDENT	4		49
				DECAGC
SOIF	5		48
EXTAU	6		47	AGCOUT
				IFIN2
IFOUT	7		46
DEC DIG
	8		45	IFIN1
				AFCOUT
GND1	9		44
VP
	10		43	VOUT
GND2	11		42	VRAMP
DEC FT
	12		41	VFB
CVBS INT
	13		40	PH1LF
		TDA8362
PEAKIN	14		39	PH2LF
CVBSEXT				FBI/SCO
	15		38
				HOUT
CHROMA	16		37
BRI				VSTART
	17		36
BOUT				XTAL2
	18		35
				XTAL1
GOUT	19		34
ROUT	20		33	DET
RGBIN	21		32	XTALOUT
RIN	22		31	BYO
GIN	23		30	RYO
BIN	24		29	RYI
CON
	25		28	BYI
SAT	26		27	HUE
		MBC203

Fig.4 Pin configuration for TDA8362.

SYMBOL	PIN	DESCRIPTION
AUDEEM	1	audio de-emphasis and ± modulation switch
IFDEM1	2	IF demodulator tuned circuit
IFDEM2	3	IF demodulator tuned circuit
IDENT	4			input
		video identification output/MUTE
SOIF	5	sound IF input and volume control
EXTAU	6	external audio input
IFOUT	7	IF video output
DECDIG	8	decoupling digital supply
GND1	9	ground 1
VP	10	supply voltage (+8 V)
GND2	11	ground 2
DECFT	12	decoupling filter tuning
CVBSINT	13	internal CVBS input
PEAKIN	14	peaking control input
CVBSEXT	15	external CVBS input
CHROMA	16	chrominance and A/V switch input
BRI	17	brightness control input
BOUT	18	blue output
GOUT	19	green output
ROUT	20	red output
RGBIN	21	RGB insertion and blanking input
RIN	22	red input
GIN	23	green input
BIN	24	blue input
CON	25	contrast control input
SAT	26	saturation control input
HUE	27	hue control input (or chrominance output)
BYI	28	B−Y input signal
RYI	29	R−Y input signal
RYO	30	R−Y output signal
BYO	31	B−Y output signal
XTALOUT	32	4.43 MHz output for TDA8395
DET	33	loop filter burst phase detector
XTAL1	34	3.58 MHz crystal connection
XTAL2	35	4.43 MHz crystal connection
VSTART	36	supply/start horizontal oscillator
HOUT	37	horizontal output
FBI/SCO	38	flyback input/sandcastle output
PH2LF	39	phase 2 loop filter
PH1LF	40	phase 1 loop filter

March 1994

7

Philips Semiconductors	Objective specification

Integrated PAL and PAL/NTSC TV

TDA8360; TDA8361; TDA8362

processors

SYMBOL	PIN	DESCRIPTION
VFB	41	vertical feedback input
VRAMP	42	vertical ramp generator
VOUT	43	vertical output
AFCOUT	44	AFC output
IFIN1	45	IF input 1
IFIN2	46	IF input 2
AGCOUT	47	tuner AGC output
DECAGC	48	AGC decoupling capacitor
TUNEADJ	49	tuner take-over adjustment
AUOUT	50	audio output
DECDEM	51	decoupling sound demodulator
DECBG	52	decoupling bandgap supply

TDA8360

The TDA8360 has the following differences to the pinning:

Pin 6: external audio input not connected

Pin 15: external CVBS input not connected

Pin 16: chrominance and A/V switch input not connected

Pin 27: hue control input not connected.

TDA8361

The TDA8361 has the following differences to the pinning:

Pin 1: only audio de-emphasis

Pin 27: only hue control

Pin 32: 4.43 MHz output for TDA8395 is not connected.

FUNCTIONAL DESCRIPTION

Video IF amplifier

The IF amplifier contains

3 AC-coupled control stages with a total gain control range of greater than 60 dB. The sensitivity of the circuit is comparable with that of modern IF ICs.

The reference carrier for the video demodulator is obtained by means of passive regeneration of the picture carrier. The external reference tuned circuit is the only remaining adjustment of the IC.

In the TDA8362 the polarity of the demodulator can be switched so that the circuit is suitable for both positive and negative modulated signals.

The AFC circuit is driven with the same reference signal as the video demodulator. To ensure that the video content does not disturb the AFC operation a sample-and-hold circuit is incorporated; the capacitor for this function is internal. The AFC output voltage is 6 V.

The AGC detector operates on levels, top sync for negative modulated and top white for positive modulated signals.The AGC detector time constant capacitor is connected externally. This is mainly because of the flexibility of the application.

The time constant of the AGC system during positive modulation (TDA8362) is slow, this is to avoid any visible picture variations. This, however, causes the system to react very slowly to sudden changes in the input signal amplitude.

To overcome this problem a speed-up circuit has been included which detects whether the AGC detector is activated every frame period. If, during a 3-frame period, no action is detected the speed of the system is increased. When the incoming signal has no peak white information (e.g. test lines in the vertical retrace period) the gain would be video signal dependent. To avoid this effect the circuit also contains a black level AGC detector which is activated when the black level of the video signal exceeds a certain level.

The TDA8361 and TDA8362 contain a video identification circuit which is independent of the synchronization circuit. Therefore search tuning is possible when the display section of the receiver is used as a monitor. In the TDA8360 this circuit is only used for stable OSD at no signal input. In the normal television mode the identification output is connected to the coincidence detector, this applies to all three devices. The identification output voltage is LOW when no transmitter is identified. In this condition the sound demodulator is switched off (mute function). When a transmitter is identified the output voltage is HIGH. The voltage level is dependent on the frequency of the incoming chrominance signal.

March 1994

8

Philips Semiconductors	Objective specification

Integrated PAL and PAL/NTSC TV

TDA8360; TDA8361; TDA8362

processors

Sound circuit

The sound bandpass and trap filters have to be connected externally. The filtered intercarrier signal is fed to a limiter circuit and is demodulated by means of a PLL demodulator. The PLL circuit tunes itself automatically to the incoming signal, consequently, no adjustment is required.

The volume is DC controlled. The composite audio output signal has an amplitude of 700 mV RMS at a volume control setting of −6 dB. The de-emphasis capacitor has to be connected externally. The non-controlled audio signal can be obtained from this pin via a buffer stage. The amplitude of this signal is 350 mV RMS.

The TDA8361 and TDA8362 external audio input signal must have an amplitude of 350 mV RMS. The audio/video switch is controlled via the chrominance input pin.

Synchronization circuit

The sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed level. The sync pulses are then fed to the slicing stage (separator) which operates at 50% of the amplitude.

The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence detector is used for transmitter identification and to detect whether the line oscillator is synchronized. When the circuit is not synchronized the voltage on the peaking control pin (pin 14) is LOW so that this condition can be detected externally. The first PLL has a very high static steepness, this ensures that the phase of the picture is independent of the line frequency. The line oscillator operates at twice the line frequency.

The oscillator network is internal. Because of the spread of internal components an automatic adjustment circuit has been added to the IC. The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. This results in a free-running frequency which deviates less than 2% from the typical value.

The circuit employs a second control loop to generate the drive pulses for the horizontal driver stage.

X-ray protection can be realised by switching the pin of the second control loop to the positive supply line. The detection circuit must be connected externally. When the X-ray protection is active the horizontal output voltage is switched to a high level. When the voltage on this pin returns to its normal level the horizontal output is released again.

The IC contains a start-up circuit for the horizontal oscillator. When this feature is required a current of 6.5 mA has to be supplied to pin 36. For an application without start-up both supply pins (10 and 36) must be connected to the 8 V supply line.

The drive signal for the vertical ramp generator is generated by means of a divider circuit. The RC network for the ramp generator is external.

Integrated video filters

The circuit contains a chrominance bandpass and trap circuit. The filters are realised by means of gyrator circuits and are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder.

In the TDA8361 and TDA8362 the chrominance trap is active only when the separate chrominance input pin is connected to ground or to the positive supply voltage and when a colour signal is recognized.

When the pin is left open-circuit the trap is switched off so that the circuit can also be used for S-VHS applications.

The luminance delay line and the delay for the peaking circuit are also realised by means of gyrator circuits.

Colour decoder

The colour decoder in the various ICs contains an alignment-free crystal oscillator, a colour killer circuit and colour difference demodulators.

The 90° phase shift for the reference signal is achieved internally. Because the main differences of the 3 ICs are found in the colour decoder the various types will be discussed.

TDA8360

This IC contains only a PAL decoder. Depending on the frequency of the crystals which are connected to the IC the decoder can demodulate all PAL standards. Because the horizontal oscillator is calibrated by using the crystal frequency as a reference the 4.4 MHz crystal must be connected to pin 35 and the 3.5 MHz crystal to pin 34. When only one crystal is connected to the IC the other crystal pin must be connected to the positive supply rail via a 47 kΩ resistor. For applications with two 3.5 MHz crystals both must be connected to pin 34 and the switching between the crystals must be made externally. Switching of the crystals is only allowed directly after the vertical retrace. The circuit will indicate whether a PAL signal has been identified by the colour decoder via the saturation control pin.

When two crystals are connected to the IC the output voltage of the video identification circuit indicates the frequency of the incoming chrominance signal.

March 1994

9

Philips Semiconductors	Objective specification

Integrated PAL and PAL/NTSC TV

TDA8360; TDA8361; TDA8362

processors

The conditions are:

∙Signal identified at

fosc = 3.6 MHz; VO = 6 V

∙Signal identified at

fosc = 4.4 MHz (or no colour); VO = 8 V.

This information can be used to switch the sound bandpass filter and trap filter.

TDA8361

This IC contains an automatic PAL/NTSC decoder. The conditions for connecting the reference crystals are the same as for the TDA8360. The decoder can be forced to PAL when the hue control pin is connected to the positive supply voltage via a

5 kΩ or 10 kΩ resistor (approximately). The decoder cannot be forced to the NTSC standard. It is also possible to see if a colour signal is recognized via the saturation pin.

TDA8362

In addition to the possibilities of the TDA8361, the TDA8362 can co-operate with the SECAM add-on decoder TDA8395.

The communication between the two ICs is achieved via pin 32. The TDA8362 supplies the reference signal (4.43 MHz) for the calibration system of the TDA8395, identification of the colour standard is via the same connection. When a SECAM signal is detected by the TDA8395 the IC will draw a current of 150 μA. When TDA8362 has not identified a colour signal in this condition it will go into the SECAM mode, that means it will switch off the R−Y and B−Y outputs and increase the voltage level on pin 32.

This voltage will switch off the colour-killer in the TDA8395 and switch on the R−Y and B−Y outputs of the TDA8395. Forcing the system to the SECAM standard can be achieved by loading pin 32 with a current of 150 μA. Then the system manager in the TDA8362 will not search for PAL or NTSC signals. Forcing to NTSC is not possible. For PAL/SECAM applications the input signal for the TDA8395 can be obtained from pin 27 (hue control) when this pin is connected to the positive supply rail via the 5 kΩ or 10 kΩ resistor. An external source selector is required by the TDA8395/TDA8362 combination for PAL/SECAM/NTSC applications.

RGB output circuit

The colour difference signals are matrixed with the luminance signal to obtain the RGB signals. Linear amplifiers have been chosen for the RGB inputs so that the circuit is suitable for incoming signals from the SCART connector. The contrast and brightness controls operate on internal and external signals.

The fast blanking pin has a second detection level at 3.5 V.

When this level is exceeded the RGB outputs are blanked so that “On-Screen-Display” signals can be applied to the outputs.

The output signal has an amplitude of approximately 4 V, black-to-white, with nominal input signals and nominal control settings. The nominal black level is 1.3 V.

March 1994

10

Philips Semiconductors	Objective specification

Integrated PAL and PAL/NTSC TV

TDA8360; TDA8361; TDA8362

processors

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134).

SYMBOL	PARAMETER	MIN.	MAX.	UNIT
VP	supply voltage	−	9.0	V
Tstg	storage temperature	−25	+150	°C
Tamb	operating ambient temperature	−25	+70	°C
Tsol	soldering temperature for 5 s	−	260	°C
Tj	maximum junction temperature (operating)	−	150	°C
THERMAL RESISTANCE
SYMBOL	PARAMETER	THERMAL RESISTANCE
Rth j-a	from junction to ambient in free air		40 K/W

CHARACTERISTICS

VP = 8 V; Tamb = 25 °C; unless otherwise specified.

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supplies
VP	supply voltage (pin 10)		7.2	8.0	8.8	V
IP	supply current (pin 10)		−	80	−	mA
IHOSC	horizontal oscillator start current	note 1	6.5	−	−	mA
	(pin 36)
Ptot	total power dissipation	including start supply	−	0.7	−	W
IF circuit
VISION IF AMPLIFIER INPUTS (PINS 45 AND 46)
Vi(rms)	input sensitivity (RMS value)	note 2
		fi = 38.90 MHz	−	70	100	μV
		fi = 45.75 MHz	−	70	100	μV
		fi = 58.75 MHz	−	70	100	μV
RI	Input resistance (differential)	note 3	−	2	−	kΩ
CI	Input capacitance (differential)	note 3	−	3	−	pF
Gcr	gain control range		64	−	−	dB
Vi(rms)	maximum input signal (RMS value)		100	−	−	mV

March 1994

11