Philips TDA6403AM-C1, TDA6402M-C2, TDA6402AM-C2, TDA6402AM-C1-M1, TDA6403M-C3 Datasheet
...
INTEGRATED CIRCUITS
DATA SHEET
TDA6402; TDA6402A; TDA6403; TDA6403A
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
Product specification |
2000 Jan 24 |
Supersedes data of 1998 Jul 28
File under Integrated Circuits, IC02
Philips Semiconductors |
Product specification |
|
|
5 V mixers/oscillators and synthesizers for |
TDA6402; TDA6402A; |
cable TV and VCR 2-band tuners |
TDA6403; TDA6403A |
|
|
|
|
FEATURES
∙Single-chip 5 V mixer/oscillator and synthesizer for cable TV and VCR tuners
∙Synthesizer function compatible with existing TSA5526
∙Universal bus protocol (I2C-bus or 3-wire bus)
–Bus protocol for 18 or 19-bit transmission (3-wire bus)
–Extra protocol for 27-bit transmission (test modes and features for 3-wire bus)
–Address + 4 data bytes transmission (I2C-bus ‘write’ mode)
–Address + 1 status byte (I2C-bus ‘read’ mode)
–4 independent I2C-bus addresses.
∙1 PNP buffer for UHF band selection (25 mA)
∙3 PNP buffers for general purpose, e.g. 2 VHF sub-bands, FM sound trap (25 mA)
∙33 V tuning voltage output
∙In-lock detector
∙5-step A/D converter (3 bits in I2C-bus mode)
∙15-bit programmable divider
∙Programmable reference divider ratio (512, 640 or 1024)
∙Programmable charge pump current (60 or 280 μA)
∙Programmable automatic charge pump current switch
∙Varicap drive disable
∙Mixer/oscillator function compatible with existing TDA5732
∙Balanced mixer with a common emitter input for VHF (single input)
∙Balanced mixer with a common base input for UHF (balanced input)
∙2-pin common emitter oscillator for VHF
∙4-pin common emitter oscillator for UHF
∙IF preamplifier with asymmetrical 75 Ω output impedance to drive a low-ohmic impedance (75 Ω)
∙Low power
∙Low radiation
∙Small size
∙The TDA6402A and TDA6403A differ from the TDA6402 and TDA6403 by the UHF port protocol in the I2C-bus mode (see Tables 3 and 4).
APPLICATIONS
∙Cable tuners for TV and VCR (switched concept for VHF)
∙Recommended RF bands for the USA:
55.25to 133.25 MHz, 139.25 to 361.25 MHz and
367.25to 801.25 MHz.
GENERAL DESCRIPTION
The TDA6402, TDA6402A, TDA6403 and TDA6403A are programmable 2-band mixers/oscillators and synthesizers intended for VHF/UHF cable tuners (see Fig.1).
The devices include two double balanced mixers and two oscillators for the VHF and UHF band respectively, an IF amplifier and a PLL synthesizer. The VHF band can be split-up into two sub-bands using a proper oscillator application and a switchable inductor. Two pins are available between the mixer output and the IF amplifier input to enable IF filtering for improved signal handling. Four PNP ports are provided. Band selection is provided by using pin PUHF. When PUHF is ‘ON’, the UHF mixer-oscillator is active and the VHF band is switched off. When PUHF is ‘OFF’, the VHF mixer-oscillator is active and the UHF band is ‘OFF’. PVHFL and PVHFH are used to select the VHF sub-bands. FMST is a general purpose port, that can be used to switch an FM sound trap. When it is used, the sum of the collector currents has to be limited to 30 mA.
The synthesizer consists of a divide-by-eight prescaler, a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and a phase/frequency detector combined with a charge pump which drives the tuning amplifier, including 33 V output (V33) at pin VT.
Depending on the reference divider ratio (512, 640 or 1024), the phase comparator operates at 7.8125 kHz, 6.25 kHz or 3.90625 kHz with a 4 MHz crystal.
2000 Jan 24 |
2 |
Philips Semiconductors |
Product specification |
|
|
5 V mixers/oscillators and synthesizers for |
TDA6402; TDA6402A; |
cable TV and VCR 2-band tuners |
TDA6403; TDA6403A |
|
|
The device can be controlled according to the I2C-bus format or 3-wire bus format depending on the voltage applied to pin SW (see Table 2). In the 3-wire bus mode (SW = HIGH), pin LOCK/ADC is the LOCK output.
The LOCK output is LOW when the PLL loop is locked. In the I2C-bus mode (SW = LOW), the lock detector bit FL is set to logic 1 when the loop is locked and is read on the SDA line (Status Byte; SB) during a READ operation in I2C-bus mode only. The Analog-to-Digital Converter (ADC) input is available on pin LOCK/ADC for digital AFC control in the I2C-bus mode only. The ADC code is read during a READ operation on the I2C-bus (see Table 11). In test mode, pin LOCK/ADC is used as a TEST output for
fREF and 1¤2fDIV, in both I2C-bus mode and 3-wire bus mode (see Table 7).
When the automatic charge pump current switch mode is activated and when the loop is phase-locked, the charge pump current value is automatically switched to LOW. This action is taken to improve the carrier-to-noise ratio.
The status of this feature can be read in the ACPS flag during a READ operation on the I2C-bus (see Table 9).
I2C-bus mode (SW = GND)
Five serial bytes (including address byte) are required to address the device, select the VCO frequency, program the four ports, set the charge pump current and set the reference divider ratio. The device has four independent I2C-bus addresses which can be selected by applying a specific voltage on input CE (see Table 6).
3-wire bus mode (SW = OPEN or VCC)
Data is transmitted to the devices during a HIGH-level on input CE (enable line). The device is compatible with 18-bit and 19-bit data formats, as shown in Figs 4 and 5. The first four bits are used to program the PNP ports and the remaining bits control the programmable divider. A 27-bit data format may also be used to set the charge pump current, the reference divider ratio and for test purposes (see Fig.6).
It is not allowed to address the devices with words whose length is different from 18, 19 or 27 bits.
Table 1 Data word length for 3-wire bus
TYPE NUMBER |
DATA WORD |
REFERENCE DIVIDER(1) |
FREQUENCY STEP |
TDA6402; TDA6402A; TDA6403; TDA6403A |
18-bit |
512 |
62.50 kHz |
|
|
|
|
TDA6402; TDA6402A; TDA6403; TDA6403A |
19-bit |
1024 |
31.25 kHz |
|
|
|
|
TDA6402; TDA6402A; TDA6403; TDA6403A |
27-bit |
programmable |
programmable |
|
|
|
|
Note
1.The selection of the reference divider is given by an automatic identification of the data word length. When the 27-bit format is used, the reference divider is controlled by RSA and RSB bits (see Table 8). More details are given in Chapter “PLL functional description”, Section “3-wire bus mode (SW = OPEN or VCC)”.
2000 Jan 24 |
3 |
Philips Semiconductors Product specification
5 V mixers/oscillators and synthesizers for |
TDA6402; TDA6402A; |
||||||
cable TV and VCR 2-band tuners |
TDA6403; TDA6403A |
||||||
|
|
|
|
|
|
|
|
QUICK REFERENCE DATA |
|
|
|
|
|
|
|
Measured over full voltage and temperature ranges; unless otherwise specified. |
|
|
|
|
|||
|
|
|
|
|
|
|
|
SYMBOL |
PARAMETER |
CONDITIONS |
|
MIN. |
TYP. |
MAX. |
UNIT |
|
|
|
|
|
|
|
|
VCC |
supply voltage |
operating |
|
4.5 |
5 |
5.5 |
V |
ICC |
supply current |
all PNP ports are ‘OFF’ |
|
- |
71 |
- |
mA |
fXTAL |
crystal oscillator input frequency |
|
|
3.2 |
4.0 |
4.48 |
MHz |
Io(PNP) |
PNP port output current |
note 1 |
|
- |
- |
30 |
mA |
Ptot |
total power dissipation |
note 2 |
|
- |
- |
490 |
mW |
Tstg |
IC storage temperature |
|
|
-40 |
- |
+150 |
°C |
Tamb |
ambient temperature |
|
|
-20 |
- |
+85 |
°C |
fRF |
RF frequency |
VHF band |
|
55.25 |
- |
361.25 |
MHz |
|
|
UHF band |
|
367.25 |
- |
801.25 |
MHz |
|
|
|
|
|
|
|
|
GV |
voltage gain |
VHF band |
|
- |
19 |
- |
dB |
|
|
UHF band |
|
- |
29 |
- |
dB |
|
|
|
|
|
|
|
|
NF |
noise figure |
VHF band |
|
- |
8.5 |
- |
dB |
|
|
|
|
|
|
|
|
|
|
UHF band |
|
- |
9 |
- |
dB |
|
|
|
|
|
|
|
|
Vo |
output voltage causing 1% cross |
VHF band |
|
- |
108 |
- |
dBmV |
|
modulation in channel |
UHF band |
|
- |
108 |
- |
dBmV |
|
|
|
|
|
|
|
|
Notes
1. One buffer ‘ON’, Io = 25 mA; two buffers ‘ON’, maximum sum of Io = 30 mA.
|
|
|
|
|
|
æ1 |
ö 2 |
|
|
|
|
|
|
|
--V33 |
||
2. The power dissipation is calculated as follows: Ptot |
|
VCC ´ (ICC –Io) + VCE(sat PNP) |
´ Io |
è2 |
ø |
|
||
= |
+ ---------------------- |
|
||||||
|
|
|
|
|
|
22 kW |
||
ORDERING INFORMATION |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TYPE NUMBER |
|
|
|
PACKAGE |
|
|
|
|
|
|
|
|
|
|
|
|
|
NAME |
|
|
DESCRIPTION |
|
|
|
VERSION |
|
|
|
|
|
|
|
|||
|
|
|
|
|
||||
TDA6402M; |
SSOP28 |
plastic shrink small outline package; 28 leads; body width 5.3 mm |
|
SOT341-1 |
||||
TDA6402AM |
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
TDA6403M; |
SSOP28 |
plastic shrink small outline package; 28 leads; body width 5.3 mm |
|
SOT341-1 |
||||
TDA6403AM |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2000 Jan 24 |
4 |
Philips Semiconductors Product specification
5 V mixers/oscillators and synthesizers for |
TDA6402; TDA6402A; |
cable TV and VCR 2-band tuners |
TDA6403; TDA6403A |
|
|
BLOCK DIAGRAM |
|
handbook, full pagewidth |
IFFIL1 IFFIL2 |
VCC |
|
|
|
|
5 (24) |
6 (23) |
|
|
19 (10) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(5) 24 |
3 (26) |
|
|
|
|
|
|
|
|
|
|
|
|
|
VHFOSCOC |
VHFIN |
|
RF INPUT |
|
|
|
|
VHF |
|
|
|
|
VHF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
VHF |
|
|
|
MIXER |
|
|
|
OSCILLATOR |
(7) 22 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BS |
|
|
|
BS |
|
|
BS |
|
|
|
|
|
VHFOSCIB |
|
|
|
|
|
|
|
|
|
|
|
(6) 23 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TDA6402 |
|
|
|
|
|
|
|
|
|
|
|
OSCGND |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
4 (25) |
TDA6402A |
|
|
|
|
|
|
|
|
|
IF |
|
(9) 20 |
|
RFGND |
TDA6403 |
|
|
|
|
|
|
|
PREAMPLIFIER |
IFOUT |
||||
|
|
|
|
|
|
|
|
|
||||||
|
TDA6403A |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(1) 28 |
1 (28) |
|
|
|
|
|
|
|
|
|
|
|
|
|
UHFOSCIB2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
(2) 27 |
|
UHFIN1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RF INPUT |
|
|
|
|
UHF |
|
|
|
|
UHF |
|
UHFOSCOC2 |
|
2 (27) |
|
UHF |
|
|
|
MIXER |
|
|
|
OSCILLATOR |
(3) 26 |
|||
UHFIN2 |
|
|
|
|
|
|
|
UHFOSCOC1 |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
BS |
|
|
|
BS |
|
|
BS |
|
|
|
|
|
(4) 25 |
|
|
|
|
|
|
|
|
|
|
|
UHFOSCIB1 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(13) 16 |
18 (11) |
|
XTAL |
|
PRESCALER |
|
|
|
|
|
|
|
|
CP |
|
|
|
fREF |
|
|
|
|
|
|
|
|||||
OSCILLATOR |
|
DIVIDE BY |
|
|
|
|
|
|
|
|||||
XTAL |
|
|
|
|
|
|
|
(12) 17 |
||||||
|
|
4 MHz |
|
512, 640, 1024 |
|
|
|
|
|
|
|
|
VT |
|
|
|
|
|
RSA |
RSB |
|
PHASE |
CHARGE |
|
OPAMP |
|
|
||
|
|
|
|
|
COMPARATOR |
PUMP |
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
PRESCALER |
|
|
15-BIT |
fDIV |
|
|
|
|
|
|
|
||
|
|
PROGRAMMABLE |
|
|
|
|
|
|
|
|||||
|
DIVIDE BY 8 |
|
|
|
|
|
OS |
|
|
|||||
|
|
DIVIDER |
|
|
T0, T1, T2 CP |
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
IN LOCK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DETECTOR |
|
|
|
|
|
|
|
|
POWER-DOWN |
|
|
15-BIT |
|
|
|
|
|
|
|
|
|
|
|
|
FREQUENCY |
|
|
|
|
|
|
|
|
|
|||
|
DETECTOR |
|
|
|
|
CONTROL |
|
|
||||||
|
FL |
REGISTER |
|
FL |
|
|
|
|||||||
|
|
|
|
|
REGISTER |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|||||
14 (15) |
SCL |
|
|
|
|
|
|
|
|
|
|
|
|
|
CL |
|
|
|
|
|
|
CP T2 |
T1 |
T0 RSA RSB OS |
|
||||
13 (16) |
SDA |
I2C / 3-WIRE BUS TRANSCEIVER |
|
|
|
|||||||||
DA |
|
|
|
|
|
|
|
|
|
|||||
11 (18) |
SW |
|
|
|
|
|
fREF |
|
|
|
|
|
|
|
SW |
CE/AS |
|
|
|
|
|
|
PORT |
|
|
|
|||
12 (17) |
|
|
|
|
|
FL |
1/2fDIV |
|
REGISTER |
|
|
|||
|
|
|
|
|
|
|
UHF |
VHFH |
VHFL FMST |
|
||||
CE/AS |
|
|
|
|
|
|
|
|
||||||
|
|
|
3-BIT A/D |
|
|
GATE |
|
|
|
|
|
|
|
|
|
|
CONVERTER |
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
BS |
|
|
|
|
|
(8) 21 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
T0, T1, T2 |
|
|
|
|
|
GND |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
15 (14) |
9 (20) |
8 (21) |
7 (22) |
10 (19) |
|
||
|
|
|
|
|
|
|
|
|
PVHFH |
|
FMST |
MGE692 |
||
|
|
|
|
|
|
LOCK/ADC |
|
|
|
|||||
|
|
|
|
|
|
|
|
PUHF |
|
|
PVHFL |
|
|
|
The pin numbers in parenthesis represent the TDA6403 and TDA6403A.
Fig.1 Block diagram.
2000 Jan 24 |
5 |
Philips Semiconductors Product specification
5 V mixers/oscillators and synthesizers for |
TDA6402; TDA6402A; |
||||
cable TV and VCR 2-band tuners |
TDA6403; TDA6403A |
||||
|
|
|
|
|
|
PINNING |
|
|
|
|
|
|
|
|
|
|
|
|
|
PIN |
|
|
|
SYMBOL |
|
|
|
DESCRIPTION |
|
TDA6402; |
|
TDA6403; |
|||
|
|
|
|
||
|
TDA6402A |
|
TDA6403A |
|
|
|
|
|
|
|
|
UHFIN1 |
1 |
|
28 |
UHF RF input 1 |
|
|
|
|
|
|
|
UHFIN2 |
2 |
|
27 |
UHF RF input 2 |
|
|
|
|
|
|
|
VHFIN |
3 |
|
26 |
VHF RF input |
|
|
|
|
|
|
|
RFGND |
4 |
|
25 |
RF ground |
|
|
|
|
|
|
|
IFFIL1 |
5 |
|
24 |
IF filter output 1 |
|
|
|
|
|
|
|
IFFIL2 |
6 |
|
23 |
IF filter output 2 |
|
|
|
|
|
|
|
PVHFL |
7 |
|
22 |
PNP port output, general purpose (e.g. VHF low sub-band) |
|
|
|
|
|
|
|
PVHFH |
8 |
|
21 |
PNP port output, general purpose (e.g. VHF high sub-band) |
|
|
|
|
|
|
|
PUHF |
9 |
|
20 |
PNP port output, UHF band |
|
|
|
|
|
|
|
FMST |
10 |
|
19 |
PNP port output, general purpose (e.g. FM sound trap) |
|
|
|
|
|
|
|
SW |
11 |
|
18 |
bus mode selection input (I2C-bus/3-wire bus) |
|
CE/AS |
12 |
|
17 |
Chip Enable/Address Selection input |
|
|
|
|
|
|
|
DA |
13 |
|
16 |
serial data input/output |
|
|
|
|
|
|
|
CL |
14 |
|
15 |
serial clock input |
|
|
|
|
|
|
|
LOCK/ADC |
15 |
|
14 |
lock detector output (3-wire bus)/ADC input (I2C-bus) |
|
CP |
16 |
|
13 |
charge pump output |
|
|
|
|
|
|
|
VT |
17 |
|
12 |
tuning voltage output |
|
|
|
|
|
|
|
XTAL |
18 |
|
11 |
crystal oscillator input |
|
|
|
|
|
|
|
VCC |
19 |
|
10 |
supply voltage |
|
IFOUT |
20 |
|
9 |
IF output |
|
|
|
|
|
|
|
GND |
21 |
|
8 |
digital ground |
|
|
|
|
|
|
|
VHFOSCIB |
22 |
|
7 |
VHF oscillator input base |
|
|
|
|
|
|
|
OSCGND |
23 |
|
6 |
oscillator ground |
|
|
|
|
|
|
|
VHFOSCOC |
24 |
|
5 |
VHF oscillator output collector |
|
|
|
|
|
|
|
UHFOSCIB1 |
25 |
|
4 |
UHF oscillator input base 1 |
|
|
|
|
|
|
|
UHFOSCOC1 |
26 |
|
3 |
UHF oscillator output collector 1 |
|
|
|
|
|
|
|
UHFOSCOC2 |
27 |
|
2 |
UHF oscillator output collector 2 |
|
|
|
|
|
|
|
UHFOSCIB2 |
28 |
|
1 |
UHF oscillator input base 2 |
|
|
|
|
|
|
|
2000 Jan 24 |
6 |
Philips Semiconductors |
Product specification |
|
|
5 V mixers/oscillators and synthesizers for |
TDA6402; TDA6402A; |
cable TV and VCR 2-band tuners |
TDA6403; TDA6403A |
|
|
handbook, halfpage |
|
|
|
|
UHFIN1 |
1 |
|
28 |
UHFOSCIB2 |
UHFIN2 |
|
|
|
UHFOSCOC2 |
2 |
|
27 |
||
VHFIN |
3 |
|
|
UHFOSCOC1 |
|
26 |
|||
RFGND |
4 |
|
|
UHFOSCIB1 |
|
25 |
|||
IFFIL1 |
|
|
|
VHFOSCOC |
5 |
|
24 |
||
|
|
|
|
|
IFFIL2 |
6 |
|
23 |
OSCGND |
PVHFL |
|
|
|
VHFOSCIB |
7 |
TDA6402 |
22 |
||
|
|
|
|
|
|
8 |
TDA6402A |
|
|
PVHFH |
21 |
GND |
||
PUHF |
9 |
|
|
IFOUT |
|
20 |
|||
FMST |
10 |
|
|
VCC |
|
19 |
|||
SW |
11 |
|
|
XTAL |
|
18 |
|||
CE/AS |
12 |
|
|
VT |
|
17 |
|||
DA |
13 |
|
|
CP |
|
16 |
|||
|
|
|
|
|
CL |
14 |
|
15 |
LOCK/ADC |
|
|
|
|
|
|
|
MGE690 |
|
|
Fig.2 Pin configuration for TDA6402 and TDA6402A.
handbook, halfpage |
|
|
|
UHFIN1 |
UHFOSCIB2 |
1 |
|
28 |
|
UHFOSCOC2 |
|
|
|
UHFIN2 |
2 |
|
27 |
||
UHFOSCOC1 |
3 |
|
|
VHFIN |
|
26 |
|||
UHFOSCIB1 |
4 |
|
|
RFGND |
|
25 |
|||
VHFOSCOC |
|
|
|
IFFIL1 |
5 |
|
24 |
||
|
|
|
|
|
OSCGND |
6 |
|
23 |
IFFIL2 |
VHFOSCIB |
|
|
|
PVHFL |
7 |
TDA6403 |
22 |
||
|
|
|
|
|
|
8 |
TDA6403A |
|
|
GND |
21 |
PVHFH |
||
IFOUT |
9 |
|
|
PUHF |
|
20 |
|||
VCC |
10 |
|
|
FMST |
|
19 |
|||
XTAL |
11 |
|
|
SW |
|
18 |
|||
VT |
12 |
|
|
CE/AS |
|
17 |
|||
CP |
13 |
|
|
DA |
|
16 |
|||
|
|
|
|
|
LOCK/ADC |
14 |
|
15 |
CL |
|
|
|
|
|
|
|
MGE691 |
|
|
Fig.3 Pin configuration for TDA6403 and TDA6403A.
PLL FUNCTIONAL DESCRIPTION
The device is controlled via the I2C-bus or the 3-wire bus, depending on the voltage applied on the SW input.
A HIGH-level on the SW input enables the 3-wire bus; CE/AS, DA and CL inputs are used as enable (CE), data
and clock inputs respectively. A LOW-level on SW input enables the I2C-bus; the CE/AS, DA and CL inputs are used as address selection (AS), SDA and SCL input respectively (see Table 2).
Table 2 Bus mode selection
|
|
PIN |
|
|
|
SYMBOL |
|
|
|
3-WIRE BUS MODE |
I2C-BUS MODE |
TDA6402; |
|
TDA6403; |
|||
|
|
|
|
||
|
TDA6402A |
|
TDA6403A |
|
|
|
|
|
|
|
|
SW |
11 |
|
18 |
HIGH-level or OPEN |
LOW-level or GND |
|
|
|
|
|
|
CE/AS |
12 |
|
17 |
enable input |
address selection input |
|
|
|
|
|
|
DA |
13 |
|
16 |
data input |
serial data input |
|
|
|
|
|
|
CL |
14 |
|
15 |
clock input |
serial clock input |
|
|
|
|
|
|
LOCK/ADC |
15 |
|
14 |
LOCK/TEST output |
ADC input/TEST output |
|
|
|
|
|
|
2000 Jan 24 |
7 |
Philips Semiconductors |
Product specification |
|
|
5 V mixers/oscillators and synthesizers for |
TDA6402; TDA6402A; |
cable TV and VCR 2-band tuners |
TDA6403; TDA6403A |
|
|
I2C-bus mode (SW = GND)
WRITE MODE; R/W = 0 (see Tables 3 and 4)
Data bytes can be sent to the device after the address transmission (first byte). Four data bytes are needed to fully program the device. The bus transceiver has an auto-increment facility which permits the programming of the device within one single transmission
(address + 4 data bytes).
The device can also be partially programmed providing that the first data byte following the address is divider byte 1 (DB1) or control byte (CB). The bits in the data bytes are defined in Tables 3 and 4. The first bit of the first data byte transmitted indicates whether frequency data (first bit = 0) or control and band-switch data (first bit = 1) will follow. Until an I2C-bus STOP command is sent by the
controller, additional data bytes can be entered without the need to re-address the device. The frequency register is loaded after the 8th clock pulse of the second divider byte (DB2), the control register is loaded after the 8th clock pulse of the control byte (CB) and the band-switch register is loaded after the 8th clock pulse of the band switch byte (BB).
I2C-BUS ADDRESS SELECTION
The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several synthesizers (up to 4) in one system by applying a specific voltage on the CE input. The relationship between MA1 and MA0 and the input voltage applied to the CE input is given in Table 6.
Table 3 I2C-bus data format, ‘write’ mode for the TDA6402 and TDA6403
NAME |
BYTE |
|
|
|
|
BITS |
|
|
|
ACK |
|
|
|
|
|
|
|
|
|
|
|||
MSB |
|
|
|
|
|
|
|
LSB |
|||
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
Address byte |
ADB |
1 |
1 |
0 |
0 |
|
0 |
MA1 |
MA0 |
R/W = 0 |
A |
|
|
|
|
|
|
|
|
|
|
|
|
Divider byte 1 |
DB1 |
0 |
N14 |
N13 |
N12 |
|
N11 |
N10 |
N9 |
N8 |
A |
|
|
|
|
|
|
|
|
|
|
|
|
Divider byte 2 |
DB2 |
N7 |
N6 |
N5 |
N4 |
|
N3 |
N2 |
N1 |
N0 |
A |
|
|
|
|
|
|
|
|
|
|
|
|
Control byte |
CB |
1 |
CP |
T2 |
T1 |
|
T0 |
RSA |
RSB |
OS |
A |
|
|
|
|
|
|
|
|
|
|
|
|
Band-switch byte |
BB |
X |
X |
X |
X |
|
FMST |
PUHF |
PVHFH |
PVHFL |
A |
|
|
|
|
|
|
|
|
|
|
|
|
Table 4 I2C-bus data format, ‘write’ mode for the TDA6402A and TDA6403A |
|
|
|
|
|||||||
NAME |
BYTE |
|
|
|
|
BITS |
|
|
|
ACK |
|
|
|
|
|
|
|
|
|
|
|||
MSB |
|
|
|
|
|
|
|
LSB |
|||
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
Address byte |
ADB |
1 |
1 |
0 |
0 |
|
0 |
MA1 |
MA0 |
R/W = 0 |
A |
|
|
|
|
|
|
|
|
|
|
|
|
Divider byte 1 |
DB1 |
0 |
N14 |
N13 |
N12 |
|
N11 |
N10 |
N9 |
N8 |
A |
|
|
|
|
|
|
|
|
|
|
|
|
Divider byte 2 |
DB2 |
N7 |
N6 |
N5 |
N4 |
|
N3 |
N2 |
N1 |
N0 |
A |
|
|
|
|
|
|
|
|
|
|
|
|
Control byte |
CB |
1 |
CP |
T2 |
T1 |
|
T0 |
RSA |
RSB |
OS |
A |
|
|
|
|
|
|
|
|
|
|
|
|
Band-switch byte |
BB |
X |
X |
X |
X |
|
PUHF |
FMST |
PVHFH |
PVHFL |
A |
|
|
|
|
|
|
|
|
|
|
|
|
2000 Jan 24 |
8 |
Philips Semiconductors Product specification
5 V mixers/oscillators and synthesizers for |
TDA6402; TDA6402A; |
||||
cable TV and VCR 2-band tuners |
TDA6403; TDA6403A |
||||
|
|
|
|
|
|
Table 5 Description of symbols used in Tables 3 and 4 |
|
||||
|
|
|
|
|
|
SYMBOL |
|
|
DESCRIPTION |
||
|
|
|
|
|
|
A |
|
acknowledge |
|
|
|
|
|
|
|
|
|
MA1, MA0 |
|
programmable address bits (see Table 6) |
|
||
|
|
|
|
|
|
N14 to N0 |
|
programmable divider bits; N = N14 ´ 214 + N13 ´ 213 + ... + N1 ´ 21 + N0 |
|||
CP |
|
charge pump current: |
|
||
|
|
|
CP = 0 = 60 mA |
|
|
|
|
|
CP = 1 = 280 mA (default) |
|
|
|
|
|
|
|
|
T2, T1,T0 |
|
test bits (see Table 7) |
|
||
|
|
|
|
|
|
RSA, RSB |
|
reference divider ratio select bits (see Table 8) |
|
||
|
|
|
|
|
|
OS |
|
tuning amplifier control bit: |
|
||
|
|
|
OS = 0; normal operation; tuning voltage is ‘ON’ (default) |
||
|
|
|
OS = 1; tuning voltage is ‘OFF’ (high-impedance) |
||
|
|
|
|
|
|
PVHFL, PVHFH, PUHF, FMST |
PNP ports control bits: |
|
|||
|
|
|
bit = 0; buffer n is ‘OFF’ (default) |
|
|
|
|
|
bit = 1; buffer n is ‘ON’ |
|
|
|
|
|
|
|
|
X |
|
don’t care |
|
|
|
|
|
|
|
|
|
Table 6 Address selection (I2C-bus mode) |
|
|
|||
MA1 |
|
MA0 |
|
VOLTAGE APPLIED ON CE INPUT (SW = GND) |
|
|
|
|
|
|
|
0 |
|
0 |
0 V to 0.1 ´ VCC |
|
|
0 |
|
1 |
open or 0.2 ´ VCC to 0.3 ´ VCC |
|
|
1 |
|
0 |
0.4 ´ VCC to 0.6 ´ VCC |
|
|
1 |
|
1 |
0.9 ´ VCC to 1.0 ´ VCC |
|
|
Table 7 Test modes |
|
|
|
|
|
|
|
|
|
||
T2 |
|
T1 |
T0 |
TEST MODES |
|
|
|
|
|
|
|
0 |
|
0 |
0 |
automatic charge pump switched off |
|
|
|
|
|
|
|
0 |
|
0 |
1 |
automatic charge pump switched on (note 1) |
|
|
|
|
|
|
|
0 |
|
1 |
X |
charge pump is ‘OFF’ |
|
|
|
|
|
|
|
1 |
|
1 |
0 |
charge pump is sinking current |
|
|
|
|
|
|
|
1 |
|
1 |
1 |
charge pump is sourcing current |
|
|
|
|
|
|
|
1 |
|
0 |
0 |
fREF is available on pin LOCK/ADC (note 2) |
|
1 |
|
0 |
1 |
1¤2fDIV is available on pin LOCK/ADC (note 2) |
|
Notes
1.This is the default mode at power-on reset.
2.The ADC input cannot be used when these test modes are active; see Section “Read mode; R/W = 1 (see Table 9)” for more information.
2000 Jan 24 |
9 |
Philips Semiconductors Product specification
5 V mixers/oscillators and synthesizers for |
TDA6402; TDA6402A; |
|||
cable TV and VCR 2-band tuners |
TDA6403; TDA6403A |
|||
|
|
|
|
|
Table 8 Reference divider ratio select bits |
|
|
||
|
|
|
|
|
RSA |
RSB |
|
REFERENCE DIVIDER RATIO |
FREQUENCY STEP (kHz) |
|
|
|
|
|
X(1) |
0 |
|
640 |
6.25 |
0 |
1 |
|
1024 |
3.90625 |
|
|
|
|
|
1 |
1 |
|
512 |
7.8125 |
|
|
|
|
|
Note
1. X = don’t care.
READ MODE; R/W = 1 (see Table 9)
Data can be read from the device by setting the R/W bit to logic 1. After the slave address has been recognized, the device generates an acknowledge pulse and the first data byte (status byte) is transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH-level of the SCL clock signal. A second data byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge). End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the microcontroller to generate a STOP condition.
The POR flag is set to logic 1 at power-on. The flag is reset when an end-of-data is detected by the device (end of a
READ sequence). Control of the loop is made possible with the in-lock flag FL which indicates when the loop is locked (FL = 1).
The automatic charge pump switch flag (ACPS) is LOW when the automatic charge pump switch mode is ‘ON’ and the loop is locked. In other conditions, ACPS = 1.
When ACPS = 0, the charge pump current is forced to the LOW value.
A built-in ADC is available on LOCK/ADC pin (I2C-bus mode only). This converter can be used to apply AFC information to the microcontroller from the IF section of the television. The relationship between the bits A2, A1 and A0 is given in Table 11.
Table 9 Read data format
NAME |
BYTE |
|
|
|
|
|
|
BITS |
|
|
|
ACK |
|
|
|
|
|
|
|
|
|
|
|
|
|||
MSB(1) |
|
|
|
|
|
|
|
|
LSB |
||||
|
|
|
|
|
|
|
|
|
|
|
|||
Address byte |
ADB |
1 |
|
1 |
0 |
|
0 |
|
0 |
MA1 |
MA0 |
R/W = 1 |
A |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Status byte |
SB |
POR |
|
FL |
ACPS |
|
1 |
|
1 |
A2 |
A1 |
A0 |
− |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Note |
|
|
|
|
|
|
|
|
|
|
|
|
|
1. MSB is transmitted first. |
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 10 Description of symbols used in Table 9 |
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|||
SYMBOL |
|
|
|
|
|
DESCRIPTION |
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
||
A |
acknowledge |
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|||||
POR |
power-on reset flag (POR = 1 at power-on) |
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|||||
FL |
in-lock flag (FL = 1 when the loop is locked) |
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|||||
ACPS |
automatic charge pump switch flag: |
|
|
|
|
|
|
|
|||||
|
ACPS = 0; active |
|
|
|
|
|
|
|
|
|
|
||
|
ACPS = 1; not active |
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|||||
A2, A1, A0 |
digital outputs of the 5-level ADC |
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2000 Jan 24 |
10 |
Philips Semiconductors Product specification
5 V mixers/oscillators and synthesizers for |
TDA6402; TDA6402A; |
||||
cable TV and VCR 2-band tuners |
|
TDA6403; TDA6403A |
|||
|
|
|
|
|
|
Table 11 A to D converter levels (note 1) |
|
|
|
||
|
|
|
|
|
|
A2 |
A1 |
|
A0 |
VOLTAGE APPLIED ON ADC INPUT |
|
|
|
|
|
|
|
1 |
0 |
|
0 |
0.60 × VCC to 1.00 × VCC |
|
0 |
1 |
|
1 |
0.45 × VCC to 0.60 × VCC |
|
0 |
1 |
|
0 |
0.30 × VCC to 0.45 × VCC |
|
0 |
0 |
|
1 |
0.15 × VCC to 0.30 × VCC |
|
0 |
0 |
|
0 |
0 to 0.15 × VCC |
|
Note
1. Accuracy is ±0.03 × VCC.
POWER-ON RESET
Table 12 Default bits at power-on reset
NAME |
BYTE |
|
|
|
|
BITS |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
MSB |
|
|
|
|
|
|
|
LSB |
||
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
Address byte |
ADB |
1 |
1 |
0 |
0 |
|
0 |
MA1 |
MA0 |
X |
|
|
|
|
|
|
|
|
|
|
|
Divider byte 1 |
DB1 |
0 |
X |
X |
X |
|
X |
X |
X |
X |
|
|
|
|
|
|
|
|
|
|
|
Divider byte 2 |
DB2 |
X |
X |
X |
X |
|
X |
X |
X |
X |
|
|
|
|
|
|
|
|
|
|
|
Control byte |
CB |
1 |
1 |
0 |
0 |
|
1 |
X |
1 |
1 |
|
|
|
|
|
|
|
|
|
|
|
Band switch byte |
BB |
X |
X |
X |
X |
|
0 |
0 |
0 |
0 |
|
|
|
|
|
|
|
|
|
|
|
The power-on detection threshold voltage VPOR is set to VCC = 2 V at room temperature. Below this threshold, the device is reset to the power-on state.
At power-on state, the charge pump current is set to
280 μA, the tuning voltage output is disabled, the test bits T2, T1 and T0 are set to ‘001’ (automatic charge pump switch ‘ON’) and RSB is set to logic 1.
PUHF is ‘OFF’, which means that the UHF oscillator and the UHF mixer are switched off. Consequently, the VHF oscillator and the VHF mixer are switched on. PVHFL and PVHFH are ‘OFF’, which means that the VHF tank circuit is working in the VHF I sub-band. The tuning amplifier is switched off until the first transmission. In that case, the tank circuit in VHF I is supplied with the maximum tuning voltage. The oscillator is therefore working at the end of the VHF I sub-band.
3-wire bus mode (SW = OPEN or VCC)
During a HIGH-level on the CE input (enable line), the data is clocked into the data register at the HIGH-to-LOW transition of the clock. The first four bits control the PNP ports and are loaded into the internal band switch register on the 5th rising edge of the clock pulse. The frequency
bits are loaded into the frequency register at the HIGH-to-LOW transition of the chip enable line when an 18-bit or 19-bit data word is transmitted (see Figs 4 and 5).
When a 27-bit data word is transmitted, the frequency bits are loaded into the frequency register on the 20th rising edge of the clock pulse and the control bits at the HIGH-to-LOW transition of the chip enable line (see Fig.6). In this mode, the reference divider is given by the RSA and RSB bits (see Table 8). The test bits T2, T1 and T0, the charge pump bit CP, the ratio select bit RSB and the OS bit can only be selected or changed with a 27-bit transmission. They remain programmed if an 18-bit or 19-bit transmission occurs. Only RSA is controlled by the transmission length when the 18-bit or 19-bit format is used. When an 18-bit data word is transmitted, the most significant bit of the divider N14 is internally set to logic 0 and the RSA bit is set to logic 1. When a 19-bit data word is transmitted, the RSA bit is set to logic 0.
A data word of less than 18 bits will not affect the frequency register of the device. The definition of the bits is unchanged compared to I2C-bus mode.
It is not allowed to address the devices with words whose length is different from 18, 19 or 27 bits.
2000 Jan 24 |
11 |
Philips Semiconductors |
Product specification |
|
|
5 V mixers/oscillators and synthesizers for |
TDA6402; TDA6402A; |
cable TV and VCR 2-band tuners |
TDA6403; TDA6403A |
|
|
POWER-ON RESET
The power-on detection threshold voltage VPOR is set to VCC = 2 V at room temperature. Below this threshold, the device is reset to the power-on state.
At power-on state, the charge pump current is set to
280 μA, the tuning voltage output is disabled, the test bits T2, T1 and T0 are set to ‘001’ (automatic charge pump switch ‘ON’) and RSB is set to logic 1.
PUHF is ‘OFF’, which means that the UHF oscillator and the UHF mixer are switched off. Consequently, the VHF oscillator and the VHF mixer are switched on. PVHFL and
PVHFH are ‘OFF’, which means that the VHF tank circuit is working in the VHF I sub-band. The tuning amplifier is switched off until the first transmission. In that case, the tank circuit in VHF I is supplied with the maximum tuning voltage. The oscillator is therefore working at the end of the VHF I sub-band.
If the first sequence transmitted to the device
has 18 or 19 bits, the reference divider ratio is set to 512 or 1024, depending on the sequence length.
If the sequence has 27 bits, the reference divider ratio is fixed by RSA and RSB bits (see Table 8).
INVALID |
BAND SWITCH |
|
|
|
|
|
|
FREQUENCY |
|
|
|
|
|
INVALID |
|
handbook, full pagewidth |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DATA |
DATA |
|
|
|
|
|
|
DATA |
|
|
|
|
|
DATA |
|
|
FMST PVHFL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PUHF PVHFH |
N13 |
N12 |
N11 |
N10 |
N9 |
N8 |
N7 |
N6 |
N5 |
N4 |
N3 |
N2 |
N1 |
N0 |
|
|
|
||||||||||||||
DA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
4 |
5 |
|
|
|
|
|
|
|
|
|
|
|
|
18 |
CL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CE
LOAD BAND SWITCH |
LOAD FREQUENCY |
REGISTER |
REGISTER |
|
MGE693 |
Fig.4 Normal mode; 18-bit data format (RSA = 1).
2000 Jan 24 |
12 |
Loading...