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INTEGRATED CIRCUITS
DATA SHEET
TDA8357J
Full bridge vertical deflection output circuit in LVDMOS
Preliminary specification |
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1999 Nov 10 |
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File under Integrated Circuits, IC02 |
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Philips Semiconductors |
Preliminary specification |
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Full bridge vertical deflection output circuit
TDA8357J
in LVDMOS
FEATURES
∙Few external components required
∙High efficiency fully DC coupled vertical bridge output circuit
∙Vertical flyback switch with short rise and fall times
∙Built-in guard circuit
∙Thermal protection circuit
∙Improved EMC performance due to differential inputs.
QUICK REFERENCE DATA
GENERAL DESCRIPTION
The TDA8357J is a power circuit for use in 90° and 110° colour deflection systems for 25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC contains a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge output circuit allows DC coupling of the deflection coil in combination with single positive supply voltages.
The IC is constructed in a Low Voltage DMOS (LVDMOS) process that combines bipolar, CMOS and DMOS devices. DMOS transistors are used in the output stage because of absence of second breakdown.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Supplies |
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VP |
supply voltage |
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7.5 |
12 |
18 |
V |
VFB |
flyback supply voltage |
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2VP |
45 |
66 |
V |
Iq(P)(av) |
average quiescent supply current |
during scan |
− |
10 |
15 |
mA |
Iq(FB)(av) |
average quiescent flyback supply current |
during scan |
− |
− |
10 |
mA |
Ptot |
total power dissipation |
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− |
− |
8 |
W |
Inputs and outputs |
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Vi(dif)(p-p) |
differential input voltage (peak-to-peak value) |
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− |
1000 |
1500 |
mV |
Io(p-p) |
output current (peak-to-peak value) |
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− |
− |
2.0 |
A |
Flyback switch |
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Io(peak) |
maximum (peak) output current |
t ≤ 1.5 ms |
− |
− |
±1.2 |
A |
Thermal data; in accordance with IEC 747-1 |
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Tstg |
storage temperature |
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−55 |
− |
+150 |
°C |
Tamb |
ambient temperature |
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−25 |
− |
+75 |
°C |
Tj |
junction temperature |
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− |
− |
150 |
°C |
ORDERING INFORMATION
TYPE |
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PACKAGE |
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NUMBER |
NAME |
DESCRIPTION |
VERSION |
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TDA8357J |
DBS9P |
plastic DIL-bent-SIL power package; 9 leads (lead length |
SOT523-1 |
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12/11 mm); exposed die pad |
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1999 Nov 10 |
2 |
Philips Semiconductors |
Preliminary specification |
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Full bridge vertical deflection output circuit
TDA8357J
in LVDMOS
BLOCK DIAGRAM
Vi(p-p)
VI(bias) |
0 |
Vi(p-p) |
VI(bias) |
0 |
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GUARD |
VP |
VFB |
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8 |
3 |
6 |
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GUARD |
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M5 |
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CIRCUIT |
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D2 |
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D3 |
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M2 |
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D1 |
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7 |
OUTA |
INA |
1 |
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M4 |
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INPUT |
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9 |
FEEDB |
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AND |
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FEEDBACK |
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CIRCUIT |
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INB |
2 |
M1 |
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4 |
OUTB |
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M3 |
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TDA8357J |
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5 |
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MGS803 |
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GND |
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Fig.1 Block diagram.
PINNING |
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SYMBOL |
PIN |
DESCRIPTION |
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handbook, halfpage |
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INA |
1 |
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INA |
1 |
input A |
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INB |
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2 |
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INB |
2 |
input B |
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VP |
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3 |
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VP |
3 |
supply voltage |
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OUTB |
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4 |
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OUTB |
4 |
output B |
TDA8357J |
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GND |
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GND |
5 |
ground |
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5 |
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VFB |
6 |
flyback supply voltage |
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VFB |
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6 |
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OUTA |
7 |
output A |
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OUTA |
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7 |
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GUARD |
8 |
guard output |
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GUARD |
8 |
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FEEDB |
9 |
feedback input |
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FEEDB |
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9 |
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MGS804 |
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The exposed die pad is connected to pin GND. |
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Fig.2 |
Pin configuration. |
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1999 Nov 10 |
3 |
Philips Semiconductors |
Preliminary specification |
|
|
Full bridge vertical deflection output circuit
TDA8357J
in LVDMOS
FUNCTIONAL DESCRIPTION
Vertical output stage
The vertical driver circuit has a bridge configuration. The deflection coil is connected between the complimentary driven output amplifiers. The differential
input circuit is voltage driven. The input circuit is specially designed for direct connection to driver circuits delivering a differential signal but it is also suitable for single-ended applications. The output currents of the driver device are converted to voltages by the conversion resistors
RCV1 and RCV2 (see Fig.3) connected to pins INA
and INB. The differential input voltage is compared with the voltage across the measuring resistor RM, providing internal feedback information. The voltage across RM is proportional with the output current. The relationship between the differential input current and the output current is defined by:
2 × Ii(dif)(p-p) × RCV = Io(p-p) × RM
The output current should measure 0.5 to 2.0 A (p-p) and is determined by the value of RM and RCV. The allowable input voltage range is 100 mV to 1.6 V for each input. The formula given does not include internal bondwire resistances. Depending on the values of RM and the internal bondwire resistance (typical value of 50 mΩ) the actual value of the current in the deflection coil will be about 5% lower than calculated.
Flyback supply
The flyback voltage is determined by the flyback supply voltage VFB. The principle of two supply voltages (class G) allows to use an optimum supply voltage VP for scan and an optimum flyback supply voltage VFB for flyback, thus very high efficiency is achieved. The available flyback output voltage across the coil is almost equal to VFB, due to the absence of a coupling capacitor which is not required in a bridge configuration. The very short rise and fall times of the flyback switch are determined mainly by the slew-rate value of more than 300 V/μs.
Protection
The output circuit contains protection circuits for:
∙Too high die temperature
∙Overvoltage of output A.
Guard circuit
A guard circuit with output pin GUARD is provided.
The guard circuit generates a HIGH-level during the flyback period. The guard circuit is also activated for one of the following conditions:
∙During thermal protection (Tj ≈ 170 °C)
∙During an open-loop condition.
The guard signal can be used for blanking the picture tube and signalling fault conditions. The vertical synchronization pulses of the guard signal can be used by an On Screen Display (OSD) microcontroller.
Damping resistor compensation
HF loop stability is achieved by connecting a damping resistor RD1 across the deflection coil. The current values in RD1 during scan and flyback are significantly different. Both the resistor current and the deflection coil current flow into measuring resistor RM, resulting in a too low deflection coil current at the start of the scan.
The difference in the damping resistor current values during scan and flyback have to be externally compensated in order to achieve a short settling time. For that purpose a compensation resistor RCMP in series with a zener diode is connected between pins OUTA and INA (see Fig.4). The zener diode voltage value should be equal to VP. The value of RCMP is calculated by:
(VFB –Vloss(FB) –VZ) × RD1 × RCV1
R = -----------------------------------------------------------------------------------------------------------
CMP (VFB –Vloss(FB) –Icoil(peak) × Rcoil) × RM
where:
∙Vloss(FB) is the voltage loss between pins VFB and OUTA at flyback
∙Rcoil is the deflection coil resistance
∙VZ is the voltage of zener diode D5.
1999 Nov 10 |
4 |
Philips Semiconductors |
Preliminary specification |
|
|
Full bridge vertical deflection output circuit
TDA8357J
in LVDMOS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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VP |
supply voltage |
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− |
18 |
V |
VFB |
flyback supply voltage |
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− |
68 |
V |
Vn |
DC voltage |
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pin OUTA |
note 1 |
− |
68 |
V |
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pin OUTB |
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− |
VP |
V |
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pins INA, INB, GUARD and FEEDB |
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−0.5 |
VP |
V |
In |
DC current |
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pins OUTA and OUTB |
during scan (p-p) |
− |
2.0 |
A |
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pins OUTA and OUTB |
at flyback (peak); t ≤ 1.5 ms |
− |
±1.2 |
A |
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pins INA, INB, GUARD and FEEDB |
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−20 |
+20 |
mA |
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Ilu |
latch-up current |
current into any pin; pin voltage |
− |
+200 |
mA |
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is 1.5 × VP; note 2 |
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current out of any pin; pin voltage |
−200 |
− |
mA |
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is −1.5 × VP; note 2 |
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Ves |
electrostatic handling voltage |
machine model; note 3 |
−300 |
+300 |
V |
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human body model; note 4 |
−2000 |
+2000 |
V |
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Ptot |
total power dissipation |
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− |
8 |
W |
Tstg |
storage temperature |
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−55 |
+150 |
°C |
Tamb |
ambient temperature |
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−25 |
+75 |
°C |
Tj |
junction temperature |
note 5 |
− |
150 |
°C |
Notes
1.When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.
2.At Tj(max).
3.Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.
4.Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.
5.Internally limited by thermal protection at Tj ≈ 170 °C.
THERMAL CHARACTERISTICS
In accordance with IEC 747-1.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Rth(j-c) |
thermal resistance from junction to case |
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− |
− |
6 |
K/W |
Rth(j-a) |
thermal resistance from junction to ambient |
in free air |
− |
− |
65 |
K/W |
1999 Nov 10 |
5 |
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