Philips TDA8006H-C112, TDA8006H-C113, TDA8006H-C111, TDA8006H-C110, TDA8006AH-C218 Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
TDA8006
Multiprotocol IC Card coupler
Product specification |
2000 Feb 21 |
Supersedes data of 1998 Aug 18
File under Integrated Circuits, IC02
Philips Semiconductors |
Product specification |
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Multiprotocol IC Card coupler |
TDA8006 |
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FEATURES
·80C52 core with 16 kbyte ROM and 256 byte RAM
·Extra 1 kbyte RAM outside the core for data storage
·Control and communication through a standard RS232 full duplex interface or a parallel interface
·Specific ISO 7816 UART with parallel access on I/O for automatic convention processing, variable baud rate through frequency or division ratio programming, error management at character level for T = 0, extra guard time register
·VCC generation (5 V ±5% or 3 V ±5%, 65 mA maximum with controlled rise and fall times)
·Card clock generation (up to 10 MHz) with two times synchronous frequency doubling
·Card clock STOP HIGH, clock STOP LOW or 1.25 MHz (from internal oscillator) for card power-down mode
·CLKOUT output for clocking external devices with either
fxtal, 1¤2fxtal or 1¤4fxtal
·Automatic activation and deactivation sequence through an independent sequencer
·Supports the asynchronous protocols T = 0 and T = 1 in accordance with ISO 7816, Europay, Mastercard and Visa (EMV)
·Supports synchronous cards
·Short circuit current limiting
·Special circuitry for killing spikes during power-on or off
·Supply supervisor for power-on/off reset
·Step-up converter (supply voltage from 4.2 to 6 V)
·Power-down and sleep mode for low power consumption
·Enhanced ESD protection on card side (6 kV minimum)
·Software library for easy integration within the application.
ORDERING INFORMATION
APPLICATIONS
·Smart card readers for multiprotocol applications (EMV banking, digital pay TV, access control, etc.).
GENERAL DESCRIPTION
It is assumed that the reader of this data sheet is familiar with ISO 7816.
The TDA8006 is controlled either through a standard serial interface or a parallel bus, it takes care of all ISO 7816, EMV and GSM11.11 requirements. It gives the card and the set a very high level of security due to its special hardware against ESD, short circuit, power failure, etc. Its integrated step-up converter allows operation within a supply voltage range of 4.2 to 6 V.
A special version of the TDA8006 is available which has its internal connections to the controller accessible through external pins. This allows easy development and evaluation when used with a 80CL580 microcontroller or a development tool. An emulation board is available.
A software library has been developed, taking care of all actions required for T = 0, T = 1 and synchronous protocols. This library may be either linked with the application software before masking, or masked in the internal ROM (see “Application Note AN98106”).
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PACKAGE |
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NAME |
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DESCRIPTION |
VERSION |
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TDA8006H/C1 |
QFP64 |
plastic quad flat package; 64 leads (lead length 1.95 mm); |
SOT319-2 |
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body 14 |
´ 20 |
´ 2.8 mm |
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TDA8006H/C2 |
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TDA8006H/C3 |
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TDA8006AH/C1 |
QFP44 |
plastic quad flat package; 44 leads (lead length 1.3 mm); |
SOT307-2 |
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body 10 |
´ 10 |
´ 1.75 mm |
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TDA8006AH/C2 |
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TDA8006AH/C3 |
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2000 Feb 21 |
2 |
Philips Semiconductors |
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Product specification |
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Multiprotocol IC Card coupler |
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TDA8006 |
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QUICK REFERENCE DATA |
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SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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VDD |
supply voltage |
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4.2 |
− |
6 |
V |
IDD(pd) |
supply current in power-down mode |
VDD = 5 V; card inactive; note 1 |
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− |
250 |
μA |
IDD(sm) |
supply current in sleep mode |
card powered but clock stopped; |
− |
− |
1500 |
μA |
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note 1 |
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VCC |
card supply voltage |
including static loads (5 V card) |
4.75 |
5.0 |
5.25 |
V |
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with 40 nAs dynamic loads on |
4.6 |
− |
5.4 |
V |
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100 nF capacitor (5 V card) |
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including static loads (3 V card) |
2.80 |
− |
3.20 |
V |
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with 24 nAs dynamic loads on |
2.75 |
− |
3.25 |
V |
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100 nF capacitor (3 V card) |
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ICC |
card supply current |
operating |
− |
− |
65 |
mA |
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overload detection |
− |
80 |
− |
mA |
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SR |
slew rate (rise and fall) |
maximum load capacitor pin VCC |
0.10 |
0.16 |
0.22 |
V/μs |
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400 nF (including typical 100 nF |
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decoupling) |
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tde |
deactivation cycle duration |
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− |
− |
100 |
μs |
tact |
activation cycle duration |
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− |
− |
225 |
μs |
fxtal |
crystal frequency |
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4 |
− |
25 |
MHz |
foper |
operating frequency |
external frequency applied on |
0 |
− |
25 |
MHz |
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pin XTAL1 |
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Tamb |
operating ambient temperature |
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−25 |
− |
+85 |
°C |
Note
1. IDD in all configurations include the current at pins VDD, VDDA and VDDRAM.
2000 Feb 21 |
3 |
Philips Semiconductors |
Product specification |
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Multiprotocol IC Card coupler |
TDA8006 |
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BLOCK DIAGRAM
VDD |
VDDA |
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100 nF |
100 nF |
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GND |
S1 |
S2 |
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AGND |
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TDA8006H |
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41(28) |
40 (27) |
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29 (19) |
31 |
30 |
28 (18) |
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(21) |
(20) |
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(TDA8006AH) |
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ALARM |
45 (32) |
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SUPPLY |
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STEP-UP |
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CDELAY |
44 (31) |
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AND |
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(22) 32 |
VUP |
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CONVERTER |
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SUPERVISOR |
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100 nF |
RESET |
52 (34) |
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7 (3) |
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PSEN |
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8 (4) |
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(25) 38 |
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ALE |
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P34 |
C4 |
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C4 |
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11 (7) |
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EA |
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61 (41) |
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P36/WR |
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P35 |
C8 |
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(26) 39 |
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62 (42) |
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C8 |
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P37/RD |
MICROCONTROLLER |
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19 to 12 |
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ANALOG |
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(11 to 8)(1) |
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80C52 |
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DRIVERS |
(17) 27 |
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P00 to P07 |
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CLK |
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63, 64, 1 to 6 |
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AND |
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16-kbyte ROM |
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(43, 44, 1, 2)(2) |
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SEQUENCER |
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P20 to P27 |
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256-byte RAM |
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(16) 26 |
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RST |
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P30/RXD |
58 (38) |
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59 (39) |
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P31/TXD |
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60 (40) |
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(23) 36 |
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P33/INT1 |
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VCC |
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53 (35) |
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P10/T2 |
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54 (36) |
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P11/T2EX |
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(24) 37 |
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I/O |
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P40 |
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INT0 |
6 |
8 |
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INTERNAL |
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to P47 |
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PERIPHERALS |
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OSCILLATOR |
(29) 42 |
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PRES |
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VDDRAM |
23 (14) |
1024 |
T = 0,1 |
I/O |
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24 (15) |
AUX |
ISO |
OFF |
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GNDRAM |
RAM |
UART |
3 V/5 V |
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CMDVCC |
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CLKOUT |
43 (30) |
CLOCK CIRCUITRY |
PORT EXTENSION |
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10 (6) |
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9 (5) |
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48 to 51(3) |
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XTAL1 |
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XTAL2 |
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MGR225 |
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K0 to K3 |
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Minimum value for capacitor between VDDA and AGND is 2.2 μF.
Pin numbers in parenthesis represent the TDA8006AH.
(1)Ports P04 to P07 not applicable for QFP44 package.
(2)Ports P24 to P27 not applicable for QFP44 package.
(3)Ports K0 to K3 not applicable for QFP44 package.
Fig.1 Block diagram.
2000 Feb 21 |
4 |
Philips Semiconductors |
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Product specification |
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Multiprotocol IC Card coupler |
TDA8006 |
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PINNING |
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SYMBOL |
PIN |
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DESCRIPTION |
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QFP64 |
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QFP44 |
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P22 |
1 |
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1 |
address 10/general purpose I/O port |
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P23 |
2 |
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address 11/general purpose I/O port |
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P24 |
3 |
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− |
address 12/general purpose I/O port |
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P25 |
4 |
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address 13/general purpose I/O port |
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P26 |
5 |
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address 14/general purpose I/O port |
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P27 |
6 |
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address 15/general purpose I/O port |
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7 |
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3 |
program store enable output |
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PSEN |
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ALE |
8 |
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4 |
address latch enable |
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XTAL2 |
9 |
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5 |
crystal connection |
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XTAL1 |
10 |
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6 |
crystal connection or external clock input |
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11 |
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7 |
external access |
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EA |
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P07 |
12 |
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− |
address/data 7/general purpose I/O port |
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P06 |
13 |
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address/data 6/general purpose I/O port |
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P05 |
14 |
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− |
address/data 5/general purpose I/O port |
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P04 |
15 |
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address/data 4/general purpose I/O port |
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P03 |
16 |
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8 |
address/data 3/general purpose I/O port |
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P02 |
17 |
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9 |
address/data 2/general purpose I/O port |
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P01 |
18 |
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10 |
address/data 1/general purpose I/O port |
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P00 |
19 |
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11 |
address/data 0/general purpose I/O port |
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n.c. |
20 |
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12 |
not connected |
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n.c. |
21 |
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13 |
not connected |
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n.c. |
22 |
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− |
not connected |
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VDDRAM |
23 |
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14 |
supply voltage for the auxiliary RAM |
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GNDRAM |
24 |
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15 |
ground for the auxiliary RAM |
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n.c. |
25 |
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not connected |
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RST |
26 |
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16 |
card reset output (ISO contact C2) |
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CLK |
27 |
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17 |
clock output to the card (ISO contact C3) |
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AGND |
28 |
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18 |
ground for the analog part |
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S1 |
29 |
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19 |
contact 1 for the step-up converter (a ceramic capacitor of 100 nF must be |
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connected between S1 and S2) |
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VDDA |
30 |
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20 |
analog supply voltage for the voltage doubler |
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S2 |
31 |
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21 |
contact 2 for the step-up converter (a ceramic capacitor of 100 nF must be |
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connected between S1 and S2) |
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VUP |
32 |
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22 |
output of the step-up converter; must be decoupled with a 100 nF ceramic |
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capacitor |
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n.c. |
33 |
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− |
not connected |
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n.c. |
34 |
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− |
not connected |
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n.c. |
35 |
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− |
not connected |
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VCC |
36 |
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23 |
card supply output voltage (ISO contact C1) |
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2000 Feb 21 |
5 |
Philips Semiconductors |
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Product specification |
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Multiprotocol IC Card coupler |
TDA8006 |
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SYMBOL |
PIN |
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DESCRIPTION |
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QFP64 |
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QFP44 |
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I/O |
37 |
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24 |
data line to/from the card (ISO contact C7) |
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C4 |
38 |
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25 |
auxiliary I/O for ISO contact C4 (synchronous cards for example) |
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C8 |
39 |
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26 |
auxiliary I/O for ISO contact C8 (synchronous cards for example) |
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GND |
40 |
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27 |
ground |
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VDD |
41 |
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28 |
supply voltage |
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PRES |
42 |
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29 |
card presence contact input (active HIGH or LOW by mask option); see Table 12 |
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CLKOUT |
43 |
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30 |
output for clocking external devices |
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CDELAY |
44 |
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31 |
external capacitor connection for delayed reset signal |
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ALARM |
45 |
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32 |
open drain reset output (active HIGH or LOW by mask option); see Table 12 |
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TEST |
46 |
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33 |
test pin (must be left open-circuit in the application) |
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INHIB |
47 |
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− |
test pin (must be left open-circuit in the application) |
|
|||||
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48 |
|
− |
output port from port extension (±2 mA push-pull) |
|
|
K0 |
|
|||||||||
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49 |
|
− |
output port from port extension (±2 mA push-pull) |
|
|
K1 |
|
|||||||||
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|
50 |
|
− |
output port from port extension (±2 mA push-pull) |
|
|
K2 |
|
|||||||||
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|
51 |
|
− |
output port from port extension (±2 mA push-pull) |
|
|
K3 |
|
|||||||||
|
RESET |
52 |
|
34 |
input for resetting the microcontroller (active HIGH) |
|
|||||
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|||||
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P10/T2 |
53 |
|
35 |
general purpose I/O port (connected to P10) |
|
|||||
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|||||
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P11/T2EX |
54 |
|
36 |
general purpose I/O port (connected to P11) |
|
|||||
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n.c. |
55 |
|
37 |
not connected |
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n.c. |
56 |
|
− |
not connected |
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n.c. |
57 |
|
− |
not connected |
|
|||||
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|||||
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P30/RXD |
58 |
|
38 |
general purpose I/O port or serial interface receive line |
|
|||||
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|||||
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P31/TXD |
59 |
|
39 |
general purpose I/O port or serial interface transmit line |
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60 |
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40 |
general purpose I/O port or interrupt (connected to P33) |
|
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P33/INT1 |
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|||||||
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61 |
|
41 |
general purpose I/O port or external data memory write strobe |
|
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P36/WR |
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|||||||
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62 |
|
42 |
general purpose I/O port or external data memory read strobe |
|
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P37/RD |
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|
|||||||
|
P20 |
63 |
|
43 |
address 8/general purpose I/O port |
|
|||||
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|||||
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P21 |
64 |
|
44 |
address 9/general purpose I/O port |
|
|||||
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|
|
2000 Feb 21 |
6 |
Philips Semiconductors |
Product specification |
|
|
Multiprotocol IC Card coupler |
TDA8006 |
|
|
handbook, full pagewidth
P22 1
P23 2
P24 3
P25 4
P26 5
P27 6
PSEN 7
ALE 8 XTAL2 9
XTAL1 10 EA 11
P07 12
P06 13
P05 14
P04 15
P03 16
P02 17
P01 18
P00 19
P21 |
|
P20 |
|
P37/RD |
|
|
P36/WR |
|
P33/INT1 |
|
P31/TXD |
|
P30/RXD |
|
n.c. |
|
n.c. |
|
n.c. |
|
P11/T2EX |
|
P10/T2 |
|
RESET |
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64 |
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63 |
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62 |
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61 |
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60 |
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59 |
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58 |
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57 |
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56 |
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55 |
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54 |
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53 |
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52 |
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TDA8006H
20 |
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21 |
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22 |
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23 |
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24 |
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25 |
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26 |
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27 |
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28 |
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29 |
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30 |
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31 |
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32 |
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n.c. |
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n.c. |
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n.c. |
|
V |
|
GNDRAM |
|
n.c. |
|
RST |
|
CLK |
|
AGND |
|
S1 |
|
V |
|
S2 |
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VUP |
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DDRAM |
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DDA |
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51 K3
50 K2
49 K1
48 K0
47 INHIB
46 TEST
45 ALARM
44 CDELAY
43 CLKOUT
42 PRES
41 VDD
40 GND
39 C8
38 C4
37 I/O
36 VCC
35 n.c.
34 n.c.
33 n.c.
MGR226
Fig.2 Pin configuration (QFP64).
2000 Feb 21 |
7 |
Philips Semiconductors |
Product specification |
|
|
Multiprotocol IC Card coupler |
TDA8006 |
|
|
handbook, full pagewidth
|
|
|
|
|
|
P21 |
|
P20 |
|
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P37/RD |
|
P36/WR |
|
P33/INT1 |
P31/TXD |
P30/RXD |
n.c. |
P11/T2EX |
P10/T2 |
RESET |
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44 |
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43 |
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42 |
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41 |
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40 |
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39 |
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38 |
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37 |
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36 |
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35 |
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34 |
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P22 |
1 |
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33 |
TEST |
||
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P23 |
2 |
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32 |
ALARM |
||
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PSEN |
3 |
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31 |
CDELAY |
|||
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ALE |
4 |
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30 |
CLKOUT |
||
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XTAL2 |
5 |
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29 |
PRES |
|||
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VDD |
XTAL1 |
6 |
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TDA8006AH |
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28 |
|||||||||||
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GND |
||||||||
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EA |
7 |
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27 |
|||
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P03 |
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C8 |
||
|
8 |
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26 |
||||
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P02 |
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C4 |
||
|
9 |
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25 |
||||
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P01 |
10 |
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24 |
I/O |
||
|
P00 |
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VCC |
||
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11 |
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23 |
||||
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12 |
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13 |
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14 |
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15 |
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16 |
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17 |
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18 |
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19 |
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20 |
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21 |
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22 |
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||||
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n.c. |
|
n.c. |
|
|
DDRAM |
|
GNDRAM |
|
RST |
CLK |
AGND |
S1 |
DDA |
S2 |
VUP |
MGR227 |
|||||||||||
|
|
|
|
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|
|
V |
|
|
V |
|||||||||||||||||||||
Fig.3 Pin configuration (QFP44).
2000 Feb 21 |
8 |
Philips Semiconductors |
Product specification |
|
|
Multiprotocol IC Card coupler |
TDA8006 |
|
|
FUNCTIONAL DESCRIPTION
Microcontroller
The microcontroller is an 80C52 with 16 kbytes of ROM, 256 byte RAM, timers 0, 1, 2 , and 5 I/O ports (port P0: open-drain; ports P1 to P3: weak pull-up). Port P4 is identical to 83CE560, except that precharge circuits ensure fast rise times at end of read mode (transition times <0.5 μs). The ROM code content can be tested by signature to avoid reading it out after masking; for security bit option, see Table 12. The CPU, timers 0 and 1, serial UART, parallel I/O ports, 256 byte RAM, 16 kbyte ROM and external bus are conventional C51 family library elements. Timer 2 is a conventional C52 element (interrupt enable bit ET2: bit 3 in register IEN1 at byte address E8H and interrupt priority bit PT2: bit 3 in register IP1 at byte address F8H.
Register PCON has an added feature: PCON.5 = RFI (reduced Radio Frequency Interference bit). When set to logic 1, pin ALE cannot be toggled. ALE clears on RESET.
If access is required to the external data memory via MOVX instructions (see Table 1), set bit PCON.6 = ARD in the PCON register to logic 1.
For further information, please refer to the published specification of the 83CE560 in “Data Handbook IC20; 80C51-Based 8-Bit Microcontrollers”.
Ports P40 to P47, INT0 and P12 to P17 are used internally for controlling the smart card interface and the other peripherals. Ports P34 and P35 are used to control the auxiliary contacts C4 and C8.
The list of differences given in Table 1 may help the software developer of the dedicated emulation board for the TDA8006 or other devices.
Table 1 List of differences between TDA8006, CE560, CL580 and C52
FEATURES |
TDA8006 |
|
|
83CE560 |
|
CL580 |
INTEL C52 |
|||||||||
|
|
|
|
|
||||||||||||
P4 address |
C0 |
C0 |
C1 |
no |
||||||||||||
|
|
|
|
|
|
|||||||||||
Timer 2 |
Intel |
|
Philips |
Intel |
Intel |
|||||||||||
|
|
|
|
|
||||||||||||
ROM size |
16 kbytes |
64 kbytes |
6 kbytes |
8 kbytes |
||||||||||||
|
|
|
|
|
|
|||||||||||
External 0 interrupt vector |
0003H |
|
0003H |
0003H |
0003H |
|||||||||||
|
|
|
|
|
|
|||||||||||
External 0 interrupt priority |
highest (1st) |
|
highest (1st) |
highest (1st) |
highest (1st) |
|||||||||||
|
|
|
|
|
|
|||||||||||
Timer 0 interrupt vector |
000BH |
|
000BH |
000BH |
000BH |
|||||||||||
|
|
|
|
|
|
|||||||||||
Timer 0 interrupt priority |
2nd |
|
2nd |
4th |
2nd |
|||||||||||
|
|
|
|
|
|
|||||||||||
External 1 interrupt vector |
0013H |
|
0013H |
0013H |
0013H |
|||||||||||
|
|
|
|
|
||||||||||||
External 1 interrupt priority |
3th |
3th |
7th |
3th |
||||||||||||
|
|
|
|
|
|
|||||||||||
Timer 1 interrupt vector |
001BH |
|
001BH |
001BH |
001BH |
|||||||||||
|
|
|
|
|
|
|||||||||||
Timer 1 interrupt priority |
4th |
|
4th |
10th |
4th |
|||||||||||
|
|
|
|
|
|
|||||||||||
Serial 0 interrupt vector |
0023H |
|
0023H |
0023H |
0023H |
|||||||||||
|
|
|
|
|
|
|||||||||||
Serial 0 interrupt priority |
5th |
|
5th |
13th |
5th |
|||||||||||
|
|
|
|
|
|
|||||||||||
Timer 2 interrupt vector |
004BH |
|
0033H, etc. (8) |
0033H |
002BH |
|||||||||||
|
|
|
|
|
|
|||||||||||
Timer 2 interrupt priority |
lowest (6th) |
|
miscellaneous |
5th |
lowest (6th) |
|||||||||||
|
|
|
|
|
||||||||||||
I2C-bus |
no |
yes |
yes |
no |
||||||||||||
ADC |
no |
yes |
yes |
no |
||||||||||||
|
|
|
|
|
|
|||||||||||
32 kHz oscillator |
no |
|
yes |
no |
no |
|||||||||||
|
|
|
|
|
||||||||||||
PWM |
no |
yes |
yes |
no |
||||||||||||
|
|
|
|
|
|
|||||||||||
Watchdog |
no |
|
yes |
yes |
no |
|||||||||||
|
|
|
|
|
|
|||||||||||
Interrupts on P1 |
no |
|
no |
yes |
no |
|||||||||||
|
|
|
|
|
|
|||||||||||
Additional RAM |
1 kbyte peripheral |
|
2 kbyte MOVX |
no |
no |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Wake-up from |
reset, |
|
|
|
|
reset, |
|
|
reset, |
|
to |
|
|
reset |
||
INT0, |
INT1 |
INT0, |
INT2 |
INT8 |
||||||||||||
power-down mode |
|
|
|
|
|
|
INT1 |
+ other |
|
|
|
|
|
|
||
2000 Feb 21 |
9 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
Product specification |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
Multiprotocol IC Card coupler |
|
|
|
|
|
|
TDA8006 |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 2 Special function register bit addresses |
|
|
|
|
|
|
|
|
||||
X = don’t care. |
|
|
|
|
|
|
|
|
|
|
|
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BYTE |
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BIT ADDRESS [HEX] |
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BIT RESET |
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REGISTER |
ADDRESS |
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BIT FUNCTION |
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VALUE |
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(HEX) |
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MSB |
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LSB |
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IP1 |
F8 |
[FF] |
[FE] |
[FD] |
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[FC] |
[FB] |
[FA] |
[F9] |
[F8] |
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− |
− |
− |
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− |
PT2 |
− |
− |
− |
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XXXX 0XXX |
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B |
F0 |
[F7] |
[F6] |
[F5] |
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[F4] |
[F3] |
[F2] |
[F1] |
[F0] |
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− |
− |
− |
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− |
− |
− |
− |
− |
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0000 0000 |
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IEN1 |
E8 |
[EF] |
[EE] |
[ED] |
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[EC] |
[EB] |
[EA] |
[E9] |
[E8] |
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− |
− |
− |
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− |
ET2 |
− |
− |
− |
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0000 0000 |
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ACC |
E0 |
[E7] |
[E6] |
[E5] |
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[E4] |
[E3] |
[E2] |
[E1] |
[E0] |
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− |
− |
− |
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− |
− |
− |
− |
− |
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0000 0000 |
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PSW |
D0 |
[D7] |
[D6] |
[D5] |
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[D4] |
[D3] |
[D2] |
[D1] |
[D0] |
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CY |
AC |
F0 |
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RS1 |
RS0 |
OV |
F1 |
P |
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0000 0000 |
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T2CON |
C8 |
[CF] |
[CE] |
[CD] |
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[CC] |
[CB] |
[CA] |
[C9] |
[C8] |
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TF2 |
EXF2 |
RCLK |
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TCLK |
EXEN2 |
TR2 |
C/T2N |
CP/RL2N |
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0000 0000 |
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P4 |
C0 |
[C7] |
[C6] |
[C5] |
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[C4] |
[C3] |
[C2] |
[C1] |
[C0] |
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− |
− |
− |
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− |
− |
− |
− |
− |
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1111 1111 |
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IP0 |
B8 |
[BF] |
[BE] |
[BD] |
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[BC] |
[BB] |
[BA] |
[B9] |
[B8] |
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− |
− |
− |
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PS0 |
PT1 |
PX1 |
PT0 |
PX0 |
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XXX0 0000 |
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P3 |
B0 |
[B7] |
[B6] |
[B5] |
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[B4] |
[B3] |
[B2] |
[B1] |
[B0] |
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− |
− |
− |
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− |
− |
− |
− |
− |
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1111 1111 |
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IEN0 |
A8 |
[AF] |
[AE] |
[AD] |
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[AC] |
[AB] |
[AA] |
[A9] |
[A8] |
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EA |
− |
− |
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ES0 |
ET1 |
EX1 |
ET0 |
EX0 |
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0XX0 0000 |
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P2 |
A0 |
[A7] |
[A6] |
[A5] |
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[A4] |
[A3] |
[A2] |
[A1] |
[A0] |
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− |
− |
− |
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− |
− |
− |
− |
− |
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1111 1111 |
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SCON |
98 |
[9F] |
[9E] |
[9D] |
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[9C] |
[9B] |
[9A] |
[99] |
[98] |
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SM0 |
SM1 |
SM2 |
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REN |
TB8 |
RB8 |
TI |
RI |
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0000 0000 |
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P1 |
90 |
[97] |
[96] |
[95] |
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[94] |
[93] |
[92] |
[91] |
[90] |
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− |
− |
− |
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− |
− |
− |
− |
− |
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1111 1111 |
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TCON |
88 |
[8F] |
[8E] |
[8D] |
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[8C] |
[8B] |
[8A] |
[89] |
[88] |
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TF1 |
TR1 |
TF0 |
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TR0 |
IE1 |
IT1 |
IE0 |
IT0 |
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0000 0000 |
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P0 |
80 |
[87] |
[86] |
[85] |
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[84] |
[83] |
[82] |
[81] |
[80] |
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− |
− |
− |
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− |
− |
− |
− |
− |
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1111 1111 |
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2000 Feb 21 |
10 |
Philips Semiconductors |
Product specification |
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Multiprotocol IC Card coupler |
TDA8006 |
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Table 3 Other register byte addresses
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BYTE |
BIT RESET |
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REGISTER |
ADDRESS |
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VALUE |
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(HEX) |
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SP |
81 |
0000 0111 |
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DPL |
82 |
0000 0000 |
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DPH |
83 |
0000 0000 |
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PCON |
87 |
0000 0000 |
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TMOD |
89 |
0000 0000 |
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TL0 |
8A |
0000 0000 |
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TL1 |
8B |
0000 0000 |
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TH0 |
8C |
0000 0000 |
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TH1 |
8D |
0000 0000 |
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S0BUF |
99 |
XXXX XXXX |
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RCAP2L |
CA |
0000 0000 |
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RCAP2H |
CB |
0000 0000 |
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TL2 |
CC |
0000 0000 |
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TH2 |
CD |
0000 0000 |
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Supply
The circuit operates within a supply voltage range of
4.2 to 6 V. The supply pins are VDD, VDDA, GND, AGND, VDDRAM and GNDRAM. Pins VDDA and AGND supply the card analog drivers and have to be externally decoupled
because of the large current spikes that the card and the
step-up converter can create. VDDRAM and GNDRAM supply the auxiliary RAM and should be decoupled
separately. VDD and GND supply the rest of the chip.
An integrated spike killer ensures the contacts to the card remain inactive during power-up or power-down.
An internally generated voltage reference is used by the step-up converter, the voltage supervisor and the VCC generator.
If VDD is too low to ensure proper operation, the voltage supervisor generates an alarm pulse, whose length is defined by an external capacitor tied to the CDELAY pin, (1 ms per 1 nF typical). This pulse is used to reset the controller and is used in parallel with an external reset input which can come from the system controller. It is also used to either block any spurious on-card contacts during a controller reset or to force an automatic deactivation of the contacts in the event of supply drop-out (see Sections “Activation sequence” and “Deactivation sequence”). It is also fed to an external open-drain output (called ALARM) which can be chosen active HIGH or LOW by mask option (see Table 12).
Step-up converter
Except for the VCC generator and the other card contact
buffers, the whole circuit is powered by VDD, VDDA and VDDRAM. If the supply voltage is 4.2 V, then a higher voltage is needed for the supply to the ISO contacts. When
a card session is requested by the controller, the sequencer first starts the step-up converter. This uses switched capacitors which are clocked at a frequency of approximately 2.5 MHz by an internal oscillator.
The output voltage VUP is regulated at approximately 6 V and then fed to the VCC generator. VCC and GND are used as a reference for all other card contacts.
VDD |
Vth(VDD) |
CDELAY |
Vth(CDELAY) |
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ALARM |
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tW |
MGR228 |
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Fig.4 |
Voltage supervisor. |
2000 Feb 21 |
11 |
Philips Semiconductors |
|
Product specification |
|
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|
Multiprotocol IC Card coupler |
|
TDA8006 |
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ISO 7816 security
The correct sequence during activation and deactivation of the card is ensured by a specific sequencer clocked at a frequency which is a division ratio of the internal oscillator.
Activation (bit CMDVCC within the ports extension register HIGH) is only possible if the card is present (pin PRES HIGH or LOW according to the mask option) and if the supply voltage is correct (ALARM signal inactive).
The presence of the card is signalled to the controller by the OFF bit (within the UART status register), generating an interrupt, if enabled, when toggling.
During a session, the sequencer performs an automatic emergency deactivation in the event of card take-off, supply voltage drop or short circuit. The OFF bit goes LOW, thereby warning the controller through the interrupt line INT0 and the status register.
Peripheral interface (see Figs 5 and 6)
This block allows parallel communication with the four peripherals (ISO 7816 UART, clock generator, on/off sequencer and auxiliary RAM) through an 8-bit data bus, 6-bit address and control bus and one interrupt line to the controller. The data bus consists of ports P40 (data bit 0) to P47 (data bit 7). The address bus consists of ports AD0 (P12), AD1 (P13), AD2 (P14) and AD3 (P15). The control lines are R/W (P16) and EN (P17). The interrupt line is INT0.
During a read operation, EN goes LOW allowing the controller to read data on the bus. During a write operation, the data should be present on the bus before asserting EN LOW which allows the data to be written to the registers.
After resetting EN HIGH, the controller must release the bus by setting port P4 HIGH again (the transition times on port P4 are less than 500 ns).
The interrupt line is reset HIGH when reading out the status register.
READ OPERATION
∙Set port P4 to FFH
∙Select the register with AD0, AD1, AD2, AD3
∙Assert R/W HIGH
∙Assert EN LOW; the data is available on data bus P4
∙Read the data on port P4
∙Set EN HIGH; the bus is set to high impedance.
WRITE OPERATION
∙Select the correct register with AD0, AD1, AD2, AD3
∙Assert R/W LOW
∙Write data to the data bus port P4
∙Assert EN LOW; the data is written to the register
∙Set EN HIGH
∙Set port P4 to FFH; the bus is set to high impedance.
Integrated precharges allow fast rising edges on port P4 when changing from read mode to write mode, thus avoiding the need to trigger the active pull-ups on port P4.
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P4 |
XX |
FF |
DATA |
FF |
DATA |
FF |
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R/W |
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AD0 to AD3 |
X |
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AD |
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AD |
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EN |
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read data cycle |
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write data cycle |
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MGR229
Fig.5 Use of peripheral interface.
2000 Feb 21 |
12 |
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