Philips TDA8786G-C2-S1, TDA8786G-C2, TDA8786G-C1-R5, TDA8786G-C1-S1, TDA8786G-C1 Datasheet

DATA SH EET

Product specification
Supersedes data of 1997 May 20
File under Integrated Circuits, IC02

1997 Nov 17

INTEGRATED CIRCUITS

TDA8786; TDA8786A

10-bit analog-to-digital interface for
CCD cameras

1997 Nov 17 2

Philips Semiconductors Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

FEATURES

• Correlated Double Sampling (CDS), AGC, soft clipper,
pre-blanking, 10-bit ADC and reference regulator
included

• Fully programmable via a 3-wire serial interface

• Sampling frequency up to 18 MHz

• AGC gain from 3.5 to 33.5 dB (in 0.1 dB steps)

• Programmable soft clipper for white compression

(starting at 40% of the input signal)

• Standby mode available for each block for power saving
applications (19 mW)

• 6 dB fixed gain analog output for analog iris control

• 8-bit and 10-bit DAC included for analog settings

• Low power consumption of only 475 mW (typ.)

• 5 V operation and 2.5 to 5 V operation for the digital

outputs

• CDS control pulse: TDA8786 = HIGH;
TDA8786A = LOW

• TTL compatible inputs, TTL and CMOS compatible
outputs.

GENERAL DESCRIPTION

The TDA8786; TDA8786A is a 10-bit analog-to-digital
interface for CCD cameras. The device includes a
correlated double sampling circuit, AGC, a soft clipper
circuit and a low power 10-bit Analog-to-Digital Converter
(ADC) together with its reference voltage regulator.

The AGC and soft clipper circuits are controlled by on-chip
DACs via a serial interface.

A 10-bit DAC controls the ADC input clamp level.
A pre-blanking function is also included.
An additional DAC is provided for additional system

controls; its output voltage range is 1.4 V (p-p) which is
available at pin OFDOUT.

APPLICATIONS

• CCD camera systems.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 4.5 4.75 5.5 V

V

CCD

digital supply voltage 4.5 4.75 5.5 V

V

CCO

digital outputs supply voltage 2.5 2.6 5.5 V

I

CCA

analog supply current − 83 − mA

I

CCD

digital supply current − 16 − mA

I

CCO

digital outputs supply current f

CLK

= 18 MHz;

CL= 20 pF; ramp input

− 1 − mA

ADC

res

ADC resolution − 10 − bits

V

i(CDS)(p-p)

CDS input voltage (peak-to-peak value) − 400 1200 mV

G

CDS

CDS output amplifier gain − 6 − dB

f

CLK(max)

maximum clock frequency 18 −−MHz

AGC

dyn

AGC dynamic range − 30 − dB

N

tot(rms)

total noise from CDS input to ADC
output (RMS value)

gain = 3.5 dB − 0.5 − LSB

P

tot

total power consumption − 475 − mW

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8786G

LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

TDA8786AG

1997 Nov 17 3

Philips Semiconductors Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGE361

SOFT

CLIPPER

OPTICAL

BLACK
CLAMP

TRACK-

AND-HOLD

TRACK-

AND-HOLD

TRACK-

AND-HOLD

TRACK-

AND-HOLD

TRACK-

AND-HOLD

CLAMP

ref2

ref1

CLAMP

CLAMP

8-BIT DAC

4-BIT DAC

10-BIT DAC

9-BIT DAC

+

6 dB

AGC

CLOCK

GENERATOR

10-BIT ADC

REGULATOR

SERIAL

INTERFACE

OUTPUTS

BUFFER

5

4

1

1

2

7

8

6

9
10

14

11

12

13 15 16 17 18

20

21

22

23

24

36

3

25

26

27

28

29

30

31

32

33

34

35

3738394041424344

454846

47

IN2

IN1 AGND3

V

CCA3

CDSP2 CDSP1 CLPCDS CLK

DGND2

V

CCD2

OE

V

CCO

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0
DGND1
OFDOUT

OGND

V

CCD1

STDBY

SEN

SCLK

SDATA

DEC1

V

RT

V

RB

V

CCA2

DACOUT

V

ref

CLPADC

AGND2

ADCIN

PBOUT

V

CCA1

PBIN

AGCOUT

PBK

CLPOPB

AGND1

19

STGE

AMPOUT

TDA8786

TDA8786A

1

1997 Nov 17 4

Philips Semiconductors Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

PINNING

SYMBOL PIN DESCRIPTION

CLPOPB 1 optical black clamp control pulse input (active HIGH for TDA8786, active LOW for TDA8786A)
PBK 2 pre-blanking control pulse input; if PBK is HIGH (LOW) the signal is replaced by the optical

black level for TDA8786 (TDA8786A)
OFDOUT 3 analog output of the additional 8-bit control DAC (controlled via the serial interface)
AMPOUT 4 CDS amplifier output (fixed gain = +6 dB)
AGND1 5 analog ground 1
V

CCA1

6 analog supply voltage 1
AGCOUT 7 AGC and soft clipper amplifier signal output
PBIN 8 optical black clamp and pre-blanking block signal input (from AGCOUT via a capacitor)
PBOUT 9 optical black clamp and pre-blanking block signal output
ADCIN 10 ADC analog signal input (from PBOUT or AGCOUT via a capacitor)
CLPADC 11 clamp control input for ADC analog input signal clamp (active HIGH for TDA8786 and active

LOW for TDA8786A)

V

ref

12 ADC input clamp reference voltage (normally connected to pin VRB or DACOUT)
DACOUT 13 DAC output for ADC clamp level
AGND2 14 analog ground 2
V

CCA2

15 analog supply voltage 2
V

RB

16 ADC reference voltage (BOTTOM) code 0
V

RT

17 ADC reference voltage (TOP) code 1023
DEC1 18 decoupling 1 (decoupled to ground via a capacitor)
STGE 19 CDS offset storage
SDATA 20 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 4-bit DAC for soft clipper;

additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the stand-by

mode per block; see Table 1)
SCLK 21 serial clock input for the control DACs and their serial interface; see Table 1
SEN 22 enable input for the serial interface shift register (active when SEN = logic 0); see Table 1
STDBY 23 stand-by control pin (active HIGH); all the output bits are logic 0 when stand-by is enabled
V

CCD1

24 digital supply voltage 1
DGND1 25 digital ground1
D0 26 ADC digital output 0 (LSB)
D1 27 ADC digital output 1
D2 28 ADC digital output 2
D3 29 ADC digital output 3
D4 30 ADC digital output 4
D5 31 ADC digital output 5
D6 32 ADC digital output 6
D7 33 ADC digital output 7
D8 34 ADC digital output 8
D9 35 ADC digital output 9 (MSB)
OGND 36 digital output ground

1997 Nov 17 5

Philips Semiconductors Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

V

CCO

37 digital output supply voltage
OE 38 output enable (LOW: digital outputs active; HIGH: digital outputs high impedance)
V

CCD2

39 digital supply voltage 2
DGND2 40 digital ground2
CLK 41 ADC clock input
CLPCDS 42 CDS clamp control input (active HIGH for TDA8786; active LOW for TDA8786A)
CDSP1 43 CDS control pulse input 1 (active HIGH for TDA8786; active LOW for TDA8786A)
CDSP2 44 CDS control pulse input 2 (active HIGH for TDA8786; active LOW for TDA8786A)
V

CCA3

45 analog supply voltage 3
IN1 46 input signal 1 from CCD (usually black channel)
IN2 47 input signal 2 from CCD (usually video channel)
AGND3 48 analog ground 3

SYMBOL PIN DESCRIPTION

Fig.2 Pin configuration.

1
2
3
4
5
6
7
8

9
10
11

36
35
34
33
32
31
30
29
28
27
26

13

14

15

16

17

18

19

20

21

22

23

48

47

46

45

44

43

42

41

40

39

38

12

24 37

25

TDA8786

TDA8786A

MGE360

OGND
D9
D8
D7

D5
D4
D3
D2
D1
D0
DGND1

CLPOPB

PBK
OFDOUT
AMPOUT

AGND1
V

CCA1

PBIN

PBOUT

CLPADC

V

ref

D6

IN2

IN1

V

CCA3

CDSP2

CDSP1

CLPCDS

DGND2

V

CCD2

OE

V

CCO

AGND3

CLK

AGCOUT

ADCIN

AGND2

V

CCA2

V

RB

V

RT

DEC1

STGE

SDATA

SEN

STDBY

V

CCD1

DACOUT

SCLK

1997 Nov 17 6

Philips Semiconductors Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

CCA

, V

CCD

and V

CCO

may have any value between −0.3 and +7.0 V provided that the supply

voltage difference ∆VCC remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage note 1 −0.3 +7.0 V

V

CCD

digital supply voltage note 1 −0.3 +7.0 V

V

CCO

output stages supply voltage note 1 −0.3 +7.0 V

∆V

CC

supply voltage difference

between V

CCA

and V

CCD

−1.0 +1.0 V

between V

CCA

and V

CCO

−1.0 +4.0 V

between V

CCD

and V

CCO

−1.0 +4.0 V

V

i

input voltage referenced to V

SSA

−0.3 +7.0 V

V

CLK(p-p)

AC input voltage for switching
(peak-to peak-value)

referenced to V

SSD

− V

CCD

V

I

o

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature −20 +75 °C

T

j

junction temperature − 150 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 76 K/W

1997 Nov 17 7

Philips Semiconductors Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

CHARACTERISTICS

V

CCA=VCCD

= 4.75 V; V

CCO

= 2.6 V; f

CLK

= 18 MHz; T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

analog supply voltage 4.5 4.75 5.5 V

V

CCD

digital supply voltage 4.5 4.75 5.5 V

V

CCO

digital outputs supply
voltage

2.5 2.6 5.5 V

I

CCA

analog supply current − 83 − mA

I

CCD

digital supply current − 16 − mA

I

CCO

digital outputs supply
current

CL= 20 pF on all data
outputs; ramp input

− 1 − mA

Digital inputs

C

LOCK INPUT: CLK (REFERENCED TO DGND)

V

IL

LOW-level input voltage 0 − 0.8 V

V

IH

HIGH-level input voltage 2.0 − V

CCD

V

I

IL

LOW-level input current V

CLK

= 0.8 V −1 − +1 µA

I

IH

HIGH-level input current V

CLK

= 2.0 V −−20 µA

Z

i

input impedance f

CLK

= 18 MHz − 2 − kΩ

C

i

input capacitance f

CLK

= 18 MHz − 2 − pF
INPUTS: CDSP1 AND CDSP2
V

IL

LOW-level input voltage 0 − 0.6 V

V

IH

HIGH-level input voltage 2.2 − V

CCD

V

I

IL

LOW-level input current VIL= 0.6 V −−100 −µA

I

IH

HIGH-level input current VIH= 2.2 V − 0 −µA
INPUTS: SEN, STDBY, CLPCDS, CLPOPB, PBK AND CLPADC
V

IL

LOW-level input voltage 0 − 0.6 V
V

IH

HIGH-level input voltage 2.2 − V

CCD

V

I

i

input current −2 − +2 µA
INPUTS: SEN, SDATA AND SCLK (see Fig.14)
t

su1

SEN set-up time compared

to SCLK rising edge

− 4 − ns

t

su2

SDATA set-up time

compared to SCLK rising

edge

− 4 − ns

t

su3

SEN set-up time compared

to SCLK falling edge

− 4 − ns

t

hd3

SEN hold time compared

to SCLK rising edge

− 4 − ns

t

hd4

SDATA hold time

compared to SCLK rising

edge

− 4 − ns

1997 Nov 17 8

Philips Semiconductors Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

Correlated Double Sampling; CDS

V

i(CDS)(p-p)

CDS input amplitude

(peak-to-peak value)

− 400 1200 mV

I

STGE,IN1,IN2

input current pins 19, 46

and 47

−2 − +2 µA

t

CDS(min)

CDS control pulses

minimum active time

(HIGH for TDA8786,

LOW for TDA8786A)

f

i(CDS1,2)=fCLK(pix)

V

i(CDS)(p-p)

= 1200 mV
black-to-white transition in
one pixel (±1 LSB typ.)

12 −−ns

t

hd1

hold time IN1 compared to
control pulse CDSP1

see Fig.15 − 1 − ns

t

hd2

hold time of IN2 compared
to control pulse CDSP2

see Fig.15 −−0.5 − ns

Amplifier outputs

G

AMPOUT

output amplifier gain − 6 − dB

Z

AMPOUT

output amplifier
impedance

− 300 −Ω

V

AMPOUT(p-p)

output amplifier dynamic
voltage level
(peak-to-peak value)

− 2.4 − V

V

AMPOUT(bl)

output amplifier black
level voltage

− 1.1 − V

V

AGCOUT(p-p)

AGC output amplifier
dynamic voltage level
(peak-to-peak value)

− 1800 − mV

V

AGCOUT

AGC output amplifier black
level voltage

− 1.1 − V

Z

AGCOUT

AGC output amplifier
output impedance

at 10 kHz − 5 −Ω

I

AGCOUT

AGC output static drive
current

static −−1mA

V

OPB(p-p)

optical black clamp and
blanking block output
dynamic voltage
(peak-to-peak value)

− 1.8 − V

V

OPB

optical black clamp and
blanking block output black
level voltage

− 1.4 − V

Z

OPB

optical black clamp and
blanking block output
impedance

at 10 kHz −−5Ω

I

OPB

OPB output current drive static −−1mA

I

PBIN

input current pin 8 −2 − +2 µA

G

AGC(min)

minimum gain of AGC
circuit

AGC DAC input code = 00
(9-bit control)

− 3.5 − dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Nov 17 9

Philips Semiconductors Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

G

AGC(max)

maximum gain of AGC
circuit

AGC DAC input
code = ≥319 (9-bit control)

− 33.5 − dB

V

AGCOUT

AGC output amplifier black
level voltage

− 1.1 − V

V

inflex(p-p)

voltage at soft clipper
inflexion point
(peak-to-peak value)

soft clipper 4-bit control
DAC input code = 00

− 40%
V

AGCOUT(p-p)

− V

soft clipper 4-bit control
DAC input code = 15

− 100%
V

AGCOUT(p-p)

− V

CR

sc

soft clipper compression
ratio

V

i(sc)<Vinflex

− 1.0 −

V

i(sc)>Vinflex

− 0.66 −

CLAMPS

g

mADC

ADC clamps
transconductance

at clamp level − 60 − mS

g

mPBK

PBK clamp
transconductance

at clamp level − 60 − mS

g

mCDS

CDS clamps
transconductance

at clamp level − 5.5 − mS

V

PBIN(clamp)

clamp voltage
at PBIN input

− 1.4 − V

Analog-to-Digital Converter; ADC

f

CLK(max)

maximum clock frequency 18 −−MHz

t

CPH

clock pulse width HIGH 15 −−ns

t

CPL

clock pulse width LOW 15 −−ns

SR

CLK

clock input slew rate
(rising and falling edge)

10 to 90% 0.5 −−V/ns

V

i(ADC)(p-p)

ADC input voltage level
(peak-to-peak value)

− 1.8 − V

V

RB

ADC reference voltage
output code 0

− 1.4 − V

V

RT

ADC reference voltage
output code 1023

− 3.2 − V

I

ADCIN

input current pin 10 −2 − +2 µA

ILE integral linearity error f

CLK

= 18 MHz; ramp input −±1.0 ±2.0 LSB

DLE differential linearity error f

CLK

= 18 MHz; ramp input −±0.4 ±0.75 LSB

t

d(s)

sampling delay time −−5ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT