INTEGRATED CIRCUITS
DATA SHEET
TDA8763
10-bit high-speed low-power ADC with internal reference regulator
Product specification |
1999 Jan 06 |
Supersedes data of 1997 Feb 10
File under Integrated Circuits, IC02
Philips Semiconductors |
Product specification |
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10-bit high-speed low-power ADC with
TDA8763
internal reference regulator
FEATURES
∙10-bit resolution
∙Sampling rate up to 50 MHz
∙DC sampling allowed
∙One clock cycle conversion only
∙High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz)
∙No missing codes guaranteed
∙In-Range (IR) CMOS output
∙Levels TTL and CMOS compatible digital inputs
∙3 to 5 V CMOS digital outputs
∙Low-level AC clock input signal allowed
∙Internal reference voltage regulator
∙Power dissipation only 235 mW (typical)
∙Low analog input capacitance, no buffer amplifier required
∙No sample-and-hold circuit required.
ORDERING INFORMATION
APPLICATIONS
High-speed analog-to-digital conversion for:
∙Video data digitizing
∙Radar pulse analysis
∙Transient signal analysis
∙High energy physics research
∙ΣΔ modulators
∙Medical imaging.
GENERAL DESCRIPTION
The TDA8763 is a 10-bit high-speed low-power Analog-to-Digital Converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz. All digital inputs and outputs are TTL and CMOS compatible, although a low-level sine wave clock input signal is allowed.
The device includes an internal voltage reference regulator. If the application requires that the reference is driven via external sources the recommendation is to use the TDA8763A.
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SAMPLING |
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NUMBER |
NAME |
DESCRIPTION |
VERSION |
FREQUENCY (MHz) |
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TDA8763M/3 |
SSOP28 |
plastic shrink small outline package; 28 leads; |
SOT341-1 |
30 |
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TDA8763M/4 |
SSOP28 |
SOT341-1 |
40 |
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body width 5.3 mm |
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TDA8763M/5 |
SSOP28 |
SOT341-1 |
50 |
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1999 Jan 06 |
2 |
Philips Semiconductors |
Product specification |
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10-bit high-speed low-power ADC with
TDA8763
internal reference regulator
QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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VCCA |
analog supply voltage |
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4.75 |
5.0 |
5.25 |
V |
VCCD |
digital supply voltage |
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4.75 |
5.0 |
5.25 |
V |
VCCO |
output stages supply voltage |
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3.0 |
3.3 |
5.25 |
V |
ICCA |
analog supply current |
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− |
30 |
35 |
mA |
ICCD |
digital supply current |
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− |
16 |
21 |
mA |
ICCO |
output stages supply current |
fclk = 40 MHz; ramp input |
− |
1 |
2 |
mA |
INL |
integral non-linearity |
fclk = 40 MHz; ramp input |
− |
±0.8 |
±2.0 |
LSB |
DNL |
differential non-linearity |
fclk = 40 MHz; ramp input |
− |
±0.5 |
±0.9 |
LSB |
fclk(max) |
maximum clock frequency |
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TDA8763M/3 |
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30 |
− |
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MHz |
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TDA8763M/4 |
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40 |
− |
− |
MHz |
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TDA8763M/5 |
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50 |
− |
− |
MHz |
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Ptot |
total power dissipation |
fclk = 40 MHz; ramp input |
− |
235 |
305 |
mW |
1999 Jan 06 |
3 |
Philips Semiconductors |
Product specification |
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10-bit high-speed low-power ADC with
TDA8763
internal reference regulator
BLOCK DIAGRAM
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VCCA |
DEC |
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CLK |
VCCD2 |
OE |
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3 |
5 |
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1 |
11 |
10 |
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REFERENCE |
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CLOCK DRIVER |
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2 |
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VOLTAGE |
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TC |
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REGULATOR |
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TDA8763 |
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VRT |
9 |
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25 |
D9 |
MSB |
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24 |
D8 |
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23 |
D7 |
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RLAD |
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22 |
D6 |
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V I |
8 |
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21 |
D5 |
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analog |
ANALOG -TO - DIGITAL |
LATCHES |
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CMOS |
20 |
D4 |
data outputs |
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voltage input |
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CONVERTER |
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OUTPUTS |
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19 |
D3 |
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VRM |
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7 |
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18 |
D2 |
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17 |
D1 |
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16 |
D0 |
LSB |
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VRB |
6 |
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13 |
VCCO |
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IN-RANGE LATCH |
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26 |
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IR |
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CMOS OUTPUT |
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output |
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28 |
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4 |
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12 |
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14 |
27 |
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VCCD1 |
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AGND |
DGND2 |
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OGND |
DGND1 |
MBE553 |
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analog ground |
digital ground |
output ground digital ground |
Fig.1 Block diagram.
1999 Jan 06 |
4 |
Philips Semiconductors |
Product specification |
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10-bit high-speed low-power ADC with
TDA8763
internal reference regulator
PINNING
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SYMBOL |
PIN |
DESCRIPTION |
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CLK |
1 |
clock input |
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2 |
two’s complement input (active LOW) |
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TC |
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VCCA |
3 |
analog supply voltage (+5 V) |
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AGND |
4 |
analog ground |
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DEC |
5 |
decoupling input |
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VRB |
6 |
reference voltage BOTTOM input |
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VRM |
7 |
reference voltage MIDDLE input |
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VI |
8 |
analog input voltage |
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VRT |
9 |
reference voltage TOP input |
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10 |
output enable input (CMOS level |
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OE |
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input, active LOW) |
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VCCD2 |
11 |
digital supply voltage 2 (+5 V) |
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DGND2 |
12 |
digital ground 2 |
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VCCO |
13 |
supply voltage for output stages |
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(3 to 5 V) |
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OGND |
14 |
output ground |
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n.c. |
15 |
not connected |
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D0 |
16 |
data output; bit 0 (LSB) |
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D1 |
17 |
data output; bit 1 |
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D2 |
18 |
data output; bit 2 |
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D3 |
19 |
data output; bit 3 |
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D4 |
20 |
data output; bit 4 |
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D5 |
21 |
data output; bit 5 |
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D6 |
22 |
data output; bit 6 |
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D7 |
23 |
data output; bit 7 |
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D8 |
24 |
data output; bit 8 |
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D9 |
25 |
data output; bit 9 (MSB) |
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IR |
26 |
in range data output |
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DGND1 |
27 |
digital ground 1 |
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VCCD1 |
28 |
digital supply voltage 1 (+5 V) |
handbook, halfpage |
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VCCD1 |
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CLK |
1 |
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28 |
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TC |
2 |
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27 |
DGND1 |
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VCCA |
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3 |
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26 |
IR |
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AGND |
4 |
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25 |
D9 |
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DEC |
5 |
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24 |
D8 |
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VRB |
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6 |
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23 |
D7 |
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VRM |
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7 |
TDA8763 |
22 |
D6 |
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VI |
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D5 |
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8 |
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21 |
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VRT |
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9 |
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20 |
D4 |
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D3 |
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OE |
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10 |
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19 |
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VCCD2 |
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11 |
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18 |
D2 |
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DGND2 |
12 |
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17 |
D1 |
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V CCO |
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13 |
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16 |
D0 |
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OGND |
14 |
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15 |
n.c. |
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MBE552 |
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Fig.2 Pin configuration.
1999 Jan 06 |
5 |
Philips Semiconductors |
Product specification |
|
|
10-bit high-speed low-power ADC with
TDA8763
internal reference regulator
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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VCCA |
analog supply voltage |
note 1 |
−0.3 |
+7.0 |
V |
VCCD |
digital supply voltage |
note 1 |
−0.3 |
+7.0 |
V |
VCCO |
output stages supply voltage |
note 1 |
−0.3 |
+7.0 |
V |
VCC |
supply voltage difference |
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VCCA − VCCD |
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−1.0 |
+1.0 |
V |
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VCCA − VCCO |
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−1.0 |
+4.0 |
V |
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VCCD − VCCO |
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−1.0 |
+4.0 |
V |
VI |
input voltage |
referenced to AGND |
−0.3 |
+7.0 |
V |
Vi(sw)(p-p) |
AC input voltage for switching (peak-to-peak value) |
referenced to DGND |
− |
VCCD |
V |
IO |
output current |
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− |
10 |
mA |
Tstg |
storage temperature |
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−55 |
+150 |
°C |
Tamb |
operating ambient temperature |
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−40 |
+85 |
°C |
Tj |
junction temperature |
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150 |
°C |
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply voltage differences VCC are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL |
PARAMETER |
CONDITIONS |
VALUE |
UNIT |
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Rth(j-a) |
thermal resistance from junction to ambient |
in free air |
110 |
K/W |
1999 Jan 06 |
6 |
Philips Semiconductors |
Product specification |
|
|
10-bit high-speed low-power ADC with
TDA8763
internal reference regulator
CHARACTERISTICS
VCCA = V3 to V4 = 4.75 to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 to 5.25 V; VCCO = V13 to V14 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to +70 °C; typical values measured at VCCA = VCCD = 5 V and
VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
SYMBOL |
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PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Supplies |
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VCCA |
analog supply voltage |
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4.75 |
5.0 |
5.25 |
V |
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VCCD1 |
digital supply voltage 1 |
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4.75 |
5.0 |
5.25 |
V |
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VCCD2 |
digital supply voltage 2 |
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4.75 |
5.0 |
5.25 |
V |
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VCCO |
output stages supply voltage |
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3.0 |
3.3 |
5.25 |
V |
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VCC |
supply voltage difference |
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VCCA − VCCD |
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−0.20 |
− |
+0.20 |
V |
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VCCA − VCCO |
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−0.20 |
− |
+2.25 |
V |
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VCCD − VCCO |
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−0.20 |
− |
+2.25 |
V |
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ICCA |
analog supply current |
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− |
30 |
35 |
mA |
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ICCD |
digital supply current |
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− |
16 |
21 |
mA |
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ICCO |
output stages supply current |
fclk = 40 MHz; ramp input |
− |
1 |
2 |
mA |
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Inputs |
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CLOCK INPUT CLK (REFERENCED TO DGND); note 1 |
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VIL |
LOW-level input voltage |
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0 |
− |
0.8 |
V |
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VIH |
HIGH-level input voltage |
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2 |
− |
VCCD |
V |
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IIL |
LOW-level input current |
Vclk = 0.8 V |
−1 |
0 |
+1 |
μA |
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IIH |
HIGH-level input current |
Vclk = 2 V |
− |
2 |
10 |
μA |
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Zi |
input impedance |
fclk = 40 MHz |
− |
2 |
− |
kΩ |
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Ci |
input capacitance |
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− |
2 |
− |
pF |
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INPUTS |
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AND |
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(REFERENCED TO DGND); see Table 2 |
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OE |
TC |
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VIL |
LOW-level input voltage |
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0 |
− |
0.8 |
V |
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VIH |
HIGH-level input voltage |
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2 |
− |
VCCD |
V |
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IIL |
LOW-level input current |
VIL = 0.8 V |
−1 |
− |
− |
μA |
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IIH |
HIGH-level input current |
VIH = 2 V |
− |
− |
1 |
μA |
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VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND) |
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IIL |
LOW-level input current |
VI = VRB = 1.3 V |
− |
0 |
− |
μA |
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IIH |
HIGH-level input current |
VI = VRT = 3.67 V |
− |
35 |
− |
μA |
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Zi |
input impedance |
fi = 4.43 MHz |
− |
8 |
− |
kΩ |
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Ci |
input capacitance |
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− |
5 |
− |
pF |
1999 Jan 06 |
7 |
Philips Semiconductors |
Product specification |
|
|
10-bit high-speed low-power ADC with
TDA8763
internal reference regulator
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
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MAX. |
UNIT |
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Reference voltages for the resistor ladder using the internal voltage regulator; see Table 1 |
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VRB |
reference voltage BOTTOM |
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1.1 |
1.3 |
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1.5 |
V |
VRT |
reference voltage TOP |
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3.4 |
3.6 |
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3.8 |
V |
Vdiff |
differential reference voltage |
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2.25 |
2.3 |
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2.35 |
V |
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VRT − VRB |
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Iref |
reference current |
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− |
9.39 |
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− |
mA |
Rlad |
resistor ladder |
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− |
245 |
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− |
Ω |
TCRlad |
temperature coefficient of the |
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− |
1860 |
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− |
ppm |
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resistor ladder |
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− |
456 |
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− |
mΩ/K |
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Voffset(B) |
offset voltage BOTTOM |
note 2 |
− |
175 |
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− |
mV |
Voffset(T) |
offset voltage TOP |
note 2 |
− |
175 |
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− |
mV |
Vi(p-p) |
analog input voltage |
note 3 |
1.90 |
1.95 |
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2.00 |
V |
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(peak-to-peak value) |
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Outputs |
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DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND) |
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VOL |
LOW-level output voltage |
IOL = 1 mA |
0 |
− |
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0.5 |
V |
VOH |
HIGH-level output voltage |
IOH = −1 mA |
VCCO − 0.5 |
− |
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VCCO |
V |
IOZ |
output current in 3-state mode |
0.5 V < Vo < VCCO |
−20 |
− |
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+20 |
μA |
Switching characteristics |
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CLOCK INPUT CLK; see Fig.4; note 1 |
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fclk(max) |
maximum clock frequency |
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TDA8763M/3 |
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30 |
− |
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− |
MHz |
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TDA8763M/4 |
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40 |
− |
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− |
MHz |
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TDA8763M/5 |
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50 |
− |
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− |
MHz |
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tCPH |
clock pulse width HIGH |
full effective bandwidth |
8.5 |
− |
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− |
ns |
tCPL |
clock pulse width LOW |
full effective bandwidth |
5.5 |
− |
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− |
ns |
Analog signal processing |
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LINEARITY |
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INL |
integral non-linearity |
fclk = 40 MHz; ramp input |
− |
±0.8 |
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±2.0 |
LSB |
DNL |
differential non-linearity |
fclk = 40 MHz; ramp input |
− |
±0.5 |
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±0.9 |
LSB |
Eoffset |
offset error |
middle code |
− |
±1 |
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− |
LSB |
EG |
gain error (from device to device) |
note 4 |
− |
±3 |
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% |
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using internal reference voltage |
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1999 Jan 06 |
8 |