INTEGRATED CIRCUITS
TSA5520; TSA5521
1.3 GHz universal bus-controlled TV synthesizer
Product specification |
1996 Oct 10 |
Supersedes data of 1995 Mar 16
File under Integrated Circuits, IC02
Philips Semiconductors |
Product specification |
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1.3 GHz universal bus-controlled
TSA5520; TSA5521
TV synthesizer
FEATURES
∙Complete 1.3 GHz single chip system
∙Four PNP band switch buffers (40 mA)
∙33 V output tuning voltage
∙In-lock detector
∙15-bit programmable divider
∙Programmable reference divider ratio (512, 640 or 1024)
∙Programmable charge-pump current (60 or 280 μA)
∙Varicap drive disable
∙Universal bus protocol I2C-bus or 3-wire bus (the TSA5520/TSA5521 I2C-bus mode only includes the write mode; if both read and write modes are required the TSA5526/TSA5527 devices should be selected):
–bus protocol for 18 or 19 bits transmission (3-wire bus)
–extra protocol for 27 bits for test and features (3-wire bus)
–address plus 4 data bytes transmission (I2C-bus)
–three independent I2C-bus addresses
∙Low power and low radiation.
ORDERING INFORMATION
APPLICATIONS
∙TV tuners and front ends
∙VCR tuners.
TYPE NUMBER |
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PACKAGE |
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NAME |
DESCRIPTION |
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TSA5520M |
SSOP16 |
plastic shrink small outline package; 16 leads; body width 4.4 mm |
SOT369-1 |
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TSA5520T |
SO16 |
plastic small outline package; 16 leads; body width 3.9 mm |
SOT109-1 |
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TSA5521M |
SSOP16 |
plastic shrink small outline package; 16 leads; body width 4.4 mm |
SOT369-1 |
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TSA5521T |
SO16 |
plastic small outline package; 16 leads; body width 3.9 mm |
SOT109-1 |
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1996 Oct 10 |
2 |
Philips Semiconductors |
Product specification |
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1.3 GHz universal bus-controlled
TSA5520; TSA5521
TV synthesizer
QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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VCC1 |
supply voltage (+5 V) |
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4.5 |
- |
5.5 |
V |
VCC2 |
band switch supply voltage (12 V) |
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VCC1 |
12 |
13.5 |
V |
ICC1 |
supply current |
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- |
20 |
25 |
mA |
ICC2 |
band switch supply current |
note 1 |
- |
50 |
55 |
mA |
fRF |
RF input frequency |
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64 |
- |
1300 |
MHz |
Vi(RF) |
RF input voltage |
80 to 150 MHz |
-25 |
- |
+3 |
dBm |
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150 MHz to 1 GHz |
-28 |
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+3 |
dBm |
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1 to 1.3 GHz |
-15 |
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+3 |
dBm |
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fxtal |
crystal oscillator input frequency |
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3.2 |
4.0 |
4.48 |
MHz |
Io(PNP) |
PNP band switch buffers output current |
note 2 |
4 |
- |
50 |
mA |
Ptot |
total power dissipation |
note 3 |
- |
250 |
400 |
mW |
Tstg |
IC storage temperature |
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-40 |
- |
+150 |
°C |
Tamb |
operating ambient temperature |
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-20 |
- |
+85 |
°C |
Notes
1.One band switch buffer ON with 40 mA.
2.One buffer ON, Io = 40 mA; two buffers ON, maximum sum of Io = 50 mA.
3.The power dissipation is calculated as follows:
PD = VCC1 ´ ICC1 + VCC2 ´ (ICC2 –Io) + Io ´ VCE ( satPNP) + (V33 ¤ 2) 2 ¤ 27 kW
1996 Oct 10 |
3 |
Philips Semiconductors |
Product specification |
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1.3 GHz universal bus-controlled
TSA5520; TSA5521
TV synthesizer
GENERAL DESCRIPTION
The device is a single-chip PLL frequency synthesizer designed for TV and VCR tuning systems. The circuit consists of a divide-by-eight prescaler with its own preamplifier, a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and a phase/frequency detector combined with a charge-pump which drives the tuning amplifier and the 33 V output. Four high-current PNP band switch buffers are provided for band switching. Two PNP buffers can be switched on simultaneously. The sum of the collector currents is limited to 50 mA.
Depending on the reference divider ratio (512, 640 or 1024), the phase comparator operates at 3.90625 kHz, 6.25 kHz or 7.8125 kHz using a 4 MHz crystal.
The lock detector output is LOW when the PLL loop is locked. In the test mode, this output is used as a test
output for fref and 1/2fdiv (see Table 6). The device can be controlled in accordance with the I2C-bus format or the
3-wire bus format depending on the voltage applied to the SW input (see Table 2).
I2C-bus format (SW = LOW)
Five serial bytes (including address byte) are required to address the device, select the VCO frequency, program the four PNP band switch buffers, set the charge-pump current and the reference divider ratio.
The device has three independent I2C-bus addresses which can be selected by applying a specific voltage on the CE input (see Table 5). The general address C2 is always valid. When the I2C-bus format is fully used, TSA5520 and TSA5521 are equal.
3-wire bus format (SW = VCC1 or open-circuit)
Data is transmitted to the device during a HIGH level on the CE input (enable line pin 15). The device is compatible with 18-bit and 19-bit data formats. The first four bits are used to program the PNP band switch buffers and the remaining bits are used to control the programmable divider. A 27-bit data format may also be used to set the charge-pump current, the reference divider ratio and for test purposes. The difference between TSA5520 and TSA5521 are given in Table 1.
When the 27-bit format is used, the TSA5520 and TSA5521 are equal and the reference divider is controlled by the RSA and RSB bits (see Table 7). More details are given in Chapter “Functional description” Section “3-wire
bus mode (SW = open-circuit or VCC1); see Figs 3, 4 and 5”.
Table 1 Differences between TSA5520 and TSA5521
TYPE NUMBER |
DATA WORD |
REFERENCE DIVIDER |
FREQUENCY STEP (kHz) |
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TSA5520 |
18-bit |
512(1) |
62.5 |
TSA5520 |
19-bit |
1024(1) |
31.25 |
TSA5521 |
18-bit or 19-bit |
640(2) |
50 |
Notes
1.The selection of the reference divider is given by an automatic identification of the data word length.
2.The reference divider is set to 640 at power-on reset.
1996 Oct 10 |
4 |
Philips Semiconductors |
Product specification |
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1.3 GHz universal bus-controlled
TSA5520; TSA5521
TV synthesizer
BLOCK DIAGRAM
1 |
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PRESCALER |
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15-BIT |
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9 |
CP |
AMP |
PROGRAMMABLE |
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RF |
DIVIDE-BY-8 |
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DIVIDER |
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10 |
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Vtune |
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fdiv |
DIGITAL |
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16 |
XTAL |
DIVIDER |
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CHARGE |
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f ref |
PHASE |
AMP |
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XTAL |
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PUMP |
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OSCILLATOR |
512/640/1024 |
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COMPARATOR |
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CP |
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RSA RSB |
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T2,T1,T0 |
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POWER-ON |
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15-BIT FREQUENCY |
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RESET |
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REGISTER |
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IN-LOCK |
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13 |
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DETECTOR |
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LOGIC |
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SCL |
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LOCK |
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14 |
I2C/3-WIRE BUS |
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SDA |
RECEIVER |
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15 |
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RSA,RSB |
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CE |
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3 |
VCC1 |
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OS |
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4-BIT BAND SWITCH |
GATE |
7-BIT CONTROL |
2 |
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11 |
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REGISTER |
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REGISTER |
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VEE |
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SW |
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T2,T1,T0 |
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12 |
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LOCK |
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TSA5520 |
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TSA5521 |
4 |
8 |
7 |
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6 |
5 |
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VCC2 |
BS1 |
BS2 |
BS3 |
BS4 |
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MKA965 |
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Fig.1 |
Block diagram. |
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1996 Oct 10 |
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5 |
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Philips Semiconductors |
Product specification |
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1.3 GHz universal bus-controlled
TSA5520; TSA5521
TV synthesizer
PINNING
SYMBOL |
PIN |
DESCRIPTION |
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RF |
1 |
RF signal input |
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VEE |
2 |
ground |
VCC1 |
3 |
supply voltage (+5 V) |
VCC2 |
4 |
band switch supply voltage (+12 V) |
BS4 |
5 |
PNP band switch buffer output 4 |
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BS3 |
6 |
PNP band switch buffer output 3 |
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BS2 |
7 |
PNP band switch buffer output 2 |
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BS1 |
8 |
PNP band switch buffer output 1 |
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CP |
9 |
charge-pump output |
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Vtune |
10 |
tuning voltage output |
SW |
11 |
bus format selection input, I2C-bus or |
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3-wire |
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LOCK |
12 |
lock detector output |
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SCL |
13 |
serial clock input |
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SDA |
14 |
serial data input/output |
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CE |
15 |
chip enable/address selection input |
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XTAL |
16 |
crystal oscillator input |
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FUNCTIONAL DESCRIPTION
The device is controlled via the I2C-bus or the 3-wire bus depending on the voltage applied to the SW input (pin 11). A HIGH level on the SW input enables the 3-wire bus inputs which are Chip Enable (CE), serial data input (SDA) and serial clock input (SCL). A LOW level on the SW input enables the I2C-bus inputs which are CE [Address Selection (AS) input], serial data input/output (SDA) and serial clock input (SCL). The bus format selection is given in Table 2.
I2C-bus mode (SW = LOW); see Table 3
Data bytes can be sent to the device after the address transmission (first byte). Four data bytes are required to fully program the device. The bus receiver has an auto-increment facility which permits the programming of the device within one single transmission
(address + 4 data bytes).
The device can also be partially programmed providing that the first data byte following the address is Divider Byte 1 (DB1) or the Control Byte (CB). The bits in the data bytes are defined in Table 3.
Fig.2 Pin configuration.
The first bit of the first data byte transmitted indicates whether frequency data (first bit = 0) or control and band switch data (first bit = 1) will follow. Until an I2C-bus STOP command is sent by the controller, additional data bytes can be entered without the need to re-address the device. The frequency register is loaded after the 8th clock pulse of the second Divider Byte (DB2), the control register is loaded after the 8th clock pulse of the Control Byte (CB) and the band switch register is loaded after the 8th clock pulse of the Band switch Byte (BB).
I2C-bus address selection
The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several synthesizers (up to 3) in one system by applying a specific voltage to the CE input.
The relationship between MA1 and MA0 and the input voltage applied to the CE input is given in Table 5.
1996 Oct 10 |
6 |
Philips Semiconductors |
Product specification |
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1.3 GHz universal bus-controlled
TSA5520; TSA5521
TV synthesizer
Table 2 Bus format selection
PIN |
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NAME |
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3-WIRE BUS MODE |
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I2C BUS MODE |
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11 |
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SW |
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open or HIGH |
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LOW |
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13 |
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SCL |
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clock input |
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SCL input |
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14 |
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SDA |
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data input |
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SDA input/output |
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15 |
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CE |
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chip enable input |
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address selection input |
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Table 3 I2C-bus data format |
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BYTE |
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MSB |
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DATA BYTE |
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LSB |
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SLAVE ANSWER |
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Address Byte (ADB) |
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1 |
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1 |
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0 |
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0 |
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0 |
MA1 |
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MA0 |
0 |
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A |
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Divider Byte 1 (DB1) |
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0 |
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N14 |
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N13 |
N12 |
N11 |
N10 |
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N9 |
N8 |
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A |
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Divider Byte 2 (DB2) |
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N7 |
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N6 |
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N5 |
N4 |
N3 |
N2 |
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N1 |
N0 |
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A |
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Control Byte (CB) |
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1 |
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CP |
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T2 |
T1 |
T0 |
RSA |
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RSB |
OS |
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A |
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Band switch Byte (BB) |
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X |
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X |
BS4 |
BS3 |
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BS2 |
BS1 |
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Table 4 Description of Table 3 |
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SYMBOL |
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DESCRIPTION |
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A |
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acknowledge |
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MA1 and MA0 |
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programmable address bits (see Table 5) |
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N14 to N0 |
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programmable divider bits; N = N14 × 214 + N13 × 213 + ... + N1 × 2 + N0 |
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CP |
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charge-pump current; CP = 0 = 60 μA; CP = 1 = 280 μA |
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T2 to T0 |
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test bits (see Table 6); for normal operation T2 = 0, T1 = 0 and T0 = 1 |
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RSA and RSB |
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reference divider ratio select bits (see Table 7) |
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OS |
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tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON; |
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when OS = 1 tuning voltage is OFF (high impedance) |
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BS4 to BS1 |
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PNP band switch buffers control bits; when BSn = 0 buffer n is OFF; |
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when BSn = 1 buffer n is ON |
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X |
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don’t care |
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Table 5 I2C-bus address selection |
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VOLTAGE APPLIED TO THE |
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MA1 |
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MA0 |
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CE INPUT (SW = LOW) |
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0 to 0.1VCC1 |
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0 |
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0 |
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Always valid |
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0 |
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1 |
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0.4VCC1 to 0.6VCC1 |
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1 |
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0 |
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0.9VCC1 to VCC1 |
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1 |
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1996 Oct 10 |
7 |
Philips Semiconductors |
Product specification |
|
|
1.3 GHz universal bus-controlled
TSA5520; TSA5521
TV synthesizer
3-wire bus mode (SW = open-circuit or VCC1); see Figs 3, 4 and 5
During a HIGH level on the CE input, the data is clocked into the data register at the HIGH-to-LOW transition of the clock pulse. The first four bits control the band switch buffers and are loaded into the internal band switch register on the 5th rising edge of the clock pulse.
The frequency bits are loaded into the frequency register at the HIGH-to-LOW transition of the chip enable line when an 18-bit or 19-bit data word is transmitted.
At power-on the charge-pump current is set to 280 mA, the tuning voltage output is disabled (Vtune = 33 V in application; see Fig.12), the test bits T2, T1 and T0 are set to the normal mode and RSB is set to 1 (TSA5520) or 0 (TSA5521). When an 18-bit data word is transmitted, the most significant bit of the divider N14 is internally set to 0 and bit RSA is set to 1. When a 19-bit data word is transmitted, bit RSA is set to 0.
When a 27-bit word is transmitted, the frequency bits are loaded into the frequency register on the 20th rising edge of the clock pulse and the control bits at the HIGH-to-LOW transition of the chip enable line. In this mode, the reference divider is given by the RSA and RSB bits (see Table 7). The test bits T2, T1 and T0, the charge-pump bit CP, the ratio select bit RSB and the OS bit can only be selected or changed with a 27-bit transmission. They remain programmed if an 18-bit or a 19-bit transmission
occurs. Only RSA is controlled by the transmission length when the 18-bit or 19-bit format is used.
A data word of less than 18 bits will not affect the frequency register of the device. The definition of the bits is unchanged compared to the I2C bus mode.
The power-on detection threshold voltage VPOR is fixed to VCC1 = 2 V at room temperature. Below this threshold, the device is reset to the power-on state described above.
Table 6 |
Test bits |
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T2 |
T1 |
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T0 |
DEVICE OPERATION |
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0 |
0 |
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1 |
normal mode |
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0 |
1 |
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X |
charge-pump is OFF |
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1 |
1 |
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0 |
charge-pump is sinking current |
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1 |
1 |
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1 |
charge-pump is sourcing current |
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1 |
0 |
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0 |
fref is available at LOCK output |
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1 |
0 |
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1 |
1¤2fdiv is available at LOCK output |
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Table 7 Ratio select bits |
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RSA |
RSB |
REFERENCE DIVIDER |
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X |
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0 |
640 |
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0 |
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1 |
1024 |
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1 |
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1 |
512 |
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For TSA5520 bit RSB = 1 at power-on; the reference divider is 512 or 1024.
For TSA5521 bit RSB = 0 at power-on; the reference divider is 640.
For TSA5520/TSA5521 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB remains as programmed with the 27-bit data word.
Fig.3 Normal mode; 18-bit data format (RSA = 1).
1996 Oct 10 |
8 |