Philips tda6108jf DATASHEETS

INTEGRATED CIRCUITS

DATA SHEET

TDA6108JF

Triple video output amplifier

Product specification

1999 Oct 29

Supersedes data of 1998 Jun 22

File under Integrated Circuits, IC02

Philips Semiconductors	Product specification
Triple video output amplifier	TDA6108JF

FEATURES

∙Typical bandwidth of 9.0 MHz for an output signal of 60 V (p-p)

∙High slew rate of 1850 V/μs

∙No external components required

∙Very simple application

∙Single supply voltage of 200 V

∙Internal reference voltage of 2.5 V

∙Fixed gain of 51

ORDERING INFORMATION

∙Black-Current Stabilization (BCS) circuit

∙Thermal protection.

GENERAL DESCRIPTION

The TDA6108JF includes three video output amplifiers in one plastic DIL-bent-SIL 9-pin medium power (DBS9MPF) package (SOT111-1), using high-voltage DMOS technology, and is intended to drive the three cathodes of a colour CRT directly. To obtain maximum performance, the amplifier should be used with black-current control.

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
TDA6108JF	DBS9MPF	plastic DIL-bent-SIL medium power package with fin; 9 leads	SOT111-1

BLOCK DIAGRAM

VDD

					6
	MIRROR 1			MIRROR 5
		TDA6108JF		CASCODE 1
			MIRROR 4	3×
					Voc(3),
	CURRENT
				1×	9, 8, 7
	SOURCE				Voc(2),
					Voc(1)
				1×
	THERMAL			Rf
	PROTECTION	VIP	DIFFERENTIAL
	CIRCUIT	REFERENCE	STAGE
Vi(1),	1, 2, 3				5
Vi(2),		MIRROR 3
					I
Vi(3)	Ri				o(m)
	Ra
	3×			CASCODE 2

MIRROR 2

4

MGL318

Fig.1 Block diagram (one amplifier shown).

1999 Oct 29

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	Philips Semiconductors							Product specification
	Triple video output amplifier							TDA6108JF
	PINNING
	SYMBOL	PIN	DESCRIPTION
	Vi(1)	1	inverting input 1		handbook, halfpage
	Vi(2)	2	inverting input 2		Vi(1)	1
	Vi(3)	3	inverting input 3		Vi(2)	2
	GND	4	ground (fin)		Vi(3)	3
	Iom	5	black current measurement output		GND	4
	VDD	6	supply voltage		Iom	5	TDA6108JF
	Voc(3)	7	cathode output 3
					VDD	6
	Voc(2)	8	cathode output 2
					Voc(3)	7
	Voc(1)	9	cathode output 1
					Voc(2)
						8
					Voc(1)	9
							MGL319
					Fig.2		Pin configuration.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); voltages measured with respect to pin 4 (ground); currents as specified in Fig.1; unless otherwise specified.

SYMBOL	PARAMETER	MIN.	MAX.	UNIT
VDD	supply voltage	0	250	V
Vi	input voltage	0	12	V
Vom	measurement output voltage	0	6	V
Voc	cathode output voltage	0	VDD	V
Tstg	storage temperature	−55	+150	°C
Tj	junction temperature	−20	+150	°C
Ves	electrostatic handling
	human body model (HBM)	−	2000	V
	machine model (MM)	−	300	V

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).

QUALITY SPECIFICATION

Quality specification “SNW-FQ-611 part D” is applicable.

1999 Oct 29

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Philips Semiconductors			Product	specification
Triple video output amplifier			TDA6108JF
THERMAL CHARACTERISTICS
SYMBOL	PARAMETER	CONDITIONS	VALUE	UNIT
Rth(j-a)	thermal resistance from junction to ambient		56	K/W
Rth(j-fin)	thermal resistance from junction to fin	note 1	11	K/W
Rth(h-a)	thermal resistance from heatsink to ambient		10	K/W

Note

1. An external heatsink is necessary.

8					MGL322
handbook, halfpage
Ptot
(W)
6		(1)
4
		(2)
2
0
−20	20	60	100	140	180
				Tamb (°C)

(1)Infinite heatsink.

(2)No heatsink.

Thermal protection

The internal thermal protection circuit gives a decrease of the slew rate at high temperatures: 10% decrease at 130 °C and 30% decrease at 145 °C (typical values on the spot of the thermal protection circuit).

handbook, halfpage

outputs

5 K/W

thermal protection circuit

6 K/W

fin MGK279

Fig.3 Power derating curves.

Fig.4 Equivalent thermal resistance network.

1999 Oct 29

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Philips Semiconductors	Product specification
Triple video output amplifier	TDA6108JF

CHARACTERISTICS

Operating range: Tj = -20 to +150 °C; VDD = 180 to 210 V. Test conditions: Tamb = 25 °C; VDD = 200 V;

Vo(c1) = Vo(c2) = Vo(c3) = 1¤2VDD; CL = 10 pF (CL consists of parasitic and cathode capacitance); Rth(h-a) = 18 K/W (measured in test circuit of Fig.8); unless otherwise specified.

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Iq	quiescent supply current		8.8	10.3	11.7	mA
Vref(int)	internal reference voltage		-	2.5	-	V
	(input stage)
Ri	input resistance		-	3.2	-	kW
G	gain of amplifier		47.5	51.0	55.0
DG	gain difference		-2.5	0	+2.5
VO(c)	nominal output voltage at	Ii = 0 mA	116	129	142	V
	pins 7, 8 and 9 (DC value)
DVO(c)(offset)	differential nominal output	Ii = 0 mA	-	0	5	V
	offset voltage between
	pins 7 and 8, 8 and 9 and
	9 and 7 (DC value)
DVo(c)(T)	output voltage temperature		-	-10	-	mV/K
	drift at pins 7, 8 and 9
DVo(c)(T)(offset)	differential output offset		-	0	-	mV/K
	voltage temperature drift
	between pins 7 and 8,
	8 and 9 and 7 and 9
Io(m)(offset)	offset current of measurement	Io(c) = 0 mA;	-50	-	+50	mA
	output (for 3 channels)	1.5 V < Vi < 5.5 V;
		3 V < Vo(m) < 6 V
DIo(m)/DIo(c)	linearity of current transfer	-100 mA < Io(c) < 100 mA;	0.9	1.0	1.1
		1.5 V < Vi < 5.5 V;
		3 V < Vo(m) < 6 V
Io(c)(max)	maximum peak output current	50 V < Vo(c) < VDD - 50 V	-	28	-	mA
	(pins 7, 8 and 9)
Vo(c)(min)	minimum output voltage	Vi = 7.0 V; note 1	-	-	10	V
	(pins 7, 8 and 9)
Vo(c)(max)	maximum output voltage	Vi = 1.0 V; note 1	VDD - 15	-	-	V
	(pins 7, 8 and 9)
BS	small signal bandwidth	Vo(c) = 60 V (p-p)	-	9.0	-	MHz
	(pins 7, 8 and 9)
BL	large signal bandwidth	Vo(c) = 100 V (p-p)	-	8.0	-	MHz
	(pins 7, 8 and 9)
tPco	cathode output propagation	Vo(c) = 100 V (p-p)	-	32	-	ns
	time 50% input to 50% output	square wave; f <1 MHz;
	(pins 7, 8 and 9)	tr = tf = 40 ns
		(pins 1, 2 and 3);
		see Figs 6 and 7

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