Philips TDA8714T-7-C1-R1, TDA8714T-7-C1, TDA8714T-6-C1, TDA8714T-6-C1-S1, TDA8714U-C1 Datasheet

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DATA SHEET

TDA8714

8-bit high-speed analog-to-digital converter

Product specification

1997 Oct 29

Supersedes data of 1996 Jan 31

File under Integrated Circuits, IC02

Philips Semiconductors	Product specification
8-bit high-speed analog-to-digital converter	TDA8714

FEATURES

∙8-bit resolution

∙Sampling rate up to 80 MHz

∙No missing codes guaranteed

∙High signal-to-noise ratio over a large analog input frequency range (7.7 effective bits at 4.43 MHz full-scale input at fclk = 80 MHz)

∙Overflow/underflow 3-state TTL output

∙TTL compatible digital inputs

∙Low-level AC clock input signal allowed

∙External reference voltage regulator

∙Power dissipation only 340 mW (typical)

∙Low analog input capacitance, no buffer amplifier required

∙No sample-and-hold circuit required.

QUICK REFERENCE DATA

APPLICATIONS

High-speed analog-to-digital conversion for:

∙video data digitizing

∙radar pulse analysis

∙transient signal analysis

∙high energy physics research

∙ΣΔ modulators

∙medical imaging.

GENERAL DESCRIPTION

The TDA8714 is an 8-bit high-speed Analog-to-Digital Converter (ADC) for professional video and other applications. It converts the analog input signal into 8-bit binary-coded digital words at a maximum sampling rate of 80 MHz. All digital inputs and outputs are TTL compatible, although a low-level sine wave clock input signal is allowed.

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
VCCA	analog supply voltage		4.75	5.0	5.25	V
VCCD	digital supply voltage		4.75	5.0	5.25	V
VCCO	output stages supply voltage		4.75	5.0	5.25	V
ICCA	analog supply current		−	25	30	mA
ICCD	digital supply current		−	27	33	mA
ICCO	output stages supply current		−	16	20	mA
INL	DC integral non-linearity		−	±0.4	±0.5	LSB
DNL	DC differential non-linearity		−	±0.2	±0.35	LSB
AINL	AC integral non-linearity	note 1	−	±0.5	±1.0	LSB
fclk(max)	maximum clock frequency
	TDA8714/7		80	−	−	MHz
	TDA8714/6		60	−	−	MHz
	TDA8714/4		40	−	−	MHz
Ptot	total power dissipation		−	340	435	mW

Note

1. Full-scale sine wave (fi = 4.43 MHz; fclk = 80 MHz).

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Philips Semiconductors					Product specification
8-bit high-speed analog-to-digital converter					TDA8714
ORDERING INFORMATION
TYPE			PACKAGE		SAMPLING
NUMBER	NAME		DESCRIPTION	VERSION	FREQUENCY (MHz)
TDA8714T/4	SO24	plastic small outline package; 24 leads;		SOT137-1	40
			body width 7.5 mm
TDA8714T/6	SO24			SOT137-1	60
TDA8714T/7	SO24			SOT137-1	80
TDA8714M/4	SSOP24		plastic shrink small outline package; 24 leads;	SOT340-1	40
			body width 5.3 mm
TDA8714M/6	SSOP24			SOT340-1	60
TDA8714M/7	SSOP24			SOT340-1	80

BLOCK DIAGRAM

handbook, full pagewidth

			VCCA			CLK	VCCD	CE
			7			16	18	22
					CLOCK DRIVER
	VRT	9				TDA8714
									12	D7	MSB
									13	D6
									14	D5
	V I	8	ANALOG -TO-DIGITAL						15	D4
analog						LATCHES		TTL OUTPUTS	23	D3	data outputs
voltage input			CONVERTER
									24	D2
									1	D1
									2	D0	LSB
	VRB	4							19	VCCO1
									21	VCCO2
						OVERFLOW / UNDERFLOW		TTL OUTPUT	11		overflow / underflow
	OGND	20				LATCH					output
output ground			6	17
			AGND	DGND				MSA669

analog ground

digital ground

Fig.1 Block diagram.

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Philips Semiconductors	Product specification
8-bit high-speed analog-to-digital converter	TDA8714

PINNING
	SYMBOL		PIN	DESCRIPTION
D1			1	data output; bit 1
D0			2	data output; bit 0 (LSB)
n.c.			3	not connected
VRB			4	reference voltage BOTTOM input
	n.c.		5	not connected		handbook, halfpage
	AGND		6	analog ground
	VCCA		7	analog supply voltage (+5 V)
	VI		8	analog input voltage
	VRT		9	reference voltage TOP input
	n.c.		10	not connected
	O/UF		11	overflow/underflow data output
	D7		12	data output; bit 7 (MSB)
	D6		13	data output; bit 6
	D5		14	data output; bit 5
	D4		15	data output; bit 4
	CLK		16	clock input
	DGND		17	digital ground
	VCCD		18	digital supply voltage (+5 V)
VCCO1			19	supply voltage for output stages 1
				(+5 V)
OGND			20	output ground
VCCO2			21	supply voltage for output stages 2
				(+5 V)
			22	chip enable input (TTL level input,
	CE
				active LOW)
D3			23	data output; bit 3
D2			24	data output; bit 2

D1	1		24		D2
D0	2		23		D3
n.c.	3		22
				CE
V	4		21		V	CCO2
RB
n.c.	5		20	OGND
AGND	6	TDA8714	19	VCCO1
VCCA	7		18	VCCD
V I	8		17		DGND
VRT					CLK
	9		16
n.c.					D4
	10		15
O/UF					D5
	11		14
D7	12				D6
			13
		MSA667

Fig.2 Pin configuration.

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Philips Semiconductors					Product specification
8-bit high-speed analog-to-digital converter					TDA8714
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL		PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VCCA		analog supply voltage	note 1	−0.3	+7.0	V
VCCD		digital supply voltage	note 1	−0.3	+7.0	V
VCCO		output stages supply voltage	note 1	−0.3	+7.0	V
VCC		supply voltage differences between		−1.0	+1.0	V
		VCCA and VCCD
VCC		supply voltage differences between		−1.0	+1.0	V
		VCCO and VCCD
VCC		supply voltage differences between		−1.0	+1.0	V
		VCCA and VCCO
VI		input voltage	referenced to AGND	−0.3	+7.0	V
Vclk(p-p)		AC input voltage for switching	referenced to DGND	−	VCCD	V
		(peak-to-peak value)
IO		output current		−	10	mA
Tstg		storage temperature		−55	+150	°C
Tamb		operating ambient temperature		0	+70	°C
Tj		junction temperature		−	+150	°C

Note

1.The supply voltages VCCA and VCCD may have any value between −0.3 V and +7.0 V provided the difference between VCCA and VCCD is between −1 V and +1 V.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL	PARAMETER	VALUE	UNIT
Rth j-a	thermal resistance from junction to ambient in free air
	SOT137-1	75	K/W
	SOT340-1	119	K/W

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Philips Semiconductors	Product specification
8-bit high-speed analog-to-digital converter	TDA8714

CHARACTERISTICS

VCCA = V7 to V6 = 4.75 to 5.25 V; VCCD = V18 to V17 = 4.75 to 5.25 V; VCCO = V19 and V21 to V20 = 4.75 to 5.25 V; AGND and DGND shorted together; VCCA to VCCD = −0.25 to +0.25 V; VCCO to VCCD = −0.25 to +0.25 V;

VCCA to VCCO = −0.25 to +0.25 V; Vi(p-p) = 1.75 V; Tamb = 0 to +70 °C; typical values measured at VCCA = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified.

SYMBOL			PARAMETER		CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supply
VCCA			analog supply voltage			4.75	5.0	5.25	V
VCCD			digital supply voltage			4.75	5.0	5.25	V
VCCO			output stages supply voltage			4.75	5.0	5.25	V
ICCA			analog supply current			−	25	30	mA
ICCD			digital supply current			−	27	33	mA
ICCO			output stages supply current			−	16	20	mA
Inputs
CLOCK INPUT CLK (REFERENCED TO DGND); note 1
VIL			LOW level input voltage			0	−	0.8	V
VIH			HIGH level input voltage			2.0	−	VCCD	V
IIL			LOW level input current	Vclk	= 0.4 V	−400	−	−	μA
IIH			HIGH level input current	Vclk	= 2.7 V	−	−	300	μA
ZI			input impedance	fclk = 80 MHz		−	18	−	kΩ
CI			input capacitance	fclk = 80 MHz		−	1	−	pF
INPUT		(REFERENCED TO DGND); see Table 2
	CE
VIL			LOW level input voltage			0	−	0.8	V
VIH			HIGH level input voltage			2.0	−	VCCD	V
IIL			LOW level input current	VIL = 0.4 V		−400	−	−	μA
IIH			HIGH level input current	VIH = 2.7 V		−	−	20	μA
VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND)
IIL			LOW level input current	VI = 1.2 V		−	0	−	μA
IIH			HIGH level input current	VI = 3.5 V		60	130	280	μA
ZI			input impedance	fi = 4.43 MHz		−	10	−	kΩ
CI			input capacitance	fi = 4.43 MHz		−	14	−	pF
Reference voltages for the resistor ladder; see Table 1
VRB			reference voltage BOTTOM			1.2	1.3	1.6	V
VRT			reference voltage TOP			3.5	3.6	3.9	V
Vdiff			differential reference voltage VRT − VRB			1.9	2.3	2.7	V
Iref			reference current			−	11.5	−	mA
RLAD			resistor ladder			−	200	−	Ω
TCRLAD			temperature coefficient of the resistor ladder			−	0.24	−	ppm
VosB			offset voltage BOTTOM	note 2		275	285	295	mV
VosT			offset voltage TOP	note 2		305	315	325	mV
Vi(p-p)			analog input voltage (peak-to-peak value)			1.45	1.75	2.15	V

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Philips Semiconductors				Product specification
8-bit high-speed analog-to-digital converter					TDA8714
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Outputs
DIGITAL OUTPUTS D7 to D0 (REFERENCED TO DGND)
VOL	LOW level output voltage	IO = 1 mA	0	−	0.4	V
VOH	HIGH level output voltage	IO = −0.4 mA	2.7	−	VCCD	V
		IO = −1 mA	2.4	−	VCCD	V
IOZ	output current in 3-state mode	0.4 V < VO < VCCD	−20	−	+20	μA
Switching characteristics
CLOCK INPUT CLK (note 1; see Fig.3)
fclk(max)	maximum clock frequency
	TDA8714/4		40	−	−	MHz
	TDA8714/6		60	−	−	MHz
	TDA8714/7		80	−	−	MHz
tCPH	clock pulse width HIGH		6	−	−	ns
tCPL	clock pulse width LOW		6	−	−	ns
Analog signal processing
LINEARITY
INL	DC integral non-linearity		−	±0.4	±0.5	LSB
DNL	DC differential non-linearity		−	±0.2	±0.35	LSB
AINL	AC integral non-linearity	note 3	−	±0.5	±1.0	LSB
BANDWIDTH (fclk = 40 MHz); note 4
B	analog bandwidth	full-scale sine wave	−	13	−	MHz
		75% full-scale sine	−	20	−	MHz
		wave; small signal at
		Vi = ±5 LSB, code 128
tSTLH	analog input settling time LOW-to-HIGH	full-scale square	−	2.5	3.5	ns
		wave; Fig.6; note 5
tSTHL	analog input settling time HIGH-to-LOW	full-scale square	−	3.0	4.0	ns
		wave; Fig.6; note 5
HARMONICS (fclk = 40 MHz)
h1	fundamental harmonics (full scale)	fi = 4.43 MHz	−	−	0	dB
hall	harmonics (full scale);	fi = 4.43 MHz
	all components
	second harmonics		−	−64	−60	dB
	third harmonics		−	−58	−55	dB
THD	total harmonic distortion	fi = 4.43 MHz	−	−56	−	dB
SIGNAL-TO-NOISE RATIO (note 6; see Figs 7 and 13)
S/N	signal-to-noise ratio (full scale)	without harmonics;	46	48	−	dB
		fclk = 40 MHz;
		fi = 4.43 MHz

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Philips Semiconductors				Product specification
8-bit high-speed analog-to-digital converter					TDA8714
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
EFFECTIVE BITS (note 6; see Figs 7 and 13)
EB	effective bits
	TDA8714/4	fclk = 40 MHz
		fi = 4.43 MHz	−	7.75	−	bits
		fi = 7.5 MHz	−	7.6	−	bits
	effective bits
	TDA8714/6	fclk = 60 MHz
		fi = 4.43 MHz	−	7.7	−	bits
		fi = 7.5 MHz	−	7.55	−	bits
		fi = 10 MHz	−	7.4	−	bits
	effective bits
	TDA8714/7	fclk = 80 MHz
		fi = 4.43 MHz	−	7.7	−	bits
		fi = 7.5 MHz	−	7.5	−	bits
		fi = 10 MHz	−	7.2	−	bits
		fi = 15 MHz	−	6.3	−	bits
TWO-TONE (note 7)
TTIR	two-tone intermodulation rejection	fclk = 40 MHz	−	−56	−	dB
BIT ERROR RATE
BER	bit error rate	f = 40 MHz;	−	10−11	−	times/
		clk
		fi = 4.43 MHz;				samples
		VI = ±16 LSB at
		code 128
DIFFERENTIAL GAIN (note 8)
Gdiff	differential gain	fclk = 40 MHz;	−	0.6	−	%
		fi = 4.43 MHz
DIFFERENTIAL PHASE (note 8)
ϕdiff	differential phase	fclk = 40 MHz;	−	0.8	−	deg
		fi = 4.43 MHz
Timing (note 9; see Figs 3 and 5; fclk = 80 MHz)
tds	sampling delay time		−	−	2	ns
th	output hold time		5	−	−	ns
td	output delay time		−	10	11	ns
3-state output delay times (see Fig.4)
tdZH	enable HIGH		−	40	44	ns
tdZL	enable LOW		−	12	16	ns
tdHZ	disable HIGH		−	50	54	ns
tdLZ	disable LOW		−	10	14	ns

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