MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These inverters find primary use where low power dissipation and/or high noise immunity is desired. Each of the six inverters is a single stage to minimize propagation delays.
Features
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range
•Triple Diode Protection on All Inputs
•Pin−for−Pin Replacement for CD4069UB
•Meets JEDEC UB Specifications
•Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol |
Parameter |
Value |
Unit |
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VDD |
DC Supply Voltage Range |
−0.5 to +18.0 |
V |
Vin, Vout |
Input or Output Voltage Range |
−0.5 to V DD + 0.5 |
V |
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(DC or Transient) |
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Iin, Iout |
Input or Output Current |
± 10 |
mA |
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(DC or Transient) per Pin |
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PD |
Power Dissipation, per Package |
500 |
mW |
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(Note 1) |
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TA |
Ambient Temperature Range |
−55 to +125 |
°C |
Tstg |
Storage Temperature Range |
−65 to +150 |
°C |
TL |
Lead Temperature |
260 |
°C |
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(8−Second Soldering) |
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Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
1.Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
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MARKING |
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DIAGRAMS |
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14 |
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PDIP−14 |
MC14069UBCP |
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P SUFFIX |
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AWLYYWW |
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CASE 646 |
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1 |
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14 |
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SOIC−14 |
14069U |
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D SUFFIX |
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AWLYWW |
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CASE 751A |
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1 |
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14 |
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TSSOP−14 |
14 |
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DT SUFFIX |
069U |
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CASE 948G |
ALYW |
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1 |
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14 |
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SOEIAJ−14 |
MC14069UB |
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F SUFFIX |
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AWLYWW |
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CASE 965 |
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1 |
A |
= Assembly Location |
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WL, L = Wafer Lot |
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YY, Y |
= Year |
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WW, W = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
Semiconductor Components Industries, LLC, 2005 |
1 |
Publication Order Number: |
February, 2005 − Rev. 6 |
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MC14069UB/D |
MC14069UB
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IN 1 |
1 |
14 |
VDD |
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OUT 1 |
2 |
13 |
IN 6 |
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IN 2 |
3 |
12 |
OUT 6 |
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OUT 2 |
4 |
11 |
IN 5 |
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IN 3 |
5 |
10 |
OUT 5 |
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OUT 3 |
6 |
9 |
IN 4 |
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VSS |
7 |
8 |
OUT 4 |
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Figure 1. Pin Assignment |
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1 |
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2 |
VDD = PIN 14 |
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VDD |
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3 |
4 |
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VSS = PIN 7 |
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5 |
6 |
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INPUT* |
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OUTPUT |
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9 |
8 |
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11 |
10 |
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VSS |
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13 |
12 |
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*Double diode protection on all inputs not shown |
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(1/6 of circuit shown) |
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Figure 3. Logic Diagram |
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Figure 2. Circuit Schematic |
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VDD |
20 ns |
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20 ns |
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14 |
OUTPUT |
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90% |
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VDD |
PULSE |
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INPUT |
50% |
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10% |
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VSS |
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GENERATOR |
INPUT |
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tPHL |
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tPLH |
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7 |
VSS |
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CL |
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90% |
VOH |
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OUTPUT |
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50% |
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10% |
VOL |
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tTHL |
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tTLH |
Figure 4. Switching Time Test Circuit and Waveforms
ORDERING INFORMATION
Device |
Package |
Shipping² |
MC14069UBCP |
PDIP−14 |
500 Units / Tape & Ammo Box |
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MC14069UBCPG |
PDIP−14 |
500 Units / Tape & Ammo Box |
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(Pb−Free) |
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MC14069UBD |
SOIC−14 |
55 Units / Rail |
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MC14069UBDG |
SOIC−14 |
55 Units / Rail |
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(Pb−Free) |
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MC14069UBDR2 |
SOIC−14 |
2500 Units / Tape & Reel |
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MC14069UBDR2G |
SOIC−14 |
2500 Units / Tape & Reel |
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(Pb−Free) |
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MC14069UBDTR2 |
TSSOP−14* |
2500 Units / Tape & Reel |
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MC14069UBFEL |
SOEIAJ−14 |
2000 Units / Tape & Reel |
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MC14069UBFELG |
SOEIAJ−14 |
2000 Units / Tape & Reel |
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(Pb−Free) |
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²For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
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