ON Semiconductor MC74AC573, MC74ACT573 Technical data

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MC74AC573, MC74ACT573

Octal Buffer/Line Driver with 3−State Outputs

The MC74AC573/74ACT573 is a high−speed octal latch with buffered common Latch Enable (LE) and buffered common Output

Enable (OE) inputs.

The MC74AC573/74ACT573 is functionally identical to the http://onsemi.com MC74AC373/74ACT373 but has inputs and outputs on opposite sides.

Features												MARKING
• Inputs and Outputs on Opposite Sides of Package Allowing Easy												DIAGRAM
Interface with Microprocessors
• Useful as Input or Output Port for Microprocessors												MC74xxx573N
• Functionally Identical to MC74AC373/74ACT373												MC74xxx573N
• Functionally Identical to MC74AC373/74ACT373										20		AWLYYWWG
• 3−State Outputs for Bus Interfacing											1
• 3−State Outputs for Bus Interfacing
• Outputs Source/Sink 24 mA											PDIP−20
• ′ACT573 Has TTL Compatible Inputs											N SUFFIX
• ′ACT573 Has TTL Compatible Inputs											CASE 738
• Pb−Free Packages are Available*
VCC	O0	O1	O2	O3	O4	O5	O6	O7	LE			xxx573
20	19	18	17	16	15	14	13	12	11			xxx573
20	19	18	17	16	15	14	13	12	11			AWLYYWWG
											20
											1
											SO−20
											DW SUFFIX
											CASE 751D
1	2	3	4	5	6	7	8	9	10			xxx
1	2	3	4	5	6	7	8	9	10			573
											20	573
OE	D0	D1	D2	D3	D4	D5	D6	D7	GND		20	ALYW G
OE	D0	D1	D2	D3	D4	D5	D6	D7	GND		1	ALYW G

Figure 1. Pinout 20−Lead Packages Conductors

(Top View)

PIN ASSIGNMENT

FUNCTION

D0−D7

Data Inputs

Latch Enable Input

3−State Output Enable Input

O0−O7

3−State Latch Outputs

D0 D1 D2 D3 D4 D5 D6 D7

O0 O1 O2 O3 O4 O5 O6 O7

Figure 2. Logic Symbol

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

TSSOP−20

DT SUFFIX

CASE 948E

	74xxx573
20	AWLYWWG
20
	1

EIAJ−20

M SUFFIX

CASE 967

xxx	= AC or ACT
A	= Assembly Location
WL, L	= Wafer Lot
YY, Y	= Year
WW, W	= Work Week
G or G	= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.

♥ Semiconductor Components Industries, LLC, 2005	1	Publication Order Number:
September, 2005 − Rev. 7		MC74AC573/D

MC74AC573, MC74ACT573

TRUTH TABLE

	Inputs		Outputs

OE	LE	Dn	On
L	H	H	H
L	H	L	L
L	L	X	O0
H	X	X	Z

H = HIGH Voltage Level

L = LOW Voltage Level

Z = High Impedance X = Immaterial

O0 = Previous O0 before LOW−to−HIGH Transition of Clock

D0 D1 D2 D3

Functional Description

The MC74AC573/74ACT574 contains eight D−type latches with 3−state output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH−to−LOW transition of LE. The 3−state buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

D	D		D		D	D	D	D	D
	Q		Q	Q	Q	Q	Q	Q	Q
	LE	LE	LE		LE	LE	LE	LE	LE

NOTE: That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Figure 3. Logic Diagram

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MC74AC573, MC74ACT573

MAXIMUM RATINGS

Symbol	Parameter	Value	Unit

VCC	DC Supply Voltage (Referenced to GND)	−0.5 to +7.0	V
VIN	DC Input Voltage (Referenced to GND)	−0.5 to VCC +0.5	V
VOUT	DC Output Voltage (Referenced to GND)	−0.5 to VCC +0.5	V
IIN	DC Input Current, per Pin	±20	mA
IOUT	DC Output Sink/Source Current, per Pin	±50	mA
ICC	DC VCC or GND Current per Output Pin	±50	mA
Tstg	Storage Temperature	−65 to +150	°C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Typ	Max	Unit

VCC	Supply Voltage	′AC	2.0	5.0	6.0	V

		′ACT	4.5	5.0	5.5
		′ACT	4.5	5.0	5.5

VIN, VOUT	DC Input Voltage, Output Voltage (Ref. to GND)		0	−	VCC	V
		VCC @ 3.0 V	−	150	−
	Input Rise and Fall Time (Note 1)
tr, tf	Input Rise and Fall Time (Note 1)	VCC @ 4.5 V	−	40	−	ns/V
tr, tf	′AC Devices except Schmitt Inputs	VCC @ 4.5 V	−	40	−	ns/V
		VCC @ 5.5 V	−	25	−
tr, tf	Input Rise and Fall Time (Note 2)	VCC @ 4.5 V	−	10	−	ns/V
tr, tf	′ACT Devices except Schmitt Inputs	VCC @ 5.5 V	−	8.0	−	ns/V
	′ACT Devices except Schmitt Inputs

TJ	Junction Temperature (PDIP)		−	−	140	°C
TA	Operating Ambient Temperature Range		−40	25	85	°C
IOH	Output Current − High		−	−	−24	mA
IOL	Output Current − Low		−	−	24	mA

1.VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.

2.VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

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MC74AC573, MC74ACT573

DC CHARACTERISTICS

			74AC		74AC

		VCC			TA =
Symbol	Parameter	VCC	TA = +25°C		−40°C to	Unit		Conditions
Symbol	Parameter	(V)	TA = +25°C		−40°C to	Unit		Conditions
		(V)			+85°C
					+85°C

			Typ	Guaranteed Limits

VIH	Minimum High Level	3.0	1.5	2.1	2.1		VOUT = 0.1 V
	Input Voltage	4.5	2.25	3.15	3.15	V	or VCC − 0.1 V
		5.5	2.75	3.85	3.85

VIL	Maximum Low Level	3.0	1.5	0.9	0.9		VOUT = 0.1 V
	Input Voltage	4.5	2.25	1.35	1.35	V	or VCC − 0.1 V
		5.5	2.75	1.65	1.65

VOH	Minimum High Level	3.0	2.99	2.9	2.9		IOUT = −50 mA
	Output Voltage	4.5	4.49	4.4	4.4	V
		5.5	5.49	5.4	5.4

							*VIN = VIL or VIH
		3.0	−	2.56	2.46	V		−12 mA
		4.5	−	3.86	3.76	V	IOH	−24 mA
		4.5	−	3.86	3.76		IOH	−24 mA
		5.5	−	4.86	4.76			−24 mA

VOL	Maximum Low Level	3.0	0.002	0.1	0.1		IOUT = 50 mA
	Output Voltage	4.5	0.001	0.1	0.1	V
		5.5	0.001	0.1	0.1

							*VIN = VIL or VIH
		3.0	−	0.36	0.44	V		12 mA
		4.5	−	0.36	0.44	V	IOL	24 mA
		4.5	−	0.36	0.44		IOL	24 mA
		5.5	−	0.36	0.44			24 mA

IIN	Maximum Input	5.5	−	±0.1	±1.0	mA	VI = VCC, GND
	Leakage Current	5.5	−	±0.1	±1.0	mA	VI = VCC, GND

IOZ	Maximum			±0.5	±5.0		VI (OE) = VIL, VIH
	3−State	5.5	−	±0.5	±5.0	mA	VI = VCC, GND
	Current						VO = VCC, GND
IOLD	†Minimum Dynamic	5.5	−	−	75	mA	VOLD = 1.65 V Max
	Output Current
IOHD	Output Current	5.5	−	−	−75	mA	VOHD = 3.85 V Min
IOHD		5.5	−	−	−75	mA	VOHD = 3.85 V Min
ICC	Maximum Quiescent	5.5	−	8.0	80	mA	VIN = VCC or GND
	Supply Current	5.5	−	8.0	80	mA	VIN = VCC or GND

NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. *All outputs loaded; thresholds on input associated with output under test.

†Maximum test duration 2.0 ms, one output loaded at a time.

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