Fairchild Semiconductor DM74ALS273WMX, DM74ALS273WM, DM74ALS273SJX, DM74ALS273SJ, DM74ALS273N Datasheet

April 1984

Revised February 2000

DM74ALS273

Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.

Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

Features

■Switching specifications at 50 pF

■Switching specifications guaranteed over full temperature and VCC range

■Buffer-type outputs and improved AC offer significant advantage over DM74LS273.

■Advanced oxide-isolated, ion-implanted Schottky TTL process

■Functionally and pin-for-pin compatible with DM74LS273.

Ordering Code:

Order Number	Package Number	Package Description
DM74ALS273WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS273SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS273MSA	MSA20	20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS273N	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Clear with Flop-Flip Triggered-Edge Type-D Octal DM74ALS273

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DM74ALS273

Function Table					Logic Diagram
		(Each Flip-Flop)
		Inputs		Output
	Clear	Clock	D	Q
	L	X	X	L
	H	−	H	H
	H	−	L	L
	H	L	X	Q0
L = LOW State

H = HIGH State

X = Don’t Care

− = Positive Edge Transition

Q0 = Previous Condition of Q

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Absolute Maximum Ratings(Note 1)

Supply Voltage	7V
Input Voltage	7V
Operating Free Air Temperature Range	0°C to +70°C
Storage Temperature Range	−65°C to +150°C
Typical θJA
N Package	60.0°C/W
M Package	79.0°C/W

Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol	Parameter		Min	Nom	Max	Units
VCC	Supply Voltage		4.5	5	5.5	V
VIH	HIGH Level Input Voltage		2			V
VIL	LOW Level Input Voltage				0.8	V
IOH	HIGH Level Output Current				−2.6	mA
IOL	LOW Level Output Current				24	mA
fCLK	Clock Frequency		0		35	MHz
tW(CLK)	Width of Clock Pulse	HIGH	14			ns
		LOW	14			ns
tW	Width of Clear Pulse	LOW	10			ns
tSU	Data Setup Time (Note 2)		10−			ns
		Clear Inactive	15−
tH	Data Hold Time		0−			ns
TA	Free Air Operating Temperature		0		70	°C

Note 2: The (−) arrow indicates the positive edge of the Clock is used for reference.

Electrical Characteristics

over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.

Symbol	Parameter	Conditions		Min	Typ	Max	Units
VIK	Input Clamp Voltage	VCC = 4.5V, II = −18 mA				−1.5	V
VOH	HIGH Level	VCC = 4.5V	IOH = −2.6 mA	2.4	3.3		V
	Output Voltage	VCC = 4.5V to 5.5V	IOH = −400 μA	VCC − 2			V
VOL	LOW Level	VCC = 4.5V	IOL = 12 mA		0.25	0.4	V
	Output Voltage		IOL = 24 mA		0.35	0.5	V
II	Input Current @ Maximum Input Voltage	VCC = 5.5V, VIH = 7V				0.1	mA
IIH	HIGH Level Input Current	VCC = 5.5V, VIH = 2.7V				20	μA
IIL	LOW Level Input Current	VCC = 5.5V, VIL = 0.4V				−0.2	mA
IO	Output Drive Current	VCC = 5.5V	VO = 2.25V	−30		−112	mA
ICC	Supply Current	VCC = 5.5V	Outputs HIGH		11	20	mA
		Outputs OPEN	Outputs LOW		19	29	mA

Switching Characteristics

over recommended operating free air temperature range.

Symbol	Parameter	Conditions	From	To	Min	Max	Units
fMAX	Maximum Clock Frequency	VCC = 4.5V to 5.5V			35		MHz
tPHL	Propagation Delay Time	RL = 500Ω	Clear	Any Q	4	18	ns
	HIGH-to-LOW Level Output	CL = 50 pF
tPLH	Propagation Delay Time		Clock	Any Q	2	12	ns
	LOW-to-HIGH Level Output
tPHL	Propagation Delay Time		Clock	Any Q	3	15	ns
	HIGH-to-LOW Level Output

DM74ALS273

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