OKI MSM5416272-70GS-K, MSM5416272-50GS-K, MSM5416272-60GS-K Datasheet

E2L0020-17-Y1

This version: Jan. 1998

¡SemiconductorSemiconductor MSM5416272

Previous version: Dec. 1996

MSM5416272

262,144-Word ´ 16-Bit Multiport DRAM

DESCRIPTION

The MSM5416272 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit dynamic RAM, and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and asynchronously.

It supports three types of operations: random access to RAM port, high speed serial access to SAM port, and bidirectional transfer of data between any selected row in the RAM port and the SAM port. In addition to the conventional multiport DRAM operating modes, the MSM5416272 features block write and flash write functions on the RAM port, and a split data transfer capability on the SAM port. The SAM port requires no refresh operation because it uses static CMOS flip-flops.

FEATURES

• Single power supply: 5 V ±10%	• RAS only refresh
• Full TTL compatibility	• CAS before RAS refresh
• Multiport organization	• Hidden refresh
RAM : 256K word ´ 16 bits	• Serial read/write
SAM : 512 word ´ 16 bits	• 512 tap location
• Fast page mode	• Bidirectional data transfer
• Write per bit	• Split transfer
• Byte read/write	• Masked write transfer
• Masked flash write	• Refresh: 512 cycles/8 ms

•Masked block write (8 columns)

•Package:

64-pin 525 mil plastic SSOP (SSOP64-P-525-0.80-K) (Product : MSM5416272-xxGS-K) xx indicates speed rank.

PRODUCT FAMILY

	Family	Access Time		Cycle Time		Power Dissipation
		RAM	SAM	RAM	SAM	Operating	Standby
	MSM5416272-50	50 ns	17 ns	110 ns	20 ns	180 mA	8 mA
	MSM5416272-60	60 ns	18 ns	120 ns	22 ns	170 mA	8 mA
	MSM5416272-70	70 ns	20 ns	140 ns	22 ns	160 mA	8 mA

1/37

¡ Semiconductor

MSM5416272

PIN CONFIGURATION (TOP VIEW)

VCC			64	SC
	1
TRG			63	SE
	2
VSS			62	VSS
	3
SDQ0			61	SDQ15
	4
DQ0			60	DQ15
	5
SDQ1			59	SDQ14
	6
DQ1			58	DQ14
	7
VCC			57	VCC
	8
SDQ2	9		56	SDQ13
DQ2			55	DQ13
	10
SDQ3			54	SDQ12
	11
DQ3			53	DQ12
	12
VSS			52	VSS
	13
SDQ4			51	SDQ11
	14
DQ4			50	DQ11
	15
SDQ5			49	SDQ10
	16
DQ5			48	DQ10
	17
VCC			47	VCC
	18
SDQ6			46	SDQ9
	19
DQ6			45	DQ9
	20
SDQ7			44	SDQ8
	21
DQ7			43	DQ8
	22
VSS			42	VSS
	23
CASL			41	DSF
	24
WE			40	NC
	25
RAS			39	CASU
	26
A8			38	QSF
	27
A7			37	A0
	28
A6			36	A1
	29
A5			35	A2
	30
A4			34	A3
	31
VCC			33	VSS
	32

64-Pin Plastic SSOP

Pin Name	Function	Pin Name	Function
A0 - A8	Address Input	SC	Serial Clock
DQ0 - DQ15	RAM Inputs/Outputs	SE	SAM Port Enable
SDQ0 - SDQ15	SAM Inputs/Outputs	DSF	Special Function Input
RAS	Row Address Strobe	QSF	Special Function Output
CASL	Column Address Strobe Lower	VCC	Power Supply (5 V)
CASU	Column Address Strobe Upper	VSS	Ground (0 V)
WE	Write Enable	NC	No Connection
TRG	Transfer/Output Enable

Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.

2/37

Column				Block Write	Column Mask
Address		Column Decoder
				Control	Register
Buffer
					RAM Input
		Sense Amp.		I/O Control
					Color Register
					Buffer
					Mask Register
	Row				RAM Output
Row		512 ´ 512	´ 16		Buffer
Buffer	Decoder			Control
Address		RAM ARRAY		Flash Write
A0 - A8				SAM Input
Refresh		Gate	Gate	Buffer
Counter
		SAM	SAM		SDQ 0 - 15
				SAM Output	Timing
				Buffer
		Serial Decoder			Generator
SAM	SAM Address
Address					QSF
		Counter
Buffer
		SAM Stop		SE
		Control

3/37

DQ 0 - 15

RAS

CASU / CASL

TRG WE

DSF

SC

SE

VCC

VSS

DIAGRAM BLOCK

Semiconductor ¡

MSM5416272

¡ Semiconductor

MSM5416272

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

				(Note: 1)
Parameter	Symbol	Condition	Rating	Unit
Input Output Voltage	VT	Ta = 25°C	–1.0 to 7.0	V
Output Current	IOS	Ta = 25°C	50	mA
Power Dissipation	PD	Ta = 25°C	1	W
Operating Temperature	Topr	—	0 to 70	°C
Storage Temperature	Tstg	—	–55 to 150	°C

Recommended Operating Conditions

(Ta = 0°C to 70°C) (Note: 2)

Parameter	Symbol	Min.	Typ.	Max.	Unit
Power Supply Voltage	VCC	4.5	5.0	5.5	V
Input High Voltage	VIH	2.4	—	6.5	V
Input Low Voltage	VIL	–1.0	—	0.8	V

Capacitance

(VCC = 5 V ±10%, f = 1 MHz, Ta = 25°C)

Parameter	Symbol	Min.	Max.	Unit
Input Capacitance	Ci	—	6	pF
Input/Output Capacitance	Cio	—	7	pF
Output Capacitance	Co(QSF)	—	7	pF

Note: This parameter is periodically sampled and is not 100% tested.

DC Characteristics 1

	Parameter	Symbol	Condition	Min.	Max.	Unit
	Output "H" Level Voltage	VOH	IOH = –2 mA	2.4	—	V
	Output "L" Level Voltage	VOL	IOL = 2 mA	—	0.4
			0 £ VIN £ VCC
	Input Leakage Current	ILI	All other pins not	–10	10
			under test = 0 V			mA
	Output Leakage Current	ILO	0 £ VOUT £ 5.5 V	–10	10
			Output Disable

4/37

	¡ Semiconductor					MSM5416272
	DC Characteristics 2
				(VCC = 5 V ±10%, Ta = 0°C to 70°C)
	Item (RAM)	SAM	Symbol	-50	-60	-70	Unit	Note
				Max.	Max.	Max.
	Operating Current	Standby	ICC1	140	130	120		3, 4
	(RAS, CAS Cycling, tRC = tRC min.)	Active	ICC1A	180	170	160		17
	Standby Current	Standby	ICC2	8	8	8
	(RAS, CAS = VIH)	Active	ICC2A	60	55	55		3, 4
	RAS Only Refresh Current	Standby	ICC3	140	130	120		3, 4
	(RAS Cycling, CAS = VIH, tRC = tRC min.)	Active	ICC3A	180	170	160		17
	Page Mode Current	Standby	ICC4	150	140	130		3, 4
	(RAS = VIL, CAS Cycling, tPC = tPC min.)	Active	ICC4A	200	190	180	mA	18
	CAS before RAS Refresh Current	Standby	ICC5	120	110	100		3, 4
	(RAS Cycling, CAS before RAS, tRC = tRCmin.)	Active	ICC5A	160	150	140		3, 4
	Data Transfer Current	Standby	ICC6	130	120	110		3, 4
	(RAS, CAS Cycling, tRC = tRC min.)	Active	ICC6A	170	160	150		17
	Flash Write Current	Standby	ICC7	130	120	110		3, 4
	(RAS, CAS Cycling, tRC = tRC min.)	Active	ICC7A	170	160	150		3, 4
	Block Write Current	Standby	ICC8	130	120	110		3, 4
	(RAS, CAS Cycling, tRC = tRC min.)	Active	ICC8A	170	160	150		3, 4

5/37

	¡ Semiconductor							MSM5416272
	AC Characteristics (1/3)
	Parameter	Symbol	-50		-60		-70		Unit	Note
			Min.	Max.	Min.	Max.	Min.	Max.
	Random Read or Write Cycle Time	tRC	84	—	104	—	124	—	ns
	Read Modify Write Cycle	tRWC	135	—	140	—	170	—	ns
	Fast Page Mode Cycle Time	tPC	25	—	30	—	35	—	ns
	Fast Page Mode Read Modify Write Cycle Time	tPRWC	72	—	76	—	81	—	ns
	Access Time from RAS	tRAC	—	50	—	60	—	70	ns	8, 14
	Access Time from Column Address	tAA	—	25	—	30	—	35	ns	8, 14
	Access Time from CAS	tCAC	—	15	—	15	—	20	ns	8, 15
	Access Time from CAS Precharge	tCPA	—	30	—	35	—	40	ns	8, 15
	Output Buffer Turn-off Delay	tOFF	0	12	0	15	0	17	ns	10
	Transition Time (Rise and Fall)	tT	2	35	2	35	2	35	ns	7
	RAS Precharge Time	tRP	30	—	40	—	50	—	ns
	RAS Pulse Width	tRAS	50	10k	60	10k	70	10k	ns
	RAS Pulse Width (Fast Page Mode Only)	tRASP	50	100k	60	100k	70	100k	ns
	RAS Hold Time	tRSH	15	—	15	—	20	—	ns
	CAS Hold Time	tCSH	45	—	45	—	55	—	ns
	CAS Pulse Width	tCAS	15	10k	15	10k	15	10k	ns
	RAS to CAS Delay Time	tRCD	15	35	15	42	15	50	ns	14
	RAS to Column Address Delay Time	tRAD	12	25	12	30	12	35	ns	14
	Column Address to RAS Lead Time	tRAL	25	—	30	—	35	—	ns
	CAS to RAS Precharge Time	tCRP	5	—	5	—	10	—	ns
	CAS Precharge Time (Fast Page Mode)	tCP	6	—	10	—	10	—	ns
	Row Address Set-up Time	tASR	0	—	0	—	0	—	ns
	Row Address Hold Time	tRAH	8	—	10	—	10	—	ns
	Column Address Set-up Time	tASC	0	—	0	—	0	—	ns
	Column Address Hold Time	tCAH	8	—	10	—	10	—	ns
	Column Address Hold Time referenced to RAS	tAR	40	—	50	—	55	—	ns
	Read Command Set-up Time	tRCS	0	—	0	—	0	—	ns
	Read Command Hold Time	tRCH	0	—	0	—	0	—	ns	11
	Read Command Hold Time referenced to RAS	tRRH	0	—	0	—	0	—	ns	11
	Write Command Set-up Time	tWCS	0	—	0	—	0	—	ns	13
	Write Command Hold Time	tWCH	8	—	10	—	10	—	ns
	Write Command Hold Time referenced to RAS	tWCR	40	—	50	—	55	—	ns
	Write Command Pulse Width	tWP	8	—	10	—	10	—	ns
	Write Command to RAS Lead Time	tRWL	12	—	15	—	15	—	ns
	Write Command to CAS Lead Time	tCWL	12	—	15	—	15	—	ns

6/37

	¡ Semiconductor									MSM5416272
	AC Characteristics (2/3)
	Parameter	Symbol		-50			-60		-70		Unit	Note
			Min.		Max.	Min.	Max.	Min.		Max.
	Data Set-up Time	tDS	0		—	0	—	0		—	ns	12
	Data Hold Time	tDH	8		—	10	—	12		—	ns	12
	Data Hold Time referenced to RAS	tDHR	40		—	50	—	55		—	ns
	RAS to WE Delay Time	tRWD	70		—	80	—	90		—	ns	13
	Column Address to WE Delay Time	tAWD	45		—	50	—	55		—	ns	13
	CAS to WE Delay Time	tCWD	30		—	35	—	40		—	ns	13
	Data to CAS Delay Time	tDZC	0		—	0	—	0		—	ns
	Data to TRG Delay Time	tDZO	0		—	0	—	0		—	ns
	Access Time from TRG	tOEA	—		15	—	15	—		20	ns
	Output Buffer Turn-off Delay from TRG	tOEZ	0		12	0	15	0		15	ns
	TRG Command Hold Time	tOEH	8		—	10	—	10		—	ns
	RAS Hold Time referenced to TRG	tROH	10		—	10	—	15		—	ns
	CAS Set-up Time for CAS before RAS Cycle	tCSR	5		—	5	—	5		—	ns
	CAS Hold Time for CAS before RAS Cycle	tCHR	8		—	10	—	10		—	ns
	RAS Precharge to CAS Active Time	tRPC	0		—	0	—	0		—	ns
	Refresh Period	tREF	—		8	—	8	—		8	ms
	WE Set-up Time	tWSR	0		—	0	—	0		—	ns
	WE Hold Time	tRWH	8		—	10	—	10		—	ns
	DSF Set-up Time referenced to RAS	tFSR	0		—	0	—	0		—	ns
	DSF Hold Time referenced to RAS (1)	tRFH	8		—	10	—	10		—	ns
	DSF Hold Time referenced to RAS (2)	tFHR	40		—	50	—	55		—	ns
	DSF Set-up Time referenced to CAS	tFSC	0		—	0	—	0		—	ns
	DSF Hold Time referenced to CAS	tCFH	8		—	10	—	10		—	ns
	Write Per Bit Mask Data Set-up Time	tMS	0		—	0	—	0		—	ns
	Write Per Bit Mask Data Hold Time	tMH	8		—	10	—	10		—	ns
	TRG High Set-up Time	tTHS	0		—	0	—	0		—	ns
	TRG High Hold Time	tTHH	8		—	10	—	10		—	ns
	TRG Low Set-up Time	tTLS	0		—	0	—	0		—	ns
	TRG Low Hold Time	tTLH	8		10k	10	10k	10		10k	ns
	TRG Low Hold Time referenced to RAS	tRTH	40		10k	50	10k	60		10k	ns
	TRG Low Hold Time referenced to Column Address	tATH	20		—	20	—	25		—	ns
	TRG Low Hold Time referenced to CAS	tCTH	15		—	15	—	20		—	ns

7/37

¡ Semiconductor										MSM5416272
AC Characteristics (3/3)
Parameter	Symbol		-50		-60				-70		Unit	Note
		Min.		Max.	Min.	Max.		Min.		Max.
TRG to RAS Precharge Time	tTRP	40		—	40		—	50		—	ns
TRG Precharge Time	tTP	15		—	20		—	20		—	ns
RAS to First SC Delay Time (Read Transfer)	tRSD	50		—	60		—	70		—	ns
Column Address to First SC Delay Time	tASD	25		—	30		—	35		—	ns
CAS to First SC Delay Time (Read Transfer)	tCSD	20		—	20		—	20		—	ns
Last SC to TRG Lead Time	tTSL	5		—	5		—	5		—	ns
TRG to First SC Delay Time (Read Transfer)	tTSD	10		—	10		—	10		—	ns
Last SC to RAS Set-up Time (Serial Input)	tSRS	20		—	20		—	25		—	ns
Serial Output Buffer Turn-off Delay from RAS	tSDZ	10		30	10		30	10		40	ns	10
SC Cycle Time	tSCC	18		—	18		—	20		—	ns
SC Pulse Width (SC High Time)	tSC	5		—	5		—	5		—	ns
SC Precharge Time (SC Low Time)	tSCP	5		—	5		—	5		—	ns
Access Time from SC	tSCA	—		15	—		15	—		17	ns	9
Serial Output Hold Time from SC	tSOH	3		—	3		—	5		—	ns	19
Access Time from SE	tSEA	—		15	—		15	—		17	ns	9
SE Pulse Width	tSE	10		—	10		—	10		—	ns
SE Precharge Time	tSEP	10		—	10		—	10		—	ns
Serial Output Buffer Turn-off Delay from SE	tSEZ	0		14	0		15	0		15	ns	10
Split Transfer Set-up Time	tSTS	20		—	20		—	25		—	ns
Split Transfer Hold Time	tSTH	20		—	20		—	25		—	ns
SC-QSF Delay Time	tSQD	—		20	—		20	—		25	ns
TRG-QSF Delay Time	tTQD	—		20	—		20	—		25	ns
CAS-QSF Delay Time	tCQD	—		30	—		30	—		35	ns
RAS-QSF Delay Time	tRQD	—		65	—		70	—		75	ns
RAS to Serial Input Delay Time	tSDD	30		—	30		—	40		—	ns
Serial Input Set-up Time	tSDS	0		—	0		—	0		—	ns
Serial Input Hold Time	tSDH	8		—	10		—	10		—	ns
Serial Input to SE Delay Time	tSZE	0		—	0		—	0		—	ns
Serial Input to First SC Delay Time	tSZS	0		—	0		—	0		—	ns
Serial Write Enable Set-up Time	tSWS	0		—	0		—	0		—	ns
Serial Write Enable Hold Time	tSWH	8		—	10		—	10		—	ns
Serial Write Disable Set-up Time	tSWIS	0		—	0		—	0		—	ns
Serial Write Disable Hold Time	tSWIH	8		—	10		—	10		—	ns

8/37

¡ Semiconductor

MSM5416272

Notes: 1. Exposure beyond the "Absolute Maximum Ratings" may cause permanent damage to the device.

2.All voltages are referenced to VSS.

3.These parameters depend on the cycle rate.

4.These parameters depend on output loading. Specified values are obtained with the output open.

5.An initial pause of 200 ms is required after power up followed by any 8 RAS cycles (TRG = "high") and any 8 SC cycles before proper device operation is achieved. In the case of using an internal refresh counter, a minimum of 8 CAS before RAS cycles instead of 8 RAS cycles are required.

6.AC measurements assume tT = 5 ns.

7.VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL.

8.RAM port outputs are measured with a load equivalent to 1 TTL load and 50 pF. DOUT reference levels : VOH/VOL = 2.0 V/0.8 V.

9.SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF. DOUT reference levels : VOH/VOL = 2.0 V/0.8 V.

10.tOFF (Max.), tOEZ (Max.), tSDZ (Max.) and tSEZ (Max.) define the time at which the outputs achieve the open circuit condition, and are not referenced to output voltage levels. This parameter is sampled and not 100% tested.

11.Either tRCH or tRRH must be satisfied for a read cycle.

12.These parameters are referenced to CAS leading edge of early write cycles, and to WE leading edge in TRG controlled write cycles and read modify write cycles.

13.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only.

If tWCS ≥ tWCS (Min.), the cycle is an early write cycle, and the data out pin will remain open circuit throughout the entire cycle; If tRWD ≥ tRWD (Min.), tCWD ≥ tCWD (Min.) and tAWD ≥ tAWD (Min.), the cycle is a read modify write cycle, and the data out will contain data read from the selected cell; If neither of the above sets of conditions are satisfied, the condition of the data out is indeterminate.

14.Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC.

15.Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA.

16.Input levels at the AC testing are 3.0 V/0 V.

17.Address (A0 - A8) may be changed two times or less while RAS = VIL.

18.Address (A0 - A8) may be changed once or less while CAS = VIH and RAS = VIL.

19.This is guaranteed by design. (tSOH/tCOH = tSCA/tCAC - output transition time) This parameter is not 100% tested.

9/37

¡ Semiconductor

MSM5416272

TIMING WAVEFORM

Read Cycle

tRC

tRAS

tRP

RAS

tCSH

tCRP

tRCD

tRSH

CASL

tCAS

tCSH

tCRP

tRCD

tRSH

tCAS

CASU			tAR
		tRAD		tRAL
	tASR	tRAH	tASC	tCAH
Address	Row			Column
			tFHR
	tFSR	tRFH	tFSC	tCFH
DSF
			tRCS	tRRH
WE				tRCH
				tCAC
				tOFF
				tAA

DQ0 - 7

Open

Valid Data

tRAC

DQ8 - 15

Open

Valid Data

tROH

TRG

tTHS

tTHH

tOEA

tOEZ

"H" or "L"

10/37

¡ Semiconductor

MSM5416272

Fast Page Mode Read Cycle

tRASP

tRP

RAS
			tCSH			tPC		tRSH
	tCRP	tRCD		tCAS	tCP	tCAS	tCP	tCAS
CASL
			tCSH			tPC		tRSH
	tCRP	tRCD		tCAS	tCP	tCAS	tCP	tCAS
CASU		tAR
								tRAL
		tRAD
	tASR	tRAH	tASC	tCAH	tASC	tCAH	tASC	tCAH
Address	Row		Column		Column		Column
		tFHR
	tFSR	tRFH	tFSC	tCFH	tFSC	tCFH	tFSC	tCFH
DSF

tRCS

tRCS

tRCH

WE

t

RCS

tRCH

tRCH

tRRH

tCAC

tCAC

tCAC

tAA

tAA

tAA

tOFF

tOFF

tOFF

Valid

Valid

Valid

DQ0 - 7

Open

Data

Data

Data

tRAC

tCPA

tCPA

Valid

Valid

Valid

DQ8 - 15

Open

Data

Data

Data

tOEZ

tTHS

tTHH

tOEA

TRG

"H" or "L"

11/37

¡ Semiconductor						MSM5416272
				Write Cycle Function Table
	RAS Falling Edge			CAS Falling Edge
Code	A	C	D	B	E	Function
	DSF	WE	DQ	DSF	DQ
RWM	0	0	Write Mask	0	Valid Data	Masked Write
BWM	0	0	Write Mask	1	Column Mask	Masked Block Write
FWM	1	0	Write Mask	X	X	Masked Flash Write
RW	0	1	X	0	Valid Data	Normal Write
BW	0	1	X	1	Column Mask	Block Write
LCR	1	1	X	1	Color Data	Load Color Register

WRITE MASK DATA: "Low" = Mask, "High" = No Mask

Column Mask Data

		DQ0 - 15	Column Mask Data
		DQ0	Column 0 (A0 = 0, A1 = 0, A2 = 0)
		DQ1	Column 1 (A0 = 1, A1 = 0, A2 = 0)
		DQ2	Column 2 (A0 = 0, A1 = 1, A2 = 0)
				Low : Mask
	Lower Byte	DQ3	Column 3 (A0 = 1, A1 = 1, A2 = 0)
				High : No Mask
		DQ4	Column 4 (A0 = 0, A1 = 0, A2 = 1)
		DQ5	Column 5 (A0 = 1, A1 = 0, A2 = 1)
		DQ6	Column 6 (A0 = 0, A1 = 1, A2 = 1)
		DQ7	Column 7 (A0 = 1, A1 = 1, A2 = 1)
		DQ8	Column 0 (A0 = 0, A1 = 0, A2 = 0)
		DQ9	Column 1 (A0 = 1, A1 = 0, A2 = 0)
		DQ10	Column 2 (A0 = 0, A1 = 1, A2 = 0)
				Low : Mask
	Upper Byte	DQ11	Column 3 (A0 = 1, A1 = 1, A2 = 0)
				High : No Mask
		DQ12	Column 4 (A0 = 0, A1 = 0, A2 = 1)
		DQ13	Column 5 (A0 = 1, A1 = 0, A2 = 1)
		DQ14	Column 6 (A0 = 0, A1 = 1, A2 = 1)
		DQ15	Column 7 (A0 = 1, A1 = 1, A2 = 1)

12/37