OKI MSM51V17405DSL-60TS-K, MSM51V17405D-70TS-K, MSM51V17405D-50TS-K, MSM51V17405DSL-60SJ, MSM51V17405DSL-50SJ Datasheet

	E2G0125-17-61	Preliminary
	¡ Semiconductor
		This version: Mar. 1998
		MSM51V17405D/DSL
	Semiconductor

MSM51V17405D/DSL

4,194,304-Word ´ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO

DESCRIPTION

TheMSM51V17405D/DSLisa4,194,304-word ´4-bitdynamicRAMfabricatedinOki'ssilicon-gate CMOS technology. The MSM51V17405D/DSL achieves high integration, high-speed operation, andlow-powerconsumptionbecauseOkimanufacturesthedeviceinaquadruple-layerpolysilicon/ double-layermetalCMOSprocess.TheMSM51V17405D/DSLisavailableina26/24-pinplasticSOJ or 26/24-pin plastic TSOP. The MSM51V17405DSL (the self-refresh version) is specially designed for lower-power applications.

FEATURES

•4,194,304-word ´ 4-bit configuration

•Single 3.3 V power supply, ±0.3 V tolerance

• Input : LVTTL compatible, low input capacitance

•Output : LVTTL compatible, 3-state

•Refresh : 2048 cycles/32 ms, 2048 cycles/128 ms (SL version)

•Fast page mode with EDO, read modify write capability

•CAS before RAS refresh, hidden refresh, RAS-only refresh capability

•CAS before RAS self-refresh capability (SL version)

•Multi-bit test mode capability

•Package options:

26/24-pin 300 mil plastic SOJ	(SOJ26/24-P-300-1.27) (Product : MSM51V17405D/DSL-xxSJ)
26/24-pin 300 mil plastic TSOP	(TSOPII26/24-P-300-1.27-K) (Product : MSM51V17405D/DSL-xxTS-K)
	xx indicates speed rank.

PRODUCT FAMILY

	Family	Access Time (Max.)				Cycle Time	Power Dissipation
						(Min.)
		tRAC	tAA	tCAC	tOEA		Operating (Max.)	Standby (Max.)
	MSM51V17405D/DSL-50	50 ns	25 ns	13 ns	13 ns	84 ns	360 mW	1.8 mW/
	MSM51V17405D/DSL-60	60 ns	30 ns	15 ns	15 ns	104 ns	324 mW
								0.72 mW (SL version)
	MSM51V17405D/DSL-70	70 ns	35 ns	20 ns	20 ns	124 ns	288 mW

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¡ Semiconductor

MSM51V17405D/DSL

PIN CONFIGURATION (TOP VIEW)
VCC	1	26	VSS	VCC	1	26	VSS
DQ1	2	25	DQ4	DQ1	2	25	DQ4
DQ2	3	24	DQ3	DQ2	3	24	DQ3
WE 4		23	CAS	WE 4		23	CAS
RAS	5	22	OE	RAS	5	22	OE
NC	6	21	A9	NC	6	21	A9
A10	8	19	A8	A10	8	19	A8
A0	9	18	A7	A0	9	18	A7
A1	10	17	A6	A1	10	17	A6
A2	11	16	A5	A2	11	16	A5
A3	12	15	A4	A3	12	15	A4
VCC 13		14	VSS	VCC 13		14	VSS
	26/24-Pin Plastic SOJ				26/24-Pin Plastic TSOP
						(K Type)

Pin Name	Function
A0 - A10	Address Input
RAS	Row Address Strobe
CAS	Column Address Strobe
DQ1 - DQ4	Data Input/Data Output
OE	Output Enable
WE	Write Enable
VCC	Power Supply (3.3 V)
VSS	Ground (0 V)
NC	No Connection

Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.

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¡ Semiconductor MSM51V17405D/DSL

BLOCK DIAGRAM

RAS			Timing
		Generator
							Timing
CAS						Generator
	Column						Write
11				11	Column		Clock	WE
	Address				Decoders		Generator		OE
	Buffers
							4	Output	4
								Buffers
	Internal		Refresh				I/O
A0 - A10					Sense
	Address					4			4 DQ1 - DQ4
			Control Clock		Amplifiers		4
	Counter						Selector	Input
							4		4
								Buffers
	Row		Row	Word	Memory
11	Address	11
			De-
				Drivers	Cells
	Buffers
			coders

VCC

On Chip

VBB Generator

VSS

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¡ Semiconductor MSM51V17405D/DSL

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

	Parameter	Symbol		Rating			Unit
	Voltage on Any Pin Relative to VSS	VT		–0.5 to 4.6			V
	Short Circuit Output Current	IOS		50			mA
	Power Dissipation	PD*		1			W
	Operating Temperature	Topr		0 to 70			°C
	Storage Temperature	Tstg		–55 to 150			°C
		*: Ta = 25°C
Recommended Operating Conditions						(Ta = 0°C to 70°C)
	Parameter	Symbol	Min.	Typ.		Max.	Unit
	Power Supply Voltage	VCC	3.0	3.3		3.6	V
		VSS	0	0		0	V
	Input High Voltage	VIH	2.0	—		VCC + 0.3	V
	Input Low Voltage	VIL	–0.3	—		0.8	V
Capacitance				(VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz)
	Parameter	Symbol	Typ.			Max.	Unit
	Input Capacitance (A0 - A10)	CIN1	—			5	pF
	Input Capacitance (RAS, CAS, WE, OE)	CIN2	—			7	pF
	Output Capacitance (DQ1 - DQ4)	CI/O	—			7	pF

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¡ Semiconductor								MSM51V17405D/DSL
DC Characteristics						(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C)
			MSM51V17405MSM51V17405MSM51V17405
Parameter	Symbol	Condition	D/DSL-50		D/DSL-60			D/DSL-70		Unit	Note
			Min.	Max. Min.			Max. Min.		Max.
Output High Voltage	VOH	IOH = –2.0 mA	2.4	VCC	2.4		VCC	2.4	VCC	V
Output Low Voltage	VOL	IOL = 2.0 mA	0	0.4	0		0.4	0	0.4	V
		0 V £ VI £ VCC + 0.3 V;
Input Leakage Current	ILI	All other pins not	–10	10	–10		10	–10	10	mA
		under test = 0 V
Output Leakage Current	ILO	DQ disable	–10	10	–10		10	–10	10	mA
		0 V £ VO £ VCC
Average Power		RAS, CAS cycling,
Supply Current	ICC1		—	100	—		90	—	80	mA	1, 2
		tRC = Min.
(Operating)
Power Supply		RAS, CAS = VIH	—	2	—		2	—	2	mA	1
	ICC2	RAS, CAS	—	0.5	—		0.5	—	0.5
Current (Standby)
		³ VCC –0.2 V	—	200	—		200	—	200	mA	1, 5
Average Power		RAS cycling,
Supply Current	ICC3	CAS = VIH,	—	100	—		90	—	80	mA	1, 2
(RAS-only Refresh)		tRC = Min.
Power Supply		RAS = VIH,
	ICC5	CAS = VIL,	—	5	—		5	—	5	mA	1
Current (Standby)
		DQ = enable
Average Power		RAS cycling,
Supply Current	ICC6		—	100	—		90	—	80	mA	1, 2
		CAS before RAS
(CAS before RAS Refresh)
Average Power		RAS = VIL,
Supply Current	ICC7	CAS cycling,	—	100	—		90	—	80	mA	1, 3
(Fast Page Mode)		tHPC = Min.
Average Power		tRC = 62.5 ms,									1, 4,
Supply Current	ICC10	CAS before RAS,	—	300	—		300	—	300	mA
											5
(Battery Backup)		tRAS £ 1 ms
Average Power
Supply Current	ICCS	RAS £ 0.2 V,	—	300	—		300	—	300	mA	1, 5
(CAS before RAS		CAS £ 0.2 V
Self-Refresh)

Notes : 1. ICC Max. is specified as ICC for output open condition.

2.The address can be changed once or less while RAS = VIL.

3.The address can be changed once or less while CAS = VIH.

4.VCC – 0.2 V £ VIH £ VCC + 0.3 V, –0.3 V £ VIL £ 0.2 V.

5.SL version.

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¡ Semiconductor						MSM51V17405D/DSL
AC Characteristics (1/2)
		(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13
		MSM51V17405MSM51V17405MSM51V17405
Parameter	Symbol	D/DSL-50		D/DSL-60		D/DSL-70		Unit	Note
		Min.	Max. Min.		Max. Min.		Max.
Random Read or Write Cycle Time	tRC	84	—	104	—	124	—	ns
Read Modify Write Cycle Time	tRWC	110	—	135	—	160	—	ns
Fast Page Mode Cycle Time	tHPC	20	—	25	—	30	—	ns
Fast Page Mode Read Modify Write	tHPRWC	58	—	68	—	78	—	ns
Cycle Time
Access Time from RAS	tRAC	—	50	—	60	—	70	ns	4, 5, 6
Access Time from CAS	tCAC	—	13	—	15	—	20	ns	4, 5
Access Time from Column Address	tAA	—	25	—	30	—	35	ns	4, 6
Access Time from CAS Precharge	tCPA	—	30	—	35	—	40	ns	4
Access Time from OE	tOEA	—	13	—	15	—	20	ns	4
Output Low Impedance Time from CAS	tCLZ	0	—	0	—	0	—	ns	4
Data Output Hold After CAS Low	tDOH	5	—	5	—	5	—	ns
CAS to Data Output Buffer Turn-off Delay Time	tCEZ	0	13	0	15	0	20	ns	7, 8
RAS to Data Output Buffer Turn-off Delay Time	tREZ	0	13	0	15	0	20	ns	7, 8
OE to Data Output Buffer Turn-off Delay Time	tOEZ	0	13	0	15	0	20	ns	7
WE to Data Output Buffer Turn-off Delay Time	tWEZ	0	13	0	15	0	20	ns	7
Transition Time	tT	1	50	1	50	1	50	ns	3
Refresh Period	tREF	—	32	—	32	—	32	ms
Refresh Period (SL version)	tREF	—	128	—	128	—	128	ms	14
RAS Precharge Time	tRP	30	—	40	—	50	—	ns
RAS Pulse Width	tRAS	50	10,000	60	10,000	70	10,000	ns
RAS Pulse Width (Fast Page Mode with EDO)	tRASP	50	100,000	60	100,000	70	100,000	ns
RAS Hold Time	tRSH	7	—	10	—	13	—	ns
RAS Hold Time referenced to OE	tROH	7	—	10	—	13	—	ns
CAS Precharge Time (Fast Page Mode with EDO)	tCP	7	—	10	—	10	—	ns
CAS Pulse Width	tCAS	7	10,000	10	10,000	13	10,000	ns
CAS Hold Time	tCSH	35	—	40	—	45	—	ns
CAS to RAS Precharge Time	tCRP	5	—	5	—	5	—	ns
RAS Hold Time from CAS Precharge	tRHCP	30	—	35	—	40	—	ns
OE Hold Time from CAS (DQ Disable)	tCHO	5	—	5	—	5	—	ns
RAS to CAS Delay Time	tRCD	11	37	14	45	14	50	ns	5
RAS to Column Address Delay Time	tRAD	9	25	12	30	12	35	ns	6
Row Address Set-up Time	tASR	0	—	0	—	0	—	ns
Row Address Hold Time	tRAH	7	—	10	—	10	—	ns
Column Address Set-up Time	tASC	0	—	0	—	0	—	ns
Column Address Hold Time	tCAH	7	—	10	—	13	—	ns
Column Address to RAS Lead Time	tRAL	25	—	30	—	35	—	ns

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