E2L0013-17-Y1
This version: Jan. 1998
¡SemiconductorSemiconductor MSM514262
Previous version: Dec. 1996
MSM514262
262,144-Word ¥ 4-Bit Multiport DRAM
DESCRIPTION
The MSM514262 is an 1-Mbit CMOS multiport DRAM composed of a 262,144-word by 4-bit dynamic RAM and a 512-word by 4-bit SAM. Its RAM and SAM operate independently and asynchronously.
The MSM514262 supports three types of operation : random access to RAM port, high speed serial access to SAM port and bidirectional transfer of data between any selected row in the RAM port and the SAM port. In addition to the conventional multiport DRAM operating modes, the MSM514262 features the block write and flash write functions on the RAM port and a split data transfer capability on the SAM port. The SAM port requires no refresh operation because it uses static CMOS flip-flops.
FEATURES
•Single power supply: 5 V ±10%
•Full TTL compatibility
•Multiport organization
RAM: 256K word ¥ 4 bits
SAM: 512 word ¥ 4 bits
•Fast page mode
•Write per bit
•Masked flash write
•Masked block write
•RAS only refresh
•CAS before RAS refresh
•Hidden refresh
•Serial read/write
•512 tap location
•Bidirectional data transfer
•Split transfer
•Masked write transfer
•Refresh: 512 cycles/8 ms
•Package options:
28-pin 400 mil plastic ZIP |
(ZIP28-P-400-1.27) |
(Product : MSM514262-xxZS) |
28-pin 400 mil plastic SOJ |
(SOJ28-P-400-1.27) |
(Product : MSM514262-xxJS) |
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xx indicates speed rank. |
PRODUCT FAMILY
Family |
Access Time |
Cycle Time |
Power Dissipation |
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RAM |
SAM |
RAM |
SAM |
Operating |
Standby |
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MSM514262-70 |
70 ns |
25 ns |
140 ns |
30 ns |
120 mA |
8 mA |
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MSM514262-80 |
80 ns |
25 ns |
150 ns |
30 ns |
110 mA |
8 mA |
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MSM514262-10 |
100 ns |
25 ns |
180 ns |
30 ns |
100 mA |
8 mA |
1/45
¡ Semiconductor |
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MSM514262 |
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PIN CONFIGURATION (TOP VIEW) |
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DSF |
1 |
W3/IO3 |
SC |
1 |
28 |
VSS |
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2 |
SIO1 |
2 |
27 |
SIO4 |
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W4/IO4 |
3 |
SE |
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4 |
SIO2 |
3 |
26 |
SIO3 |
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SIO3 |
5 |
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SIO4 |
DT/OE |
4 |
25 |
SE |
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6 |
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VSS |
7 |
SC |
W1/IO1 |
5 |
24 |
W4/IO4 |
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8 |
W2/IO2 |
6 |
23 |
W3/IO3 |
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SIO1 |
9 |
SIO2 |
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10 |
WB/WE 7 |
22 |
DSF |
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DT/OE |
11 |
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W1/IO1 |
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CAS |
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W2/IO2 |
12 |
NC |
8 |
21 |
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13 |
WB/WE |
RAS 9 |
20 |
QSF |
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14 |
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NC |
15 |
RAS |
A8 |
10 |
19 |
A0 |
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16 |
A6 |
11 |
18 |
A1 |
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A8 |
17 |
A6 |
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18 |
A5 |
12 |
17 |
A2 |
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A5 |
19 |
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A4 |
A4 |
13 |
16 |
A3 |
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20 |
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VCC |
21 |
A7 |
VCC 14 |
15 |
A7 |
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22 |
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A3 |
23 |
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24 |
A2 |
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A1 |
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28-Pin Plastic SOJ |
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25 |
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26 |
A0 |
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QSF |
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27 |
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CAS |
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28 |
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28-Pin Plastic ZIP
Pin Name |
Function |
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A0 - A8 |
Address Input |
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RAS |
Row Address Strobe |
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CAS |
Column Address Strobe |
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DT/OE |
Transfer/Output Enable |
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WB/WE |
Mask/Write Enable |
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DSF |
Special Function Input |
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W1/IO1 - W4/IO4 |
RAM Inputs/Outputs |
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SC |
Serial Clock |
SE |
SAM Port Enable |
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SIO1 - SIO4 |
SAM Inputs/Ourputs |
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QSF |
Special Function Output |
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VCC |
Power Supply (5 V) |
VSS |
Ground (0 V) |
NC |
No Connection |
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2/45
A0 - A8
3/45
Column
Address
Buffer
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Row |
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Row |
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Decoder |
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Address |
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Buffer |
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Refresh |
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Counter |
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Column Decoder
Sense Amp.
512 ¥ 512 ¥ 4 RAM ARRAY
Gate Gate
SAM SAM
Serial Decoder
SAM
Address
SAM Address
Buffer
Counter
Block Write |
Column Mask |
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Register |
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Control |
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I/O Control |
Color Register |
RAM Input |
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Buffer |
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Mask Register |
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RAM Output |
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Buffer |
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Flash Write |
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Control |
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SAM Input |
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Buffer |
SIO1 |
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SAM Output |
- SIO4 |
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Timing |
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Buffer |
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Generator |
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QSF |
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W1/IO1
- W4/IO4
RAS
CAS
DT/OE WB/WE
DSF
SC
SE
VCC
VSS
DIAGRAM BLOCK |
Semiconductor ¡ |
MSM514262
¡ Semiconductor |
MSM514262 |
ELECTRICAL CHARACTERISTICS |
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Absolute Maximum Ratings |
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(Note: 16) |
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Parameter |
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Symbol |
Condition |
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Rating |
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Unit |
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Input Output Voltage |
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VT |
Ta = 25°C |
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–1.0 to 7.0 |
V |
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Output Current |
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IOS |
Ta = 25°C |
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50 |
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mA |
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Power Dissipation |
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PD |
Ta = 25°C |
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1 |
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W |
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Operating Temperature |
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Topr |
— |
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0 to 70 |
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°C |
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Storage Temperature |
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Tstg |
— |
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–55 to 150 |
°C |
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Recommended Operating Condition |
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(Ta = 0°C to 70°C) (Note: 17) |
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Parameter |
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Symbol |
Min. |
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Typ. |
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Max. |
Unit |
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Power Supply Voltage |
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VCC |
4.5 |
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5.0 |
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5.5 |
V |
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Input High Voltage |
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VIH |
2.4 |
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— |
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6.5 |
V |
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Input Low Voltage |
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VIL |
–1.0 |
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— |
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0.8 |
V |
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Capacitance |
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(VCC = 5 V ±10%, f = 1 MHz, Ta = 25°C) |
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Parameter |
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Symbol |
Min. |
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Max. |
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Unit |
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Input Capacitance |
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CI |
— |
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7 |
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pF |
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Input/Output Capacitance |
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CI/O |
— |
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9 |
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pF |
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Output Capacitance |
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CO(QSF) |
— |
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9 |
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pF |
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Note: |
This parameter is periodically sampled and is not 100% tested. |
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DC Characteristics 1 |
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Parameter |
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Symbol |
Condition |
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Min. |
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Max. |
Unit |
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Output "H" Level Voltage |
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VOH |
IOH = –2 mA |
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2.4 |
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— |
V |
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Output "L" Level Voltage |
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VOL |
IOL = 2 mA |
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— |
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0.4 |
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0 £ VIN £ VCC |
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Input Leakage Current |
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ILI |
All other pins not |
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–10 |
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10 |
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under test = 0 V |
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mA |
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Output Leakage Current |
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ILO |
0 £ VOUT £ 5.5 V |
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–10 |
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10 |
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Output Disable |
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4/45
¡ Semiconductor |
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MSM514262 |
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DC Characteristics 2 |
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(VCC = 5 V ±10%, Ta = 0°C to 70°C) |
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Item (RAM) |
SAM |
Symbol |
-70 |
-80 |
-10 |
Unit |
Note |
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Max. |
Max. |
Max. |
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Operating Current |
Standby |
ICC1 |
85 |
75 |
65 |
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1, 2 |
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(RAS, CAS Cycling, tRC = tRC min.) |
Active |
ICC1A |
120 |
110 |
100 |
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1, 2 |
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Standby Current |
Standby |
ICC2 |
8 |
8 |
8 |
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3 |
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(RAS, CAS = VIH) |
Active |
ICC2A |
50 |
45 |
40 |
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1, 2 |
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RAS Only Refresh Current |
Standby |
ICC3 |
85 |
75 |
65 |
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1, 2 |
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(RAS Cycling, CAS = VIH, tRC = tRC min.) |
Active |
ICC3A |
120 |
110 |
100 |
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1, 2 |
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Page Mode Current |
Standby |
ICC4 |
70 |
65 |
60 |
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1, 2 |
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(RAS = VIL, CAS Cycling, tPC = tPC min.) |
Active |
ICC4A |
120 |
110 |
100 |
mA |
1, 2 |
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CAS before RAS Refresh Current |
Standby |
ICC5 |
85 |
75 |
65 |
1, 2 |
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(RAS Cycling, CAS before RAS, tRC = tRC min.) |
Active |
ICC5A |
120 |
110 |
100 |
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1, 2 |
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Data Transfer Current |
Standby |
ICC6 |
85 |
75 |
65 |
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1, 2 |
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(RAS, CAS Cycling, tRC = tRC min.) |
Active |
ICC6A |
120 |
110 |
100 |
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1, 2 |
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Flash Write Current |
Standby |
ICC7 |
85 |
75 |
65 |
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1, 2 |
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(RAS, CAS Cycling, tRC = tRC min.) |
Active |
ICC7A |
120 |
110 |
100 |
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1, 2 |
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Block Write Current |
Standby |
ICC8 |
85 |
75 |
65 |
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1, 2 |
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(RAS, CAS Cycling, tRC = tRC min.) |
Active |
ICC8A |
120 |
110 |
100 |
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1, 2 |
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5/45
¡ Semiconductor |
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MSM514262 |
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AC Characteristics (1/3) |
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(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6 |
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Parameter |
Symbol |
-70 |
-80 |
-10 |
Unit |
Note |
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Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
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Random Read or Write Cycle Time |
tRC |
140 |
— |
150 |
— |
180 |
— |
ns |
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Read Modify Write Cycle Time |
tRWC |
195 |
— |
195 |
— |
235 |
— |
ns |
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Fast Page Mode Cycle Time |
tPC |
45 |
— |
50 |
— |
55 |
— |
ns |
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Fast Page Mode Read Modify Write Cycle Time |
tPRWC |
90 |
— |
90 |
— |
100 |
— |
ns |
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Access Time from RAS |
tRAC |
— |
70 |
— |
80 |
— |
100 |
ns |
7, 13 |
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Access Time from Column Address |
tAA |
— |
35 |
— |
40 |
— |
55 |
ns |
7, 13 |
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Access Time from CAS |
tCAC |
— |
20 |
— |
25 |
— |
25 |
ns |
7, 14 |
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Access Time from CAS Precharge |
tCPA |
— |
40 |
— |
45 |
— |
50 |
ns |
7, 14 |
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Output Buffer Turn-off Delay |
tOFF |
0 |
20 |
0 |
20 |
0 |
20 |
ns |
9 |
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Transition Time (Rise and Fall) |
tT |
3 |
35 |
3 |
35 |
3 |
35 |
ns |
6 |
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RAS Precharge Time |
tRP |
60 |
— |
60 |
— |
70 |
— |
ns |
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RAS Pulse Width |
tRAS |
70 |
10k |
80 |
10k |
100 |
10k |
ns |
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RAS Pulse Width (Fast Page Mode Only) |
tRASP |
70 |
100k |
80 |
100k |
100 |
100k |
ns |
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RAS Hold Time |
tRSH |
20 |
— |
25 |
— |
25 |
— |
ns |
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CAS Hold Time |
tCSH |
70 |
— |
80 |
— |
100 |
— |
ns |
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CAS Pulse Width |
tCAS |
20 |
10k |
25 |
10k |
25 |
10k |
ns |
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RAS to CAS Delay Time |
tRCD |
20 |
50 |
20 |
55 |
20 |
75 |
ns |
13 |
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RAS to Column Address Delay Time |
tRAD |
15 |
35 |
15 |
40 |
20 |
50 |
ns |
13 |
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Column Address to RAS Lead Time |
tRAL |
35 |
— |
40 |
— |
55 |
— |
ns |
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CAS to RAS Precharge Time |
tCRP |
10 |
— |
10 |
— |
10 |
— |
ns |
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CAS Precharge Time |
tCPN |
10 |
— |
10 |
— |
10 |
— |
ns |
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CAS Precharge Time (Fast Page Mode) |
tCP |
10 |
— |
10 |
— |
10 |
— |
ns |
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Row Address Set-up Time |
tASR |
0 |
— |
0 |
— |
0 |
— |
ns |
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Row Address Hold Time |
tRAH |
10 |
— |
10 |
— |
10 |
— |
ns |
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Column Address Set-up Time |
tASC |
0 |
— |
0 |
— |
0 |
— |
ns |
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Column Address Hold Time |
tCAH |
15 |
— |
15 |
— |
15 |
— |
ns |
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Column Address Hold Time referenced to RAS |
tAR |
55 |
— |
55 |
— |
70 |
— |
ns |
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Read Command Set-up Time |
tRCS |
0 |
— |
0 |
— |
0 |
— |
ns |
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Read Command Hold Time |
tRCH |
0 |
— |
0 |
— |
0 |
— |
ns |
10 |
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Read Command Hold Time referenced to RAS |
tRRH |
0 |
— |
0 |
— |
0 |
— |
ns |
10 |
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Write Command Hold Time |
tWCH |
15 |
— |
15 |
— |
15 |
— |
ns |
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Write Command Hold Time referenced to RAS |
tWCR |
55 |
— |
55 |
— |
70 |
— |
ns |
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Write Command Pulse Width |
tWP |
15 |
— |
15 |
— |
15 |
— |
ns |
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Write Command to RAS Lead Time |
tRWL |
20 |
— |
20 |
— |
25 |
— |
ns |
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Write Command to CAS Lead Time |
tCWL |
20 |
— |
20 |
— |
25 |
— |
ns |
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6/45
¡ Semiconductor |
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MSM514262 |
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AC Characteristics (2/3) |
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(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6 |
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Parameter |
Symbol |
-70 |
-80 |
-10 |
Unit |
Note |
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Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
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Data Set-up Time |
tDS |
0 |
— |
0 |
— |
0 |
— |
ns |
11 |
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Data Hold Time |
tDH |
15 |
— |
15 |
— |
15 |
— |
ns |
11 |
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Data Hold Time referenced to RAS |
tDHR |
55 |
— |
55 |
— |
70 |
— |
ns |
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Write Command Set-up Time |
tWCS |
0 |
— |
0 |
— |
0 |
— |
ns |
12 |
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RAS to WE Delay Time |
tRWD |
100 |
— |
100 |
— |
130 |
— |
ns |
12 |
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Column Address to WE Delay Time |
tAWD |
65 |
— |
65 |
— |
80 |
— |
ns |
12 |
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CAS to WE Delay Time |
tCWD |
45 |
— |
45 |
— |
55 |
— |
ns |
12 |
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Data to CAS Delay Time |
tDZC |
0 |
— |
0 |
— |
0 |
— |
ns |
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Data to OE Delay Time |
tDZO |
0 |
— |
0 |
— |
0 |
— |
ns |
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Access Time from OE |
tOEA |
— |
20 |
— |
20 |
— |
25 |
ns |
7 |
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Output Buffer Turn-off Delay from OE |
tOEZ |
0 |
10 |
0 |
10 |
0 |
20 |
ns |
9 |
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OE to Data Delay Time |
tOED |
10 |
— |
10 |
— |
20 |
— |
ns |
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OE Command Hold Time |
tOEH |
10 |
— |
10 |
— |
20 |
— |
ns |
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RAS Hold Time referenced to OE |
tROH |
15 |
— |
15 |
— |
15 |
— |
ns |
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CAS Set-up Time for CAS before RAS Cycle |
tCSR |
10 |
— |
10 |
— |
10 |
— |
ns |
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CAS Hold Time for CAS before RAS Cycle |
tCHR |
10 |
— |
10 |
— |
10 |
— |
ns |
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RAS Precharge to CAS Active Time |
tRPC |
0 |
— |
0 |
— |
0 |
— |
ns |
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Refresh Period |
tREF |
— |
8 |
— |
8 |
— |
8 |
ms |
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WB Set-up Time |
tWSR |
0 |
— |
0 |
— |
0 |
— |
ns |
|
|
WB Hold Time |
tRWH |
15 |
— |
15 |
— |
15 |
— |
ns |
|
|
DSF Set-up Time referenced to RAS |
tFSR |
0 |
— |
0 |
— |
0 |
— |
ns |
|
|
DSF Hold Time referenced to RAS (1) |
tRFH |
15 |
— |
15 |
— |
15 |
— |
ns |
|
|
DSF Hold Time referenced to RAS (2) |
tFHR |
55 |
— |
55 |
— |
70 |
— |
ns |
|
|
DSF Set-up Time referenced to CAS |
tFSC |
0 |
— |
0 |
— |
0 |
— |
ns |
|
|
DSF Hold Time referenced to CAS |
tCFH |
15 |
— |
15 |
— |
15 |
— |
ns |
|
|
Write Per Bit Mask Data Set-up Time |
tMS |
0 |
— |
0 |
— |
0 |
— |
ns |
|
|
Write Per Bit Mask Data Hold Time |
tMH |
15 |
— |
15 |
— |
15 |
— |
ns |
|
|
DT High Set-up Time |
tTHS |
0 |
— |
0 |
— |
0 |
— |
ns |
|
|
DT High Hold Time |
tTHH |
15 |
— |
15 |
— |
15 |
— |
ns |
|
|
DT Low Set-up Time |
tTLS |
0 |
— |
0 |
— |
0 |
— |
ns |
|
|
DT Low Hold Time |
tTLH |
15 |
10k |
15 |
10k |
15 |
10k |
ns |
|
|
DT Low Hold Time referenced to RAS |
tRTH |
60 |
10k |
65 |
10k |
80 |
10k |
ns |
|
|
(Real Time Read Transfer) |
|
|||||||||
|
|
|
|
|
|
|
|
|
||
DT Low Hold Time referenced to Column Address |
tATH |
25 |
— |
30 |
— |
30 |
— |
ns |
|
|
(Real Time Read Transfer) |
|
|||||||||
|
|
|
|
|
|
|
|
|
||
DT Low Hold Time referenced to CAS |
tCTH |
20 |
— |
25 |
— |
25 |
— |
ns |
|
|
(Real Time Read Transfer) |
|
|||||||||
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|
|
|
|
|
|
|
|
||
SE Set-up Time referenced to RAS |
tESR |
0 |
— |
0 |
— |
0 |
— |
ns |
|
|
SE Hold Time referenced to RAS |
tREH |
15 |
— |
15 |
— |
15 |
— |
ns |
|
7/45
¡ Semiconductor |
|
|
|
|
|
|
|
|
|
MSM514262 |
|||
AC Characteristics (3/3) |
|
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6 |
|||||||||||
|
|
||||||||||||
Parameter |
Symbol |
|
-70 |
-80 |
|
-10 |
|
Unit |
Note |
||||
Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
||||||||
|
|
|
|
||||||||||
DT to RAS Precharge Time |
tTRP |
60 |
|
— |
60 |
|
— |
70 |
|
— |
ns |
|
|
DT Precharge Time |
tTP |
20 |
|
— |
20 |
|
— |
30 |
|
— |
ns |
|
|
RAS to First SC Delay Time (Read Transfer) |
tRSD |
70 |
|
— |
80 |
|
— |
100 |
|
— |
ns |
|
|
Column Address to First SC Delay Time (Read Transfer) |
tASD |
45 |
|
— |
45 |
|
— |
50 |
|
— |
ns |
|
|
CAS to First SC Delay Time (Read Transfer) |
tCSD |
20 |
|
— |
25 |
|
— |
25 |
|
— |
ns |
|
|
Last SC to DT Lead Time (Real Time Read Transfer) |
tTSL |
5 |
|
— |
5 |
|
— |
5 |
|
— |
ns |
|
|
DT to First SC Delay Time (Read Transfer) |
tTSD |
15 |
|
— |
15 |
|
— |
15 |
|
— |
ns |
|
|
Last SC to RAS Set-up Time (Serial Input) |
tSRS |
25 |
|
— |
25 |
|
— |
30 |
|
— |
ns |
|
|
RAS to First SC Delay Time (Serial Input) |
tSRD |
20 |
|
— |
20 |
|
— |
25 |
|
— |
ns |
|
|
RAS to Serial Input Delay Time |
tSDD |
40 |
|
— |
40 |
|
— |
50 |
|
— |
ns |
|
|
Serial Output Buffer Turn-off Delay from RAS |
tSDZ |
10 |
|
40 |
10 |
|
40 |
10 |
|
50 |
ns |
9 |
|
(Pseudo Write Transfer) |
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
||
SC Cycle Time |
tSCC |
30 |
|
— |
30 |
|
— |
30 |
|
— |
ns |
|
|
SC Pulse Width (SC High Time) |
tSC |
10 |
|
— |
10 |
|
— |
10 |
|
— |
ns |
|
|
SC Precharge Time (SC Low Time) |
tSCP |
10 |
|
— |
10 |
|
— |
10 |
|
— |
ns |
|
|
Access Time from SC |
tSCA |
— |
|
25 |
— |
|
25 |
— |
|
25 |
ns |
8 |
|
Serial Output Hold Time from SC |
tSOH |
5 |
|
— |
5 |
|
— |
5 |
|
— |
ns |
|
|
Serial Input Set-up Time |
tSDS |
0 |
|
— |
0 |
|
— |
0 |
|
— |
ns |
|
|
Serial Input Hold Time |
tSDH |
15 |
|
— |
15 |
|
— |
15 |
|
— |
ns |
|
|
Access Time from SE |
tSEA |
— |
|
25 |
— |
|
25 |
— |
|
25 |
ns |
8 |
|
SE Pulse Width |
tSE |
25 |
|
— |
25 |
|
— |
25 |
|
— |
ns |
|
|
SE Precharge Time |
tSEP |
25 |
|
— |
25 |
|
— |
25 |
|
— |
ns |
|
|
Serial Output Buffer Turn-off Delay from SE |
tSEZ |
0 |
|
20 |
0 |
|
20 |
0 |
|
20 |
ns |
9 |
|
Serial Input to SE Delay Time |
tSZE |
0 |
|
— |
0 |
|
— |
0 |
|
— |
ns |
|
|
Serial Input to First SC Delay Time |
tSZS |
0 |
|
— |
0 |
|
— |
0 |
|
— |
ns |
|
|
Serial Write Enable Set-up Time |
tSWS |
5 |
|
— |
5 |
|
— |
5 |
|
— |
ns |
|
|
Serial Write Enable Hold Time |
tSWH |
15 |
|
— |
15 |
|
— |
15 |
|
— |
ns |
|
|
Serial Write Disable Set-up Time |
tSWIS |
5 |
|
— |
5 |
|
— |
5 |
|
— |
ns |
|
|
Serial Write Disable Hold Time |
tSWIH |
15 |
|
— |
15 |
|
— |
15 |
|
— |
ns |
|
|
Split Transfer Set-up Time |
tSTS |
25 |
|
— |
30 |
|
— |
30 |
|
— |
ns |
|
|
Split Transfer Hold Time |
tSTH |
25 |
|
— |
30 |
|
— |
30 |
|
— |
ns |
|
|
SC-QSF Delay Time |
tSQD |
— |
|
25 |
— |
|
25 |
— |
|
25 |
ns |
|
|
DT-QSF Delay Time |
tTQD |
— |
|
25 |
— |
|
25 |
— |
|
25 |
ns |
|
|
CAS-QSF Delay Time |
tCQD |
— |
|
35 |
— |
|
35 |
— |
|
35 |
ns |
|
|
RAS-QSF Delay Time |
tRQD |
— |
|
75 |
— |
|
75 |
— |
|
85 |
ns |
|
8/45
¡ Semiconductor |
MSM514262 |
Notes: 1. These parameters depend on output loading. Specified values are obtained with the output open.
2.These parameters are masured at minimum cycle test.
3.ICC2 (Max.) are mesured under the condition of TTL input level.
4.VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL.
5.An initial pause of 200 ms is required after power-up followed by any 8 RAS cycles (DT/OE “high”) and any 8 SC cycles before proper divice operation is achieved. In the case of using an internal refresh counter, a minimum of 8 CAS before RAS initialization cycles in stead of 8 RAS cycles are required.
6.AC measurements assume tT = 5 ns.
7.RAM port outputs are mesured with a load equivalent to 1 TTL load and 100 pF. Output reference levels are VOH/VOL = 2.4 V/0.8 V.
8.SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output reference levels are VOH/VOL = 2.0 V/0.8 V.
9.tOFF (Max.), tOEZ (Max.), tSDZ (Max.) and tSEZ (Max.) difine the time at which the outputs achieve the open circuit condition and are not reference to output voltage levels.
10.Either tRCH or tRRH must be satisfied for a read cycle.
11.These parameters are referenced to CAS leading edge of early write cycles and to WB/WE leading edge in OE controlled write cycles and read modify write cycles.
12.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only.
If tWCS ≥ tWCS (Min.), the cycle is an early write cycle, and the data out pin will remain open circuit (high impedance) throughout the entire cycle : If tRWD ≥ tRWD (Min.), tCWD ≥ tCWD (Min.) and tAWD ≥ tAWD (Min.) the cycle is a read-write cycle and the data out will contain data read from the selected cell : If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indterminate.
13.Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only : If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC.
14.Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only : If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA.
15.Input levels at the AC parameter measurement are 3.0 V/0 V.
16.Stresses greater than those listed under “Absolute Maximum Ratings” may cause permenent damege to the device.
17.All voltages are referenced to VSS.
9/45
¡ Semiconductor |
MSM514262 |
TIMING WAVEFORM |
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||
Read Cycle |
|
|
|
|
|
|
|
|
|
|
|
tRC |
|
|
|
|
|
tRAS |
|
tRP |
RAS |
VIH – |
|
|
tAR |
|
|
|
|
|
|
|
||
VIL – |
|
|
|
|
|
|
|
|
|
tCSH |
|
|
|
|
|
|
|
|
|
|
|
|
tCRP |
|
tRCD |
tRSH |
tCPN |
CAS |
VIH – |
|
|
|
tCAS |
|
VIL – |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tRAD |
|
tRAL |
|
|
|
tASR |
tRAH |
tASC |
tCAH |
|
A0 - A8 |
VIH – |
Row Address |
Column Address |
|
||
VIL – |
|
|||||
|
|
|
|
|
tRCH |
|
|
|
|
|
|
|
tRCS |
|
|
||
tRRH |
||||
|
|
|
|
|
WB/WE |
VIH – |
|
|
|
|
VIL – |
|
|
|
|
|
|
|
|
|
|
|
|
tTHS |
tTHH |
|
tROH |
|
|
|
|
|
||
DT/OE |
VIH – |
|
|
|
|
VIL – |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tFHR |
|
|
|
tFSR |
tRFH |
tFSC |
tCFH |
|
DSF |
VIH – |
|
|
|
|
VIL – |
|
|
|
|
|
|
|
|
|
|
|
|
|
tDZO |
|
tOEA |
|
|
|
|
|
|
|
IN |
VIH – |
|
|
|
|
VIL – |
|
|
tCAC |
tOFF |
|
|
|
tAA |
|||
W1/IO1 - |
|
tRAC |
|
tOEZ |
|
W4/IO4 |
|
|
|
|
|
VOH– |
|
|
|
|
|
OUT |
|
Open |
|
Valid Data-out |
|
VOL – |
|
|
|||
|
|
|
|
|
"H" or "L"
10/45
¡ Semiconductor |
MSM514262 |
Write Cycle (Early Write) |
|
|
|
|||
|
|
|
|
|
tRC |
|
|
|
|
|
tRAS |
|
tRP |
RAS |
VIH – |
|
|
tAR |
|
|
|
|
|
|
|
||
VIL – |
|
|
|
|
|
|
|
|
|
tCSH |
|
|
|
|
|
|
|
|
|
|
|
|
tCRP |
|
tRCD |
tRSH |
tCPN |
CAS |
VIH – |
|
|
|
tCAS |
|
VIL – |
|
|
|
|
|
|
|
|
tRAD |
|
|
|
|
|
|
|
|
tRAL |
|
|
|
|
tASR |
tRAH |
tASC |
tCAH |
|
A0 - A8 |
VIH – |
Row Address |
Column Address |
|
||
VIL – |
|
|||||
|
|
|
|
|
|
|
|
|
tWSR |
tRWH |
tWCS |
tWCH |
|
WB/WE |
VIH – |
|
*1 |
tWP |
|
|
VIL – |
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
tWCR |
tCWL |
|
|
|
tTHS |
tTHH |
|
|
|
|
VIH – |
|
tRWL |
|
||
DT/OE |
|
|
|
|
|
|
VIL – |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tFHR |
|
|
|
|
tFSR |
tRFH |
tFSC |
tCFH |
|
DSF |
VIH – |
|
|
|
|
|
VIL – |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tMS |
tMH |
tDS |
tDH |
|
VIH –
IN WM1 Data Valid Data-in
VIL –
W1/IO1 - |
|
|
|
tDHR |
|
||||
W4/IO4 |
VOH– |
|
|
|
|
|
|
||
|
|
OUT |
|
|
Open |
|
|
||
|
|
|
|
|
|
||||
|
|
VOL – |
|
|
|
|
|||
|
|
|
|||||||
|
|
|
|
|
|
|
|
"H" or "L"
*1 WB/WE |
W1/IO1 - W4/IO4 |
Cycle |
|
|
|
|
|
|
0 |
WM1 data |
Write per Bit |
|
|
|
1 |
Don’t Care |
Normal Write |
|
|
|
WM1 data: |
0: Write Disable |
|
|
1: Write Enable |
|
11/45
¡ Semiconductor |
MSM514262 |
Write Cycle (OE Controlled Write)
tRC
tRAS |
|
tRP |
RAS |
VIH – |
|
tAR |
|
|
|
|
|
|
||
VIL – |
|
|
|
|
|
|
|
|
tCSH |
|
|
|
|
|
|
|
|
|
tCRP |
|
tRCD |
tRSH |
tCPN |
CAS |
VIH – |
|
|
tCAS |
|
VIL – |
|
|
|
|
|
|
tRAD |
|
tRAL |
|
|
|
|
|
|
||
|
tASR |
tRAH |
tASC |
tCAH |
|
A0 - A8 |
VIH – |
|
Column Address |
|
|
Row Address |
|
||||
|
VIL – |
|
|
|
tCWL |
|
|
|
|
|
|
|
tWSR |
tRWH |
|
|
tRWL |
WB/WE |
VIH – |
*1 |
|
|
tWP |
VIL – |
|
|
|
||
|
|
|
tWCR |
|
|
|
|
|
|
|
|
|
tTHS |
|
|
|
tOEH |
DT/OE |
VIH – |
|
|
|
|
VIL – |
|
|
|
|
|
|
|
tFHR |
|
|
|
|
|
|
|
|
|
|
tFSR |
tRFH |
tFSC |
tCFH |
|
DSF |
VIH – |
|
|
|
|
VIL – |
|
|
|
|
|
|
|
|
|
|
|
|
tMS |
tMH |
|
tDS |
tDH |
VIH –
IN WM1 Data Valid Data-in
VIL –
W1/IO1 - |
|
tDHR |
W4/IO4 |
|
|
|
VOH– |
||
OUT |
|
|
Open |
|
|
||
|
VOL – |
"H" or "L"
*1 WB/WE |
W1/IO1 - W4/IO4 |
Cycle |
|
|
|
|
|
|
0 |
WM1 data |
Write per Bit |
|
|
|
1 |
Don’t Care |
Normal Write |
|
|
|
WM1 data: |
0: Write Disable |
|
|
1: Write Enable |
|
12/45
¡ Semiconductor |
MSM514262 |
Read Modify Write Cycle
RAS
CAS
A0 - A8
WB/WE
DT/OE
DSF
IN
W1/IO1 - W4/IO4
OUT
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
VOH–
VOL –
|
|
|
tRWC |
|
|
|
|
tRAS |
tRP |
|
|
tAR |
|
|
|
|
|
tCSH |
|
tCRP |
|
tRCD |
tRSH |
tCPN |
|
|
|
tCAS |
|
|
|
tRAD |
|
|
tASR |
tRAH |
tASC |
tCAH |
|
Row Address |
Column Address |
|
||
|
|
|
|
tCWL |
tWSR |
tRWH |
tRCS |
tCWD |
tRWL |
|
*1 |
|
tAWD |
tWP |
|
|
|
||
|
|
|
tRWD |
|
tTHS |
|
tTHH |
|
tOEH |
|
|
tFHR |
|
|
tFSR |
tRFH |
tFSC |
tCFH |
|
|
|
tDZC |
tOED |
tDS |
tMS |
tMH |
tDZO |
tDH |
|
WM1 Data |
|
tOEA |
Valid |
|
|
Data-in |
|||
|
|
|
||
|
|
tAA |
tCAC |
|
|
|
tOEZ |
|
|
|
|
tRAC |
|
|
Open
Valid
Data-out
"H" or "L"
*1 WB/WE |
W1/IO1 - W4/IO4 |
Cycle |
|
|
|
|
|
|
0 |
WM1 data |
Write per Bit |
|
|
|
1 |
Don’t Care |
Normal Write |
|
|
|
WM1 data: |
0: Write Disable |
|
|
1: Write Enable |
|
13/45
¡ Semiconductor |
MSM514262 |
Fast Page Mode Read Cycle |
|
|
|
|
|
||||
|
|
|
|
|
|
tRASP |
|
|
tRP |
RAS |
VIH – |
|
|
tAR |
|
tPC |
|
|
|
|
|
|
|
|
|
|
|
||
VIL – |
|
|
|
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tCRP |
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tRSH |
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tRCD |
|
tCP |
tCP |
tCAS |
tCPN |
|
CAS |
VIH – |
|
tRAD |
tCAS |
tCAS |
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VIL – |
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tCSH |
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tRAL |
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tCAH |
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tASR |
tRAH |
tASC |
tCAH |
tASC |
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tASC |
tCAH |
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A0 - A8 |
VIH – |
Row |
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Column |
Column |
|
Column |
|
VIL – |
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|||||
|
Address |
|
Address 1 |
Address 2 |
|
Address n |
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tRCH |
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tRCH |
|
tRCH |
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tRCS |
tRCS |
tRCS |
tRRH |
||
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||||
WB/WE |
VIH – |
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VIL – |
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tTHS |
tTHH |
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DT/OE |
VIH – |
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VIL – |
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tFSC |
|
tFSC |
|
tFSC |
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tFSR |
|
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||
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tRFH |
tCFH |
|
tCFH |
|
tCFH |
|
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DSF |
VIH – |
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||||
VIL – |
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tFHR |
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tDZO |
|
tCPA |
|
tCPA |
|
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|
VIH – |
|
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||
IN |
|
|
|
tOEA |
|
|
||
VIL – |
|
tOEA |
|
tOEA |
|
|||
|
|
tOFF |
tOFF |
|||||
W1/IO1 - |
|
tCAC |
tCAC |
tOFF |
tCAC |
|||
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|
|||||
|
tAA |
|
tOEZ |
tOEZ |
tOEZ |
|||
W4/IO4 |
|
|
tAA |
tAA |
||||
VOH– |
tRAC |
|
|
|
|
|||
OUT |
Open |
Data-out 1 |
|
Data-out 2 |
Data-out n |
|||
VOL – |
|
|||||||
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"H" or "L"
14/45