OKI MSM514400DL-70ZS, MSM514400DL-60SJ, MSM514400DL-60TS-K, MSM514400DL-60ZS, MSM514400DL-70SJ Datasheet

E2G0023-17-41

This version: Jan. 1998

¡SemiconductorSemiconductor MSM514400D/DL

Previous version: May 1997

MSM514400D/DL

1,048,576-Word ¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE

DESCRIPTION

The MSM514400D/DL is a 1,048,576-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514400D/DL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM514400D/DL is available in a 26/20-pin plastic SOJ, 20pin plastic ZIP, or 26/20-pin plastic TSOP. The MSM514400DL (the low-power version) is specially designed for lower-power applications.

FEATURES

•1,048,576-word ¥ 4-bit configuration

•Single 5 V power supply, ±10% tolerance

• Input : TTL compatible, low input capacitance

•Output : TTL compatible, 3-state

•Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)

•Fast page mode, read modify write capability

•CAS before RAS refresh, hidden refresh, RAS-only refresh capability

•Multi-bit test mode capability

•Package options:

26/20-pin	300 mil plastic SOJ	(SOJ26/20-P-300-1.27)	(Product : MSM514400D/DL-xxSJ)
20-pin 400 mil plastic ZIP		(ZIP20-P-400-1.27)	(Product : MSM514400D/DL-xxZS)
26/20-pin	300 mil plastic TSOP	(TSOPII26/20-P-300-1.27-K) (Product : MSM514400D/DL-xxTS-K)
			xx indicates speed rank.

PRODUCT FAMILY

	Family	Access Time (Max.)				Cycle Time	Power Dissipation
						(Min.)
		tRAC	tAA	tCAC	tOEA		Operating (Max.)	Standby (Max.)
	MSM514400D/DL-50	50 ns	25 ns	13 ns	13 ns	90 ns	550 mW	5.5 mW/
	MSM514400D/DL-60	60 ns	30 ns	15 ns	15 ns	110 ns	495 mW
								1.1 mW (L-version)
	MSM514400D/DL-70	70 ns	35 ns	20 ns	20 ns	130 ns	440 mW

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¡ Semiconductor

MSM514400D/DL

PIN CONFIGURATION (TOP VIEW)

DQ1	1	26	VSS
DQ2	2	25	DQ4
WE 3		24	DQ3
RAS	4	23	CAS
A9	5	22	OE
A0	9	18	A8
A1	10	17	A7
A2	11	16	A6
A3	12	15	A5
VCC 13		14	A4

26/20-Pin Plastic SOJ

OE
	1			CAS	DQ1	1		26	VSS
			2
DQ3
	3				DQ2	2		25	DQ4
			4	DQ4
VSS	5				WE	3		24	DQ3
			6	DQ1
DQ2	7			WE	RAS	4		23	CAS
			8
RAS
	9		10	A9	A9	5		22	OE
A0	11
			12	A1
A2	13				A0	9		18	A8
			14	A3
VCC	15				A1	10		17	A7
			16	A4
A5
	17				A2	11		16	A6
			18	A6
A7
	19		20	A8	A3	12		15	A5
					VCC	13		14	A4
20-Pin Plastic ZIP						26/20-Pin Plastic TSOP
							(K Type)

Pin Name	Function
A0 - A9	Address Input
RAS	Row Address Strobe
CAS	Column Address Strobe
DQ1 - DQ4	Data Input/Data Output
OE	Output Enable
WE	Write Enable
VCC	Power Supply (5 V)
VSS	Ground (0 V)

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¡ Semiconductor MSM514400D/DL

BLOCK DIAGRAM

RAS			Timing
		Generator
							Timing
CAS						Generator
	Column						Write
10				10	Column		Clock	WE
	Address				Decoders		Generator		OE
	Buffers
							4	Output	4
								Buffers
	Internal		Refresh				I/O
A0 - A9					Sense
	Address					4			4 DQ1 - DQ4
			Control Clock		Amplifiers		4
	Counter						Selector	Input
							4		4
								Buffers
	Row		Row
10	Address 10			Word	Memory
	Buffers		De-
				Drivers	Cells
			coders
VCC
			On Chip
			VBB Generator
VSS

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¡ Semiconductor MSM514400D/DL

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

	Parameter	Symbol		Rating				Unit
	Voltage on Any Pin Relative to VSS	VT		–1.0 to 7.0				V
	Short Circuit Output Current	IOS		50				mA
	Power Dissipation	PD*		1				W
	Operating Temperature	Topr		0 to 70				°C
	Storage Temperature	Tstg		–55 to 150				°C
		*: Ta = 25°C
Recommended Operating Conditions							(Ta = 0°C to 70°C)
	Parameter	Symbol	Min.	Typ.		Max.		Unit
	Power Supply Voltage	VCC	4.5	5.0		5.5		V
		VSS	0	0		0		V
	Input High Voltage	VIH	2.4	—		6.5		V
	Input Low Voltage	VIL	–1.0	—		0.8		V
Capacitance				(VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz)
	Parameter	Symbol	Typ.			Max.		Unit
	Input Capacitance (A0 - A9)	CIN1	—			6		pF
	Input Capacitance (RAS, CAS, WE, OE)	CIN2	—			7		pF
	Output Capacitance (DQ1 - DQ4)	CI/O	—			7		pF

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¡ Semiconductor								MSM514400D/DL
DC Characteristics						(VCC = 5 V ±10%, Ta = 0°C to 70°C)
			MSM514400		MSM514400		MSM514400
Parameter	Symbol	Condition	D/DL-50		D/DL-60		D/DL-70			Unit	Note
			Min.	Max.	Min.	Max.	Min.		Max.
Output High Voltage	VOH	IOH = –5.0 mA	2.4	VCC	2.4	VCC	2.4		VCC	V
Output Low Voltage	VOL	IOL = 4.2 mA	0	0.4	0	0.4	0		0.4	V
		0 V £ VI £ 6.5 V;
Input Leakage Current	ILI	All other pins not	–10	10	–10	10	–10		10	mA
		under test = 0 V
Output Leakage Current	ILO	DQ disable	–10	10	–10	10	–10		10	mA
		0 V £ VO £ 5.5 V
Average Power		RAS, CAS cycling,
Supply Current	ICC1		—	100	—	90	—		80	mA	1, 2
		tRC = Min.
(Operating)
Power Supply		RAS, CAS = VIH	—	2	—	2	—		2	mA	1
	ICC2	RAS, CAS	—	1	—	1	—		1
Current (Standby)
		³ VCC –0.2 V	—	200	—	200	—		200	mA	1, 5
Average Power		RAS cycling,
Supply Current	ICC3	CAS = VIH,	—	100	—	90	—		80	mA	1, 2
(RAS-only Refresh)		tRC = Min.
Power Supply		RAS = VIH,
	ICC5	CAS = VIL,	—	5	—	5	—		5	mA	1
Current (Standby)
		DQ = enable
Average Power		RAS cycling,
Supply Current	ICC6		—	100	—	90	—		80	mA	1, 2
		CAS before RAS
(CAS before RAS Refresh)
Average Power		RAS = VIL,
Supply Current	ICC7	CAS cycling,	—	80	—	70	—		60	mA	1, 3
(Fast Page Mode)		tPC = Min.
Average Power		tRC = 125 ms,									1, 4,
Supply Current	ICC10	CAS before RAS,	—	300	—	300	—		300	mA
											5
(Battery Backup)		tRAS £ 1 ms

Notes : 1. ICC Max. is specified as ICC for output open condition.

2.The address can be changed once or less while RAS = VIL.

3.The address can be changed once or less while CAS = VIH.

4.VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V.

5.L-version.

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¡ Semiconductor								MSM514400D/DL
AC Characteristics (1/2)
			(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12
		MSM514400			MSM514400		MSM514400
Parameter	Symbol	D/DL-50			D/DL-60		D/DL-70			Unit	Note
		Min.		Max.	Min.	Max.	Min.		Max.
Random Read or Write Cycle Time	tRC	90		—	110	—	130		—	ns
Read Modify Write Cycle Time	tRWC	131		—	150	—	180		—	ns
Fast Page Mode Cycle Time	tPC	35		—	40	—	45		—	ns
Fast Page Mode Read Modify Write	tPRWC	76		—	80	—	95		—	ns
Cycle Time
Access Time from RAS	tRAC	—		50	—	60	—		70	ns	4, 5, 6
Access Time from CAS	tCAC	—		13	—	15	—		20	ns	4, 5
Access Time from Column Address	tAA	—		25	—	30	—		35	ns	4, 6
Access Time from CAS Precharge	tCPA	—		30	—	35	—		40	ns	4
Access Time from OE	tOEA	—		13	—	15	—		20	ns	4
Output Low Impedance Time from CAS	tCLZ	0		—	0	—	0		—	ns	4
CAS to Data Output Buffer Turn-off Delay Time	tOFF	0		13	0	15	0		20	ns	7
OE to Data Output Buffer Turn-off Delay Time	tOEZ	0		13	0	15	0		20	ns	7
Transition Time	tT	3		50	3	50	3		50	ns	3
Refresh Period	tREF	—		16	—	16	—		16	ms
Refresh Period (L-version)	tREF	—		128	—	128	—		128	ms
RAS Precharge Time	tRP	30		—	40	—	50		—	ns
RAS Pulse Width	tRAS	50		10,000	60	10,000	70		10,000	ns
RAS Pulse Width (Fast Page Mode)	tRASP	50		100,000	60	100,000	70		100,000	ns
RAS Hold Time	tRSH	13		—	15	—	20		—	ns
RAS Hold Time referenced to OE	tROH	10		—	15	—	20		—	ns
CAS Precharge Time (Fast Page Mode)	tCP	10		—	10	—	10		—	ns
CAS Pulse Width	tCAS	13		10,000	15	10,000	20		10,000	ns
CAS Hold Time	tCSH	50		—	60	—	70		—	ns
CAS to RAS Precharge Time	tCRP	5		—	5	—	5		—	ns
RAS Hold Time from CAS Precharge	tRHCP	30		—	35	—	40		—	ns
RAS to CAS Delay Time	tRCD	20		37	20	45	20		50	ns	5
RAS to Column Address Delay Time	tRAD	15		25	15	30	15		35	ns	6
Row Address Set-up Time	tASR	0		—	0	—	0		—	ns
Row Address Hold Time	tRAH	10		—	10	—	10		—	ns
Column Address Set-up Time	tASC	0		—	0	—	0		—	ns
Column Address Hold Time	tCAH	10		—	15	—	15		—	ns
Column Address Hold Time from RAS	tAR	45		—	50	—	55		—	ns
Column Address to RAS Lead Time	tRAL	25		—	30	—	35		—	ns

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