OKI MSM51V17405F-70TS-K, MSM51V17405F-50TS-K, MSM51V17405F-70SJ, MSM51V17405F-60SJ, MSM51V17405F-50SJ Datasheet

FEDD51V17405F-01

1Semiconductor

MSM51V17405F

This version: June. 2000 Previous version :

4,194,304-Word × 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO

DESCRIPTION

The MSM51V17405F is a 4,194,304-word × 4-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM51V17405F achieves high integration, high-speed operation, and lowpower consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM51V17405F is available in a 26/24-pin plastic SOJ or 26/24-pin plastic TSOP.

FEATURES

∙ 4,194,304-word × 4-bit configuration

∙ Single 3.3V power supply, ± 0.3V tolerance

∙ Input	: LVTTL compatible, low input capacitance
∙ Output	: LVTTL compatible, 3-state

∙Refresh : 2048 cycles/32ms

∙Fast page mode with EDO, read modify write capability

∙CAS before RAS refresh, hidden refresh, RAS-only refresh capability

∙Packages

26/24-pin 300mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM51V17405F-xxSJ) 26/24-pin 300mil plastic TSOP (TSOPII26/24-P-300-0.80-K) (Product : MSM51V17405F-xxTS-K)

						xx indicates speed rank.
PRODUCT FAMILY
			Access Time (Max.)			Cycle Time	Power Dissipation
	Family
		tRAC	tAA	tCAC	tOEA	(Min.)	Operating	Standby
							(Max.)	(Max.)
		50ns	25ns	13ns	13ns	84ns	360mW
	MSM51V17405F	60ns	30ns	15ns	15ns	104ns	324mW	1.8mW
		70ns	35ns	20ns	20ns	124ns	288mW

1/17

FEDD51V17405F-01

1Semiconductor

MSM51V17405F

PIN CONFIGURATION (TOP VIEW)

											VCC		1				VSS
	VCC		1		26		VSS								26
										DQ1 2							DQ4
DQ1 2					25		DQ4								25
										DQ2 3							DQ3
DQ2 3					24		DQ3								24
	WE 4				23		CAS				WE 4				23	CAS
RAS 5					22		OE			RAS 5					22		OE
											NC 6						A9
	NC 6				21		A9								21
										A10			8				A8
A10			8		19		A8								19
											A0		9				A7
	A0		9		18		A7								18
											A1		10				A6
	A1		10		17		A6								17
											A2		11				A5
	A2		11		16		A5								16
											A3		12				A4
	A3		12		15		A4								15
											VCC 13						VSS
	VCC 13				14		VSS								14
				26/24-Pin Plastic									26/24-Pin Plastic TSOP
				SOJ										(K Type)

Pin Name	Function
A0–A10	Address Input
RAS	Row Address Strobe
CAS	Column Address Strobe
DQ1–DQ4	Data Input/Data Output
OE	Output Enable
WE	Write Enable
VCC	Power Supply (3.3V)
VSS	Ground (0V)
NC	No Connection

Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.

2/17

FEDD51V17405F-01

1Semiconductor

MSM51V17405F

BLOCK DIAGRAM

RAS

Timing

Generator

Timing

CAS

Generator

Write

WE

Column

Clock

OE

Generator

11

Address

11

Column Decoders

Buffers

4

Output

4

Buffers

Internal

Refresh

Sense Amplifiers

4

I/O

4

4

DQ1 −

DQ4

A0 −

Selector

A10

Address

Control Clock

Input

Counter

4

4

Buffers

Row

Row

11

Address

11

Buffers

Deco-

Word

Memory

ders

Drivers

Cells

VCC

On Chip

VBB Generator

VSS

3/17

FEDD51V17405F-01

1Semiconductor

MSM51V17405F

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIUM RATINGS

Parameter

Symbol

Value

Unit

Voltage VCC Supply relative to VSS

VT

–0.5 to 4.6

V

Short Circuit Output Current

IOS

50

mA

Power Dissipation

PD*

1

W

Operating Temperature

Topr

0 to 70

°C

Storage Temperature

Tstg

–55 to 150

°C

*: Ta = 25° C

RECOMMENDED OPERATING CONDITIONS

(Ta = 0 to 70°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Power Supply Voltage

VCC

3.0

3.3

3.6

V

VSS

0

0

0

V

Input High Voltage

VIH

2.0

VCC + 0.3

V

Input Low Voltage

VIL

− 0.3

0.8

V

Notes: *1. The input voltage is VCC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied).

*2. The input voltage is VSS − 1.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied).

PIN CAPACITANCE

			(Vcc = 3.3V ±		0.3V, Ta = 25°C, f = 1 MHz)
Parameter	Symbol	Min.		Typ.		Min.	Unit
Input Capacitance (A0 – A10)	CIN1	—		—		5	pF
Input Capacitance	CIN2	—		—		7	pF
(RAS, CAS, WE, OE)
Output Capacitance (DQ1 – DQ4)	CI/O	—		—		7	pF

4/17

FEDD51V17405F-01

1Semiconductor

MSM51V17405F

DC CHARACTERISTICS

(VCC = 3.3V ±

0.3V, Ta = 0 to 70°C)

MSM51V17405

MSM51V17405

MSM51V17405

Parameter

Symbol

Condition

F-50

F-60

F-70

Unit

Note

Min.

Max.

Min.

Max.

Min.

Max.

Output High Voltage

VOH

IOH = − 2.0mA

2.4

VCC

2.4

VCC

2.4

VCC

V

Output Low Voltage

VOL

IOL = 2.0mA

0

0.4

0

0.4

0

0.4

V

Input Leakage

0V ≤ VI ≤ VCC+0.3V;

ILI

All other pins not

−

10

10

−

10

10

−

10

10

A

Current

under test = 0V

Output Leakage

ILO

DQ disable

−

10

10

−

10

10

−

10

10

A

Current

0V ≤ VO ≤ VCC

Average Power

RAS, CAS cycling,

Supply Current

ICC1

100

90

80

mA

1,2

tRC = Min.

(Operating)

Power Supply

RAS, CAS = VIH

2

2

2

Current

ICC2

RAS, CAS

0.5

0.5

0.5

mA

1

(Standby)

≥ VCC − 0.2V

Average Power

RAS cycling,

Supply Current

ICC3

CAS = VIH,

100

90

80

mA

1,2

(RAS-only Refresh)

tRC = Min.

Power Supply

RAS = VIH,

Current

ICC5

CAS = VIL,

5

5

5

mA

1

(Standby)

DQ = enable

Average Power

Supply Current

ICC6

RAS = cycling,

100

90

80

mA

1,2

(CAS before RAS

CAS before RAS

Refresh)

Average Power

RAS = VIL,

Supply Current

ICC7

CAS cycling,

100

90

80

mA

1,3

(Fast Page Mode)

tHPC = Min.

Notes: 1. ICC Max. is specified as ICC for output open condition.

2.The address can be changed once or less while RAS = VIL.

3.The address can be changed once or less while CAS = VIH.

5/17

										FEDD51V17405F-01
1Semiconductor										MSM51V17405F
AC CHARACTERISTICS (1/3)
				(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3,12,13
		MSM51V17405			MSM51V17405			MSM51V17405
Parameter	Symbol		F-50			F-60			F-70		Unit	Note
		Min.		Max.	Min.		Max.	Min.		Max.
Random Read or Write Cycle Time	tRC	84			104			124			ns
Read Modify Write Cycle Time	tRWC	110			135			160			ns
Fast Page Mode Cycle Time	tHPC	20			25			30			ns
Fast Page Mode Read Modify Write	tHPRWC	58			68			78			ns
Cycle Time
Access Time from RAS	tRAC			50			60			70	ns	4, 5, 6
Access Time from CAS	tCAC			13			15			20	ns	4,5
Access Time from Column Address	tAA			25			30			35	ns	4,6
Access Time from CAS Precharge	tCPA			30			35			40	ns	4
Access Time from OE	tOEA			13			15			20	ns	4
Output Low Impedance Time from	tCLZ	0			0			0			ns	4
CAS
Data Output Hold After CAS Low	tDOH	5			5			5			ns
CAS to Data Output Buffer Turn-	tCEZ	0		13	0		15	0		20	ns	7,8
off Delay Time
RAS to Data Output Buffer Turn-	tREZ	0		13	0		15	0		20	ns	7,8
off Delay Time
OE to Data Output Buffer Turn-off	tOEZ	0		13	0		15	0		20	ns	7
Delay Time
WE to Data Output Buffer Turn-	tWEZ	0		13	0		15	0		20	ns	7
off Delay Time
Transition Time	tT	1		50	1		50	1		50	ns	3
Refresh Period	tREF			32			32			32	ms
RAS Precharge Time	tRP	30			40			50			ns
RAS Pulse Width	tRAS	50		10,000	60		10,000	70		10,000	ns
RAS Pulse Width	tRASP	50		100,000	60		100,000	70		100,000	ns
(Fast Page Mode with EDO)
RAS Hold Time	tRSH	7			10			13			ns
RAS Hold Time referenced to OE	tROH	7			10			13			ns
CAS Precharge Time	tCP	7			10			10			ns
(Fast Page Mode with EDO)
CAS Pulse Width	tCAS	7		10,000	10		10,000	13		10,000	ns
CAS Hold Time	tCSH	35			40			45			ns

6/17