OKI MSM548262-80JS, MSM548262-60JS, MSM548262-60TS-K, MSM548262-70JS, MSM548262-80TS-K Datasheet

• RAS only refresh

• CAS before RAS refresh

• Hidden refresh

• Serial read/write

• 512 tap location

• Bidirectional data transfer

• Split transfer

• Masked write transfer

• Refresh: 512 cycles/8 ms

E2L0016-17-Y1

This version: Jan. 1998

¡SemiconductorSemiconductor MSM548262

Previous version: Dec. 1996

MSM548262

262,144-Word ¥ 8-Bit Multiport DRAM

DESCRIPTION

The MSM548262 is a 2-Mbit CMOS multiport DRAM composed of a 262,144-word by 8-bit dynamic RAM, and a 512-word by 8-bit SAM. Its RAM and SAM operate independently and asynchronously.

It supports three types of operations: random access to RAM port, high speed serial access to SAM port, and bidirectional transfer of data between any selected row in the RAM port and the SAM port. In addition to the conventional multiport DRAM operating modes, the MSM548262 features block write, flash write functions on the RAM port and a split data transfer capability on the SAM port. The SAM port requires no refresh operation because it uses static CMOS flipflops.

FEATURES

• Single power supply: 5 V ±10%

• Full TTL compatibility

• Multiport organization RAM : 256K word ¥ 8 bits SAM : 512 word ¥ 8 bits

• Fast page mode

• Write per bit

• Masked flash write

• Masked block write

• Package options:

40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM548262-xxJS) 44/40-pin 400 mil plastic TSOP (Type II)(TSOPII44/40-P-400-0.80-K)(Product : MSM548262-xxTS-K)

xx indicates speed rank.

PRODUCT FAMILY

	Family	Access Time		Cycle Time		Power Dissipation
		RAM	SAM	RAM	SAM	Operating	Standby
	MSM548262-60	60 ns	17 ns	120 ns	22 ns	140 mA	8 mA
	MSM548262-70	70 ns	17 ns	140 ns	22 ns	130 mA	8 mA
	MSM548262-80	80 ns	20 ns	150 ns	25 ns	120 mA	8 mA

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¡ Semiconductor

MSM548262

PIN CONFIGURATION (TOP VIEW)

VCC				VSS	VCC	1	44	VSS
	1		40
					SC	2	43	SDQ8
SC	2		39	SDQ8	SDQ1	3	42	SDQ7
SDQ1				SDQ7	SDQ2	4	41	SDQ6
	3		38
SDQ2				SDQ6	SDQ3	5	40	SDQ5
	4		37		SDQ4	6	39	SE
SDQ3				SDQ5	TRG	7	38	DQ8
	5		36
SDQ4				SE	DQ1	8	37	DQ7
	6		35		DQ2	9	36	DQ6
TRG				DQ8	DQ3	10	35	DQ5
	7		34
DQ1				DQ7
	8		33
DQ2				DQ6	DQ4	13	32	VSS
	9		32
DQ3				DQ5	VSS	14	31	DSF
	10		31		WE 15		30	NC
DQ4				VSS	RAS	16	29	CAS
	11		30
					A8	17	28	QSF
VSS	12		29	DSF	A7	18	27	A0
WE				NC	A6	19	26	A1
	13		28
					A5	20	25	A2
RAS				CAS
	14		27		A4	21	24	A3
A8				QSF	VCC	22	23	VSS
	15		26
A7				A0
	16		25				44/40-Pin Plastic TSOP (II)
A6				A1
	17		24
							(K Type)
A5				A2
	18		23
A4				A3
	19		22
VCC				VSS
	20		21

40-Pin Plastic SOJ

Pin Name		Function	Pin Name	Function
	A0 - A8	Address Input	SC	Serial Clock
DQ1 - DQ8		RAM Inputs/Outputs	SE	SAM Port Enable
SDQ1 - SDQ8		SAM Inputs/Outputs	DSF	Special Function Input
	RAS	Row Address Strobe	QSF	Special Function Output
	CAS	Column Address Strobe	VCC	Power Supply (5 V)
	WE	Write Enable	VSS	Ground (0 V)
	TRG	Transfer/Output Enable	NC	No Connection
Note:	The same power supply voltage must be provided to every VCC pin, and the same GND
	voltage level must be provided to every VSS pin.

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	Column
	Address		Column Decoder
	Buffer
			Sense Amp.
	Row	Row	512	¥ 512 ¥ 8
	Address	Decoder
			RAM ARRAY
	Buffer
	A0 - A8
	Refresh		Gate	Gate
	Counter
			SAM	SAM
			Serial Decoder
	SAM	SAM Address
	Address
			Counter
	Buffer
			SAM Stop
			Control

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Block Write	Column Mask
Control	Register
I/O Control	RAM Input
	Color Register
	Buffer
	Mask Register
	RAM Output
	Buffer
Flash Write
Control

SAM Input

Buffer

SDQ 1 - 8

SAM Output

Timing

Buffer

Generator

QSF

DQ 1 - 8

RAS

CAS

TRG

WE

DSF

SC

SE

VCC

VSS

DIAGRAM BLOCK

Semiconductor ¡

MSM548262

¡ Semiconductor

MSM548262

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

				(Note: 1)
Parameter	Symbol	Condition	Rating	Unit
Input Output Voltage	VT	Ta = 25°C	–1.0 to 7.0	V
Output Current	IOS	Ta = 25°C	50	mA
Power Dissipation	PD	Ta = 25°C	1	W
Operating Temperature	Topr	—	0 to 70	°C
Storage Temperature	Tstg	—	–55 to 150	°C

Recommended Operating Conditions

(Ta = 0°C to 70°C) (Note: 2)

Parameter	Symbol	Min.	Typ.	Max.	Unit
Power Supply Voltage	VCC	4.5	5.0	5.5	V
Input High Voltage	VIH	2.4	—	6.5	V
Input Low Voltage	VIL	–1.0	—	0.8	V

Capacitance

(VCC = 5 V ±10%, f = 1 MHz, Ta = 25°C)

Parameter	Symbol	Min.	Max.	Unit
Input Capacitance	Ci	—	8	pF
Input/Output Capacitance	Cio	—	9	pF
Output Capacitance	Co(QSF)	—	9	pF

Note: This parameter is periodically sampled and is not 100% tested.

DC Characteristics 1

	Parameter	Symbol	Condition	Min.	Max.	Unit
	Output "H" Level Voltage	VOH	IOH = –1 mA	2.4	—	V
	Output "L" Level Voltage	VOL	IOL = 2.1 mA	—	0.4
			0 £ VIN £ VCC
	Input Leakage Current	ILI	All other pins not	–10	10
			under test = 0 V			mA
	Output Leakage Current	ILO	0 £ VOUT £ 5.5 V	–10	10
			Output Disable

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	¡ Semiconductor					MSM548262
	DC Characteristics 2
				(VCC = 5 V ±10%, Ta = 0°C to 70°C)
	Item (RAM)	SAM	Symbol	-60	-70	-80	Unit	Note
				Max.	Max.	Max.
	Operating Current	Standby	ICC1	95	85	75		3, 4
	(RAS, CAS Cycling, tRC = tRC min.)	Active	ICC1A	140	130	120		17
	Standby Current	Standby	ICC2	8	8	8
	(RAS, CAS = VIH)	Active	ICC2A	60	55	50		3, 4
	RAS Only Refresh Current	Standby	ICC3	95	85	75		3, 4
	(RAS Cycling, CAS = VIH, tRC = tRC min.)	Active	ICC3A	140	130	120		17
	Page Mode Current	Standby	ICC4	75	70	65		3, 4
	(RAS = VIL, CAS Cycling, tPC = tPC min.)	Active	ICC4A	140	130	120	mA	18
	CAS before RAS Refresh Current	Standby	ICC5	95	85	75		3, 4
	(RAS Cycling, CAS before RAS, tRC = tRCmin.)	Active	ICC5A	140	130	120		3, 4
	Data Transfer Current	Standby	ICC6	95	85	75		3, 4
	(RAS, CAS Cycling, tRC = tRC min.)	Active	ICC6A	140	130	120		17
	Flash Write Current	Standby	ICC7	95	85	75		3, 4
	(RAS, CAS Cycling, tRC = tRC min.)	Active	ICC7A	140	130	120		3, 4
	Block Write Current	Standby	ICC8	95	85	75		3, 4
	(RAS, CAS Cycling, tRC = tRC min.)	Active	ICC8A	140	130	120		3, 4

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	¡ Semiconductor							MSM548262
	AC Characteristics (1/3)
	Parameter	Symbol	-60		-70		-80		Unit	Note
			Min.	Max.	Min.	Max.	Min.	Max.
	Random Read or Write Cycle Time	tRC	120	—	140	—	150	—	ns
	Read Modify Write Cycle	tRWC	170	—	185	—	195	—	ns
	Fast Page Mode Cycle Time	tPC	40	—	45	—	50	—	ns
	Fast Page Mode Read Modify Write Cycle Time	tPRWC	85	—	90	—	90	—	ns
	Access Time from RAS	tRAC	—	60	—	70	—	80	ns	8, 14
	Access Time from Column Address	tAA	—	30	—	35	—	40	ns	8, 14
	Access Time from CAS	tCAC	—	15	—	20	—	25	ns	8, 15
	Access Time from CAS Precharge	tCPA	—	35	—	40	—	45	ns	8, 15
	Output Buffer Turn-off Delay	tOFF	0	15	0	20	0	20	ns	10
	Transition Time (Rise and Fall)	tT	3	35	3	35	3	35	ns	7
	RAS Precharge Time	tRP	50	—	60	—	60	—	ns
	RAS Pulse Width	tRAS	60	10k	70	10k	80	10k	ns
	RAS Pulse Width (Fast Page Mode Only)	tRASP	60	100k	70	100k	80	100k	ns
	RAS Hold Time	tRSH	15	—	20	—	25	—	ns
	CAS Hold Time	tCSH	60	—	70	—	80	—	ns
	CAS Pulse Width	tCAS	15	10k	20	10k	25	10k	ns
	RAS to CAS Delay Time	tRCD	20	45	20	50	20	55	ns	14
	RAS to Column Address Delay Time	tRAD	15	30	15	35	15	40	ns	14
	Column Address to RAS Lead Time	tRAL	30	—	35	—	40	—	ns
	CAS to RAS Precharge Time	tCRP	10	—	10	—	10	—	ns
	CAS Precharge Time (Fast Page Mode)	tCP	10	—	10	—	10	—	ns
	Row Address Set-up Time	tASR	0	—	0	—	0	—	ns
	Row Address Hold Time	tRAH	10	—	10	—	10	—	ns
	Column Address Set-up Time	tASC	0	—	0	—	0	—	ns
	Column Address Hold Time	tCAH	10	—	10	—	12	—	ns
	Column Address Hold Time referenced to RAS	tAR	50	—	55	—	55	—	ns
	Read Command Set-up Time	tRCS	0	—	0	—	0	—	ns
	Read Command Hold Time	tRCH	0	—	0	—	0	—	ns	11
	Read Command Hold Time referenced to RAS	tRRH	0	—	0	—	0	—	ns	11
	Write Command Set-up Time	tWCS	0	—	0	—	0	—	ns	13
	Write Command Hold Time	tWCH	10	—	12	—	15	—	ns
	Write Command Hold Time referenced to RAS	tWCR	50	—	55	—	55	—	ns
	Write Command Pulse Width	tWP	10	—	12	—	15	—	ns
	Write Command to RAS Lead Time	tRWL	15	—	20	—	20	—	ns
	Write Command to CAS Lead Time	tCWL	15	—	20	—	20	—	ns
	Data Set-up Time	tDS	0	—	0	—	0	—	ns	12
	Data Hold Time	tDH	10	—	12	—	15	—	ns	12
	Data Hold Time referenced to RAS	tDHR	50	—	55	—	55	—	ns

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	¡ Semiconductor									MSM548262
	AC Characteristics (2/3)
	Parameter	Symbol		-60			-70		-80		Unit	Note
			Min.		Max.	Min.		Max.	Min.	Max.
	RAS to WE Delay Time	tRWD	80		—	90		—	100	—	ns	13
	Column Address to WE Delay Time	tAWD	50		—	55		—	65	—	ns	13
	CAS to WE Delay Time	tCWD	35		—	40		—	45	—	ns	13
	Data to CAS Delay Time	tDZC	0		—	0		—	0	—	ns
	Data to TRG Delay Time	tDZO	0		—	0		—	0	—	ns
	Access Time from TRG	tOEA	—		15	—		20	—	20	ns
	Output Buffer Turn-off Delay from TRG	tOEZ	0		10	0		10	0	10	ns
	TRG Command Hold Time	tOEH	10		—	10		—	10	—	ns
	RAS Hold Time referenced to TRG	tROH	10		—	15		—	15	—	ns
	CAS Set-up Time for CAS before RAS Cycle	tCSR	10		—	10		—	10	—	ns
	CAS Hold Time for CAS before RAS Cycle	tCHR	10		—	10		—	10	—	ns
	RAS Precharge to CAS Active Time	tRPC	0		—	0		—	0	—	ns
	Refresh Period	tREF	—		8	—		8	—	8	ms
	WE Set-up Time	tWSR	0		—	0		—	0	—	ns
	WE Hold Time	tRWH	10		—	10		—	12	—	ns
	DSF Set-up Time referenced to RAS	tFSR	0		—	0		—	0	—	ns
	DSF Hold Time referenced to RAS (1)	tRFH	10		—	10		—	12	—	ns
	DSF Hold Time referenced to RAS (2)	tFHR	50		—	55		—	55	—	ns
	DSF Set-up Time referenced to CAS	tFSC	0		—	0		—	0	—	ns
	DSF Hold Time referenced to CAS	tCFH	10		—	10		—	12	—	ns
	Write Per Bit Mask Data Set-up Time	tMS	0		—	0		—	0	—	ns
	Write Per Bit Mask Data Hold Time	tMH	10		—	10		—	12	—	ns
	TRG High Set-up Time	tTHS	0		—	0		—	0	—	ns
	TRG High Hold Time	tTHH	10		—	10		—	12	—	ns
	TRG Low Set-up Time	tTLS	0		—	0		—	0	—	ns
	TRG Low Hold Time	tTLH	10		10k	10		10k	12	10k	ns
	TRG Low Hold Time referenced to RAS	tRTH	50		10k	60		10k	65	10k	ns
	TRG Low Hold Time referenced to Column Address	tATH	20		—	25		—	30	—	ns
	TRG Low Hold Time referenced to CAS	tCTH	15		—	20		—	25	—	ns
	TRG to RAS Precharge Time	tTRP	50		—	60		—	60	—	ns
	TRG Precharge Time	tTP	20		—	20		—	20	—	ns
	RAS to First SC Delay Time (Read Transfer)	tRSD	60		—	70		—	80	—	ns
	Column Address to First SC Delay Time	tASD	40		—	45		—	45	—	ns
	CAS to First SC Delay Time (Read Transfer)	tCSD	20		—	20		—	25	—	ns
	Last SC to TRG Lead Time	tTSL	5		—	5		—	5	—	ns
	TRG to First SC Delay Time (Read Transfer)	tTSD	15		—	15		—	15	—	ns
	Last SC to RAS Set-up Time (Serial Input)	tSRS	20		—	25		—	25	—	ns
	Serial Output Buffer Turn-off Delay from RAS	tSDZ	10		30	10		40	10	40	ns	10

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	¡ Semiconductor										MSM548262
	AC Characteristics (3/3)
	Parameter	Symbol		-60			-70			-80		Unit	Note
			Min.		Max.	Min.		Max.	Min.		Max.
	SC Cycle Time	tSCC	22		—	22		—	25		—	ns
	SC Pulse Width (SC High Time)	tSC	5		—	5		—	7		—	ns
	SC Precharge Time (SC Low Time)	tSCP	5		—	5		—	7		—	ns
	Access Time from SC	tSCA	—		17	—		17	—		20	ns	9
	Serial Output Hold Time from SC	tSOH	5		—	5		—	5		—	ns	19
	Access Time from SE	tSEA	—		17	—		17	—		20	ns	9
	SE Pulse Width	tSE	10		—	10		—	10		—	ns
	SE Precharge Time	tSEP	10		—	10		—	10		—	ns
	Serial Output Buffer Turn-off Delay from SE	tSEZ	0		20	0		20	0		20	ns	10
	Split Transfer Set-up Time	tSTS	25		—	25		—	30		—	ns
	Split Transfer Hold Time	tSTH	25		—	25		—	30		—	ns
	SC-QSF Delay Time	tSQD	—		25	—		25	—		25	ns
	TRG-QSF Delay Time	tTQD	—		25	—		25	—		25	ns
	CAS-QSF Delay Time	tCQD	—		30	—		35	—		35	ns
	RAS-QSF Delay Time	tRQD	—		70	—		75	—		75	ns
	RAS to Serial Input Delay Time	tSDD	30		—	40		—	40		—	ns
	Serial Input Set-up Time	tSDS	0		—	0		—	0		—	ns
	Serial Input Hold Time	tSDH	10		—	10		—	12		—	ns
	Serial Input to SE Delay Time	tSZE	0		—	0		—	0		—	ns
	Serial Input to First SC Delay Time	tSZS	0		—	0		—	0		—	ns
	Serial Write Enable Set-up Time	tSWS	0		—	0		—	0		—	ns
	Serial Write Enable Hold Time	tSWH	10		—	10		—	12		—	ns
	Serial Write Disable Set-up Time	tSWIS	0		—	0		—	0		—	ns
	Serial Write Disable Hold Time	tSWIH	10		—	10		—	12		—	ns

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¡ Semiconductor

MSM548262

Notes: 1. Exposure beyond the "Absolute Maximum Ratings" may cause permanent damage to the device.

2.All voltages are referenced to VSS.

3.These parameters depend on the cycle rate.

4.These parameters depend on output loading. Specified values are obtained with the output open.

5.An initial pause of 200 ms is required after power up followed by any 8 RAS cycles (TRG = "high") and any 8 SC cycles before proper device operation is achieved. In the case of using an internal refresh counter, a minimum of 8 CAS before RAS cycles instead of 8 RAS cycles are required.

6.AC measurements assume tT = 5 ns.

7.VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL.

8.RAM port outputs are measured with a load equivalent to 1 TTL load and 50 pF. DOUT reference levels : VOH/VOL = 2.0 V/0.8 V.

9.SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF. DOUT reference levels : VOH/VOL = 2.0 V/0.8 V.

10.tOFF (Max.), tOEZ (Max.), tSDZ (Max.) and tSEZ (Max.) define the time at which the outputs achieve the open circuit condition, and are not referenced to output voltage levels. This parameter is sampled and not 100% tested.

11.Either tRCH or tRRH must be satisfied for a read cycle.

12.These parameters are referenced to CAS leading edge of early write cycles, and to WE leading edge in TRG controlled write cycles and read modify write cycles.

13.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only.

If tWCS ≥ tWCS (Min.), the cycle is an early write cycle, and the data out pin will remain open circuit throughout the entire cycle; If tRWD ≥ tRWD (Min.), tCWD ≥ tCWD (Min.) and tAWD ≥ tAWD (Min.), the cycle is a read modify write cycle, and the data out will contain data read from the selected cell; If neither of the above sets of conditions are satisfied, the condition of the data out is indeterminate.

14.Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC.

15.Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA.

16.Input levels at the AC testing are 3.0 V/0 V.

17.Address (A0 - A8) may be changed two times or less while RAS = VIL.

18.Address (A0 - A8) may be changed once or less while CAS = VIH and RAS = VIL.

19.This is guaranteed by design. (tSOH/tCOH = tSCA/tCAC - output transition time) This parameter is not 100% tested.

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¡ Semiconductor

MSM548262

TIMING WAVEFORM
Read Cycle
				tRC
				tRAS	tRP
RAS
				tCSH
	tCRP		tRCD	tRSH
				tCAS
CAS			tAR
		tRAD		tRAL
	tASR	tRAH	tASC	tCAH
Address	Row			Column
			tFHR
	tFSR	tRFH	tFSC	tCFH
DSF
					tRCH
			tRCS		tRRH
WE				tCAC
			tRAC		tOFF
				tAA

DQ1 - 8

Open

Valid Data

tROH

TRG

tTHS

tTHH

tOEA

tOEZ

"H" or "L"

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¡ Semiconductor

MSM548262

Fast Page Mode Read Cycle
					tRASP			tRP
RAS
			tCSH			tPC		tRSH
	tCRP	tRCD		tCAS	tCP	tCAS	tCP	tCAS
CAS		tAR
								tRAL
		tRAD
	tASR	tRAH	tASC	tCAH	tASC	tCAH	tASC	tCAH
Address	Row		Column		Column		Column

tFHR

t

t

tFSR

tRFH

FSC

tCFH

FSC

tCFH

FSC

tCFH

DSF

t

tRCH

tRCS

tRCS

WE

t

RCS

tCAC

tRCH

t

tCAC

tRCH

t

tCAC

tRRH

t

AA

tOFF

AA

tOFF

AA

tOFF

DQ1 - 8

Valid

Valid

Valid

Open

tRAC

Data

Data

Data

tCPA

tCPA

tTHS

tTHH

tOEA

tOEZ

tOEA tOEZ

tOEA tOEZ

TRG

"H" or "L"

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¡ Semiconductor											MSM548262
								Write Cycle Function Table
		RAS Falling Edge						CAS Falling Edge
Code		A		C		D		B	E		Function
		DSF	WE			DQ		DSF	DQ
RWM		0		0	Write Mask			0	Valid Data	Masked Write
BWM		0		0	Write Mask			1	Column Mask	Masked Block Write
FWM		1		0	Write Mask			X	X	Masked Flash Write
RW		0		1		X		0	Valid Data	Normal Write
BW		0		1		X		1	Column Mask	Block Write
LCR		1		1		X		1	Color Data	Load Color Register
WRITE MASK DATA: "Low" = Mask, "High" = No Mask
									Column Mask Data
	DQ1 - 4						Column Mask Data
		DQ1					Column 0 (A0 = 0, A1 = 0)
		DQ2					Column 1 (A0 = 1, A1 = 0)				Low: Mask
		DQ3					Column 2 (A0 = 0, A1 = 1)				High: No Mask
		DQ4					Column 3 (A0 = 1, A1 = 1)

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