E2G0129-17-61 |
Preliminary |
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¡ Semiconductor |
This version: Mar. 1998 |
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MSM51V17805D/DSL |
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Semiconductor |
MSM51V17805D/DSL
2,097,152-Word ´ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
TheMSM51V17805D/DSLisa2,097,152-word´ 8-bitdynamicRAMfabricatedinOki'ssilicon-gate CMOS technology. The MSM51V17805D/DSL achieves high integration, high-speed operation, andlow-powerconsumptionbecauseOkimanufacturesthedeviceinaquadruple-layerpolysilicon/ double-layer metal CMOS process. The MSM51V17805D/DSL is available in a 28-pin plastic SOJ or 28-pin plastic TSOP. The MSM51V17805DSL (the self-refresh version) is specially designed for lower-power applications.
FEATURES
•2,097,152-word ´ 8-bit configuration
•Single 3.3 V power supply, ±0.3 V tolerance
• Input : LVTTL compatible, low input capacitance
•Output : LVTTL compatible, 3-state
•Refresh : 2048 cycles/32 ms, 2048 cycles/128 ms (SL version)
•Fast page mode with EDO, read modify write capability
•CAS before RAS refresh, hidden refresh, RAS-only refresh capability
•CAS before RAS self-refresh capability (SL version)
•Multi-bit test mode capability
•Package options:
28-pin 400 mil plastic SOJ |
(SOJ28-P-400-1.27) |
(Product : MSM51V17805D/DSL-xxJS) |
28-pin 400 mil plastic TSOP |
(TSOPII28-P-400-1.27-K) (Product : MSM51V17805D/DSL-xxTS-K) |
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xx indicates speed rank. |
PRODUCT FAMILY
Family |
Access Time (Max.) |
Cycle Time |
Power Dissipation |
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(Min.) |
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tRAC |
tAA |
tCAC |
tOEA |
Operating (Max.) |
Standby (Max.) |
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MSM51V17805D/DSL-50 |
50 ns |
25 ns |
13 ns |
13 ns |
84 ns |
360 mW |
1.8 mW/ |
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MSM51V17805D/DSL-60 |
60 ns |
30 ns |
15 ns |
15 ns |
104 ns |
324 mW |
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0.72 mW (SL version) |
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MSM51V17805D/DSL-70 |
70 ns |
35 ns |
20 ns |
20 ns |
124 ns |
288 mW |
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¡ Semiconductor |
MSM51V17805D/DSL |
PIN CONFIGURATION (TOP VIEW) |
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VCC |
1 |
28 |
VSS |
VCC |
1 |
28 |
VSS |
DQ1 |
2 |
27 |
DQ8 |
DQ1 |
2 |
27 |
DQ8 |
DQ2 |
3 |
26 |
DQ7 |
DQ2 |
3 |
26 |
DQ7 |
DQ3 |
4 |
25 |
DQ6 |
DQ3 |
4 |
25 |
DQ6 |
DQ4 |
5 |
24 |
DQ5 |
DQ4 |
5 |
24 |
DQ5 |
WE 6 |
23 |
CAS |
WE 6 |
23 |
CAS |
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RAS |
7 |
22 |
OE |
RAS |
7 |
22 |
OE |
NC |
8 |
21 |
A9 |
NC |
8 |
21 |
A9 |
A10R |
9 |
20 |
A8 |
A10R |
9 |
20 |
A8 |
A0 |
10 |
19 |
A7 |
A0 |
10 |
19 |
A7 |
A1 |
11 |
18 |
A6 |
A1 |
11 |
18 |
A6 |
A2 |
12 |
17 |
A5 |
A2 |
12 |
17 |
A5 |
A3 |
13 |
16 |
A4 |
A3 |
13 |
16 |
A4 |
VCC 14 |
15 |
VSS |
VCC 14 |
15 |
VSS |
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28-Pin Plastic SOJ |
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28-Pin Plastic TSOP |
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(K Type) |
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Pin Name |
Function |
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A0 - A9, A10R |
Address Input |
RAS |
Row Address Strobe |
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CAS |
Column Address Strobe |
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DQ1 - DQ8 |
Data Input/Data Output |
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OE |
Output Enable |
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WE |
Write Enable |
VCC |
Power Supply (3.3 V) |
VSS |
Ground (0 V) |
Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.
2/17
¡ Semiconductor MSM51V17805D/DSL
BLOCK DIAGRAM
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Timing |
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WE |
OE |
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RAS |
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Generator |
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I/O |
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8 |
Output |
8 |
CAS |
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Controller |
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Buffers |
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DQ1 - DQ8 |
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10 |
Column |
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10 |
Column Decoders |
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Input |
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Address |
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8 |
8 |
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Buffers |
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Buffers |
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Internal |
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Sense Amplifiers 8 |
I/O |
8 |
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A0 - A9 |
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Refresh |
Selector |
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Address |
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Counter |
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Control Clock |
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10 |
Row |
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Row |
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Memory |
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Address |
11 |
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Deco- |
Word |
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A10R |
1 |
Buffers |
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Cells |
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ders |
Drivers |
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VCC
On Chip
VBB Generator
VSS
3/17
¡ Semiconductor MSM51V17805D/DSL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
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Parameter |
Symbol |
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Rating |
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Unit |
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Voltage on Any Pin Relative to VSS |
VT |
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–0.5 to 4.6 |
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V |
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Short Circuit Output Current |
IOS |
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50 |
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mA |
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Power Dissipation |
PD* |
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1 |
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W |
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Operating Temperature |
Topr |
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0 to 70 |
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°C |
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Storage Temperature |
Tstg |
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–55 to 150 |
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°C |
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*: Ta = 25°C |
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Recommended Operating Conditions |
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(Ta = 0°C to 70°C) |
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Parameter |
Symbol |
Min. |
Typ. |
Max. |
Unit |
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Power Supply Voltage |
VCC |
3.0 |
3.3 |
3.6 |
V |
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VSS |
0 |
0 |
0 |
V |
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Input High Voltage |
VIH |
2.0 |
— |
VCC + 0.3 |
V |
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Input Low Voltage |
VIL |
–0.3 |
— |
0.8 |
V |
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Capacitance |
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(VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) |
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Parameter |
Symbol |
Typ. |
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Max. |
Unit |
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Input Capacitance (A0 - A9, A10R) |
CIN1 |
— |
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5 |
pF |
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Input Capacitance (RAS, CAS, WE, OE) |
CIN2 |
— |
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7 |
pF |
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Output Capacitance (DQ1 - DQ8) |
CI/O |
— |
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7 |
pF |
4/17
¡ Semiconductor |
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MSM51V17805D/DSL |
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DC Characteristics |
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(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) |
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MSM51V17805MSM51V17805MSM51V17805 |
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Parameter |
Symbol |
Condition |
D/DSL-50 |
D/DSL-60 |
D/DSL-70 |
Unit |
Note |
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Min. |
Max. Min. |
Max. Min. |
Max. |
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Output High Voltage |
VOH |
IOH = –2.0 mA |
2.4 |
VCC |
2.4 |
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VCC |
2.4 |
VCC |
V |
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Output Low Voltage |
VOL |
IOL = 2.0 mA |
0 |
0.4 |
0 |
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0.4 |
0 |
0.4 |
V |
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0 V £ VI £ VCC + 0.3 V; |
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Input Leakage Current |
ILI |
All other pins not |
–10 |
10 |
–10 |
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10 |
–10 |
10 |
mA |
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under test = 0 V |
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Output Leakage Current |
ILO |
DQ disable |
–10 |
10 |
–10 |
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10 |
–10 |
10 |
mA |
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0 V £ VO £ VCC |
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Average Power |
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RAS, CAS cycling, |
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Supply Current |
ICC1 |
— |
100 |
— |
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90 |
— |
80 |
mA |
1, 2 |
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tRC = Min. |
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(Operating) |
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Power Supply |
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RAS, CAS = VIH |
— |
2 |
— |
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2 |
— |
2 |
mA |
1 |
ICC2 |
RAS, CAS |
— |
0.5 |
— |
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0.5 |
— |
0.5 |
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Current (Standby) |
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³ VCC –0.2 V |
— |
200 |
— |
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200 |
— |
200 |
mA |
1, 5 |
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Average Power |
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RAS cycling, |
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Supply Current |
ICC3 |
CAS = VIH, |
— |
100 |
— |
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90 |
— |
80 |
mA |
1, 2 |
(RAS-only Refresh) |
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tRC = Min. |
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Power Supply |
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RAS = VIH, |
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ICC5 |
CAS = VIL, |
— |
5 |
— |
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5 |
— |
5 |
mA |
1 |
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Current (Standby) |
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DQ = enable |
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Average Power |
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RAS cycling, |
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Supply Current |
ICC6 |
— |
100 |
— |
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90 |
— |
80 |
mA |
1, 2 |
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CAS before RAS |
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(CAS before RAS Refresh) |
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Average Power |
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RAS = VIL, |
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Supply Current |
ICC7 |
CAS cycling, |
— |
100 |
— |
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90 |
— |
80 |
mA |
1, 3 |
(Fast Page Mode) |
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tHPC = Min. |
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Average Power |
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tRC = 62.5 ms, |
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1, 4, |
Supply Current |
ICC10 |
CAS before RAS, |
— |
300 |
— |
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300 |
— |
300 |
mA |
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5 |
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(Battery Backup) |
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tRAS £ 1 ms |
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Average Power |
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Supply Current |
ICCS |
RAS £ 0.2 V, |
— |
300 |
— |
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300 |
— |
300 |
mA |
1, 5 |
(CAS before RAS |
CAS £ 0.2 V |
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Self-Refresh) |
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Notes : 1. ICC Max. is specified as ICC for output open condition.
2.The address can be changed once or less while RAS = VIL.
3.The address can be changed once or less while CAS = VIH.
4.VCC – 0.2 V £ VIH £ VCC + 0.3 V, –0.3 V £ VIL £ 0.2 V.
5.SL version.
5/17
¡ Semiconductor |
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MSM51V17805D/DSL |
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AC Characteristics (1/2) |
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(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13 |
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MSM51V17805MSM51V17805MSM51V17805 |
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Parameter |
Symbol |
D/DSL-50 |
D/DSL-60 |
D/DSL-70 |
Unit |
Note |
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Min. |
Max. Min. |
Max. Min. |
Max. |
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Random Read or Write Cycle Time |
tRC |
84 |
— |
104 |
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124 |
— |
ns |
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Read Modify Write Cycle Time |
tRWC |
110 |
— |
135 |
— |
160 |
— |
ns |
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Fast Page Mode Cycle Time |
tHPC |
20 |
— |
25 |
— |
30 |
— |
ns |
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Fast Page Mode Read Modify Write |
tHPRWC |
58 |
— |
68 |
— |
78 |
— |
ns |
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Cycle Time |
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Access Time from RAS |
tRAC |
— |
50 |
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60 |
— |
70 |
ns |
4, 5, 6 |
Access Time from CAS |
tCAC |
— |
13 |
— |
15 |
— |
20 |
ns |
4, 5 |
Access Time from Column Address |
tAA |
— |
25 |
— |
30 |
— |
35 |
ns |
4, 6 |
Access Time from CAS Precharge |
tCPA |
— |
30 |
— |
35 |
— |
40 |
ns |
4 |
Access Time from OE |
tOEA |
— |
13 |
— |
15 |
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20 |
ns |
4 |
Output Low Impedance Time from CAS |
tCLZ |
0 |
— |
0 |
— |
0 |
— |
ns |
4 |
Data Output Hold After CAS Low |
tDOH |
5 |
— |
5 |
— |
5 |
— |
ns |
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CAS to Data Output Buffer Turn-off Delay Time |
tCEZ |
0 |
13 |
0 |
15 |
0 |
20 |
ns |
7, 8 |
RAS to Data Output Buffer Turn-off Delay Time |
tREZ |
0 |
13 |
0 |
15 |
0 |
20 |
ns |
7, 8 |
OE to Data Output Buffer Turn-off Delay Time |
tOEZ |
0 |
13 |
0 |
15 |
0 |
20 |
ns |
7 |
WE to Data Output Buffer Turn-off Delay Time |
tWEZ |
0 |
13 |
0 |
15 |
0 |
20 |
ns |
7 |
Transition Time |
tT |
1 |
50 |
1 |
50 |
1 |
50 |
ns |
3 |
Refresh Period |
tREF |
— |
32 |
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32 |
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32 |
ms |
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Refresh Period (SL version) |
tREF |
— |
128 |
— |
128 |
— |
128 |
ms |
14 |
RAS Precharge Time |
tRP |
30 |
— |
40 |
— |
50 |
— |
ns |
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RAS Pulse Width |
tRAS |
50 |
10,000 |
60 |
10,000 |
70 |
10,000 |
ns |
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RAS Pulse Width (Fast Page Mode with EDO) |
tRASP |
50 |
100,000 |
60 |
100,000 |
70 |
100,000 |
ns |
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RAS Hold Time |
tRSH |
7 |
— |
10 |
— |
13 |
— |
ns |
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RAS Hold Time referenced to OE |
tROH |
7 |
— |
10 |
— |
13 |
— |
ns |
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CAS Precharge Time (Fast Page Mode with EDO) |
tCP |
7 |
— |
10 |
— |
10 |
— |
ns |
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CAS Pulse Width |
tCAS |
7 |
10,000 |
10 |
10,000 |
13 |
10,000 |
ns |
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CAS Hold Time |
tCSH |
35 |
— |
40 |
— |
45 |
— |
ns |
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CAS to RAS Precharge Time |
tCRP |
5 |
— |
5 |
— |
5 |
— |
ns |
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RAS Hold Time from CAS Precharge |
tRHCP |
30 |
— |
35 |
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40 |
— |
ns |
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OE Hold Time from CAS (DQ Disable) |
tCHO |
5 |
— |
5 |
— |
5 |
— |
ns |
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RAS to CAS Delay Time |
tRCD |
11 |
37 |
14 |
45 |
14 |
50 |
ns |
5 |
RAS to Column Address Delay Time |
tRAD |
9 |
25 |
12 |
30 |
12 |
35 |
ns |
6 |
Row Address Set-up Time |
tASR |
0 |
— |
0 |
— |
0 |
— |
ns |
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Row Address Hold Time |
tRAH |
7 |
— |
10 |
— |
10 |
— |
ns |
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Column Address Set-up Time |
tASC |
0 |
— |
0 |
— |
0 |
— |
ns |
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Column Address Hold Time |
tCAH |
7 |
— |
10 |
— |
13 |
— |
ns |
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Column Address to RAS Lead Time |
tRAL |
25 |
— |
30 |
— |
35 |
— |
ns |
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6/17