OKI MSM514265CSL-60JS, MSM514265CSL-60TS-K, MSM514265CSL-70JS, MSM514265CSL-70TS-K, MSM514265CSL-50JS Datasheet

E2G0027-17-41

This version: Jan. 1998

Semiconductor MSM514265C/CSL

¡ Semiconductor

Previous version: May 1997

MSM514265C/CSL

262,144-Word ´ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO

DESCRIPTION

The MSM514265C/CSL is a 262,144-word ´ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514265C/CSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM514265C/CSL is available in a 40-pin plastic SOJ or 44/ 40-pin plastic TSOP. The MSM514265CSL (the self-refresh version) is specially designed for lowerpower applications.

FEATURES

•262,144-word ´ 16-bit configuration

•Single 5 V power supply, ±10% tolerance

• Input : TTL compatible, low input capacitance

•Output : TTL compatible, 3-state

•Refresh : 512 cycles/8 ms, 512 cycles/128 ms (SL version)

•Fast page mode with EDO, read modify write capability

•CAS before RAS refresh, hidden refresh, RAS-only refresh capability

•CAS before RAS self-refresh capability (SL version)

•Package options:

40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM514265C/CSL-xxJS) 44/40-pin 400 mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM514265C/CSL-xxTS-K)

						xx indicates speed rank.
PRODUCT FAMILY
Family	Access Time (Max.)				Cycle Time		Power Dissipation
	tRAC	tAA	tCAC	tOEA	(Min.)		Operating (Max.)	Standby (Max.)
MSM514265C/CSL-50	50 ns	25 ns	15 ns	15 ns	90 ns		935 mW	5.5 mW/
MSM514265C/CSL-60	60 ns	30 ns	15 ns	15 ns	110 ns		825 mW
								1.1 mW (SL version)
MSM514265C/CSL-70	70 ns	35 ns	20 ns	20 ns	130 ns		770 mW

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¡ Semiconductor

MSM514265C/CSL

PIN CONFIGURATION (TOP VIEW)

VCC					VSS	VCC				VSS
	1			40			1	44
DQ1					DQ16	DQ1	2	43		DQ16
	2			39
DQ2					DQ15	DQ2	3	42		DQ15
	3			38
DQ3					DQ14	DQ3	4	41		DQ14
	4			37
						DQ4	5	40		DQ13
DQ4					DQ13
	5			36		VCC	6	39		VSS
VCC					VSS
	6			35		DQ5	7	38		DQ12
DQ5					DQ12	DQ6	8	37		DQ11
	7			34
DQ6					DQ11	DQ7	9	36		DQ10
	8			33
DQ7					DQ10	DQ8 10		35		DQ9
	9			32
DQ8					DQ9
	10			31		NC 13		32		NC
NC					NC	NC 14		31		LCAS
	11			30
NC					LCAS	WE 15		30		UCAS
	12			29
WE					UCAS RAS 16			29		OE
	13			28
RAS					OE	NC	17	28		A8
	14			27
						A0	18	27		A7
NC					A8
	15			26		A1	19	26		A6
A0					A7	A2	20	25		A5
	16			25
A1					A6	A3	21	24		A4
	17			24
						VCC 22		23		VSS
A2					A5
	18			23
A3					A4
	19			22			44/40-Pin Plastic TSOP
VCC					VSS
	20			21				(K Type)
		40-Pin Plastic SOJ
			Pin Name				Function
			A0 - A8		Address Input
			RAS		Row Address Strobe
			LCAS		Lower Byte Column Address Strobe
			UCAS		Upper Byte Column Address Strobe
			DQ1 - DQ16		Data Input / Data Output
			OE		Output Enable
			WE		Write Enable
			VCC		Power Supply (5 V)
			VSS		Ground (0 V)
			NC		No Connection

Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.

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¡ Semiconductor MSM514265C/CSL

BLOCK DIAGRAM

RAS	Timing				WE	OE
	Generator
LCAS					I/O
					Controller				Output
UCAS								8		8
					I/O				Buffers
					Controller					DQ1 - DQ8
		Column
	9			9	Column Decoders				Input
		Address						8		8
		Buffers							Buffers
		Internal			Sense Amplifiers 16		I/O	16
A0 - A8			Refresh				Selector
		Address
		Counter	Control Clock
								8	Input	8
		Row							Buffers
			Row
					Memory
	9	Address 9								DQ9 - DQ16
			Deco-	Word
		Buffers	ders	Drivers	Cells				Output
								8		8
									Buffers

VCC

On Chip

VBB Generator

VSS

FUNCTION TABLE

			Input Pin			DQ Pin			Function Mode
	RAS	LCAS	UCAS	WE	OE	DQ1 - DQ8	DQ9 - DQ16
	H	*	*	*	*	High-Z		High-Z	Standby
	L	H	H	*	*	High-Z		High-Z	Refresh
	L	L	H	H	L	DOUT		High-Z	Lower Byte Read
	L	H	L	H	L	High-Z		DOUT	Upper Byte Read
	L	L	L	H	L	DOUT		DOUT	Word Read
	L	L	H	L	H	DIN		Don't Care	Lower Byte Write
	L	H	L	L	H	Don't Care		DIN	Upper Byte Write
	L	L	L	L	H	DIN		DIN	Word Write
	L	L	L	H	H	High-Z		High-Z	—

*: "H" or "L"

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¡ Semiconductor MSM514265C/CSL

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Parameter	Symbol		Rating				Unit
Voltage on Any Pin Relative to VSS	VT		–1.0 to 7.0				V
Short Circuit Output Current	IOS		50				mA
Power Dissipation	PD*		1				W
Operating Temperature	Topr		0 to 70				°C
Storage Temperature	Tstg		–55 to 150				°C
	*: Ta = 25°C
Recommended Operating Conditions						(Ta = 0°C to 70°C)
Parameter	Symbol	Min.	Typ.		Max.		Unit
Power Supply Voltage	VCC	4.5	5.0		5.5		V
	VSS	0	0		0		V
Input High Voltage	VIH	2.4	—		6.5		V
Input Low Voltage	VIL	–1.0	—		0.8		V
Capacitance			(VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz)
Parameter	Symbol	Typ.			Max.		Unit
Input Capacitance (A0 - A8)	CIN1	—			7		pF
Input Capacitance	CIN2	—			7		pF
(RAS, LCAS, UCAS, WE, OE)
Output Capacitance (DQ1 - DQ16)	CI/O	—			10		pF

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	¡ Semiconductor							MSM514265C/CSL
	DC Characteristics
							(VCC = 5 V ±10%, Ta = 0°C to 70°C)
				MSM514265		MSM514265		MSM514265
	Parameter	Symbol	Condition	C/CSL-50		C/CSL-60		C/CSL-70		Unit	Note
				Min.	Max.	Min.	Max.	Min.	Max.
	Output High Voltage	VOH	IOH = –2.0 mA	2.4	VCC	2.4	VCC	2.4	VCC	V
	Output Low Voltage	VOL	IOL = 2.0 mA	0	0.4	0	0.4	0	0.4	V
			0 V £ VI £ 6.5 V;
	Input Leakage Current	ILI	All other pins not	–10	10	–10	10	–10	10	mA
			under test = 0 V
	Output Leakage Current	ILO	DQ disable	–10	10	–10	10	–10	10	mA
			0 V £ VO £ 5.5 V
	Average Power		RAS, CAS cycling,
	Supply Current	ICC1		—	170	—	150	—	140	mA	1, 2
			tRC = Min.
	(Operating)
	Power Supply		RAS, CAS = VIH	—	2	—	2	—	2	mA	1
		ICC2	RAS, CAS	—	1	—	1	—	1
	Current (Standby)
			³ VCC –0.2 V	—	200	—	200	—	200	mA	1, 5
	Average Power		RAS cycling,
	Supply Current	ICC3	CAS = VIH,	—	170	—	150	—	140	mA	1, 2
	(RAS-only Refresh)		tRC = Min.
	Power Supply		RAS = VIH,
		ICC5	CAS = VIL,	—	5	—	5	—	5	mA	1
	Current (Standby)
			DQ = enable
	Average Power		RAS cycling,
	Supply Current	ICC6		—	170	—	150	—	140	mA	1, 2
			CAS before RAS
	(CAS before RAS Refresh)
	Average Power		RAS = VIL,
	Supply Current	ICC7	CAS cycling,	—	170	—	150	—	140	mA	1, 3
	(Fast Page Mode)		tHPC = Min.
	Average Power		tRC = 125 ms,								1, 4,
	Supply Current	ICC10	CAS before RAS,	—	300	—	300	—	300	mA
											5
	(Battery Backup)		tRAS £ 1 ms
	Average Power
	Supply Current	ICCS	RAS £ 0.2 V,	—	200	—	200	—	200	mA	1, 5
	(CAS before RAS		CAS £ 0.2 V
	Self-Refresh)

Notes: 1. ICC Max. is specified as ICC for output open condition.

2.The address can be changed once or less while RAS = VIL.

3.The address can be changed once or less while CAS = VIH.

4.VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V.

5.SL version.

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¡ Semiconductor							MSM514265C/CSL
AC Characteristics (1/2)			(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3
		MSM514265		MSM514265		MSM514265
Parameter	Symbol	C/CSL-50		C/CSL-60		C/CSL-70			Unit	Note
		Min.	Max.	Min.	Max.	Min.		Max.
Random Read or Write Cycle Time	tRC	90	—	110	—	130		—	ns
Read Modify Write Cycle Time	tRWC	130	—	150	—	180		—	ns
Fast Page Mode Cycle Time	tHPC	20	—	25	—	30		—	ns
Fast Page Mode Read Modify Write	tHPRWC	75	—	80	—	95		—	ns
Cycle Time
Access Time from RAS	tRAC	—	50	—	60	—		70	ns	4, 5, 6
Access Time from CAS	tCAC	—	15	—	15	—		20	ns	4, 5
Access Time from Column Address	tAA	—	25	—	30	—		35	ns	4, 6
Access Time from CAS Precharge	tCPA	—	30	—	35	—		40	ns	4, 13
Access Time from OE	tOEA	—	15	—	15	—		20	ns	4
Output Low Impedance Time from CAS	tCLZ	0	—	0	—	0		—	ns	4
Data Output Hold After CAS Low	tDOH	5	—	5	—	5		—	ns
CAS to Data Output Buffer Turn-off Delay Time	tCEZ	0	15	0	15	0		20	ns	7, 8
RAS to Data Output Buffer Turn-off Delay Time	tREZ	0	15	0	15	0		20	ns	7, 8
OE to Data Output Buffer Turn-off Delay Time	tOEZ	0	15	0	15	0		20	ns	7
WE to Data Output Buffer Turn-off Delay Time	tWEZ	0	15	0	15	0		20	ns	7
Transition Time	tT	1	50	1	50	1		50	ns	3
Refresh Period	tREF	—	8	—	8	—		8	ms
Refresh Period (SL version)	tREF	—	128	—	128	—		128	ms	16
RAS Precharge Time	tRP	30	—	40	—	50		—	ns
RAS Pulse Width	tRAS	50	10,000	60	10,000	70		10,000	ns
RAS Pulse Width (Fast Page Mode with EDO)	tRASP	50	100,000	60	100,000	70		100,000	ns
RAS Hold Time	tRSH	15	—	15	—	20		—	ns
RAS Hold Time referenced to OE	tROH	10	—	15	—	20		—	ns
CAS Precharge Time (Fast Page Mode with EDO)	tCP	7	—	10	—	10		—	ns	15
CAS Pulse Width	tCAS	7	10,000	10	10,000	10		10,000	ns
CAS Hold Time	tCSH	50	—	60	—	70		—	ns
CAS to RAS Precharge Time	tCRP	10	—	10	—	10		—	ns	13
RAS Hold Time from CAS Precharge	tRHCP	30	—	35	—	40		—	ns	13
OE Hold Time from CAS (DQ Disable)	tCHO	5	—	5	—	10		—	ns
RAS to CAS Delay Time	tRCD	18	35	20	45	20		50	ns	5
RAS to Column Address Delay Time	tRAD	13	25	15	30	15		35	ns	6
RAS to Second CAS Delay Time	tRSCD	50	—	60	—	70		—	ns
Row Address Set-up Time	tASR	0	—	0	—	0		—	ns
Row Address Hold Time	tRAH	8	—	10	—	10		—	ns
Column Address Set-up Time	tASC	0	—	0	—	0		—	ns	12
Column Address Hold Time	tCAH	10	—	10	—	15		—	ns	12
Column Address Hold Time from RAS	tAR	40	—	50	—	55		—	ns
Column Address to RAS Lead Time	tRAL	25	—	30	—	35		—	ns

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