Philips PCF2113DU-10-F3, PCF2113DU-F2, PCF2113DU-F3, PCF2113EU-10-F2, PCF2113EU-10-F3 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

PCF2113x

LCD controller/driver

Product specification

1997 Apr 04

Supersedes data of 1996 Oct 21

File under Integrated Circuits, IC12

Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

CONTENTS

1FEATURES

2APPLICATIONS

3GENERAL DESCRIPTION

4ORDERING INFORMATION

5BLOCK DIAGRAM

6PINNING

7PIN FUNCTIONS

8FUNCTIONAL DESCRIPTION

8.1LCD supply voltage generator

8.2Programming ranges

8.3LCD bias voltage generator

8.4Oscillator

8.5External clock

8.6Power-on reset

8.7Power-down mode

8.8Registers

8.9Busy Flag

8.10Address Counter (AC)

8.11Display Data RAM (DDRAM)

8.12Character Generator ROM (CGROM)

8.13Character Generator RAM (CGRAM)

8.14Cursor control circuit

8.15Timing generator

8.16LCD row and column drivers

8.17Reset function

9 INSTRUCTIONS

9.1Clear display

9.2Return home

9.3Entry mode set

9.3.1I/D

9.3.2S

9.4Display control (and partial power-down mode)

9.4.1D

9.4.2C

9.4.3B

9.5Cursor/display shift

9.6Function set

9.6.1DL (parallel mode only)

9.6.2M

9.6.3H

9.7Set CGRAM address

9.8Set DDRAM address

9.9Read busy flag and address

9.10Write data to CGRAM or DDRAM

9.11Read data from CGRAM or DDRAM

10EXTENDED FUNCTION SET INSTRUCTIONS AND FEATURES

10.1New instructions

10.2Icon control

10.3IM

10.4IB

10.5Normal/Icon mode operation

10.6Screen configuration

10.7Display configuration

10.8TC1, TC2

10.9Set VLCD

10.10Reducing current consumption

11INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE)

12INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE)

12.1Characteristics of the I2C-bus

12.2I2C-bus protocol

12.3Definitions

13LIMITING VALUES

14HANDLING

15DC CHARACTERISTICS

16AC CHARACTERISTICS

17TIMING CHARACTERISTICS

18APPLICATION INFORMATION

18.18-bit operation, 1-line display using internal reset

18.24-bit operation, 1-line display using internal reset

18.38-bit operation, 2-line display

18.4I2C operation, 1-line display

19BONDING PAD LOCATIONS

20PACKAGE OUTLINE

21SOLDERING

21.1Introduction

21.2Reflow soldering

21.3Wave soldering

21.4Repairing soldered joints

22DEFINITIONS

23LIFE SUPPORT APPLICATIONS

24PURCHASE OF PHILIPS I2C COMPONENTS

1997 Apr 04

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Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

1 FEATURES

∙Single-chip LCD controller/driver

∙2-line display of up to 12 characters + 120 icons, or 1-line display of up to 24 characters + 120 icons

∙5 × 7 character format plus cursor; 5 × 8 for kana (Japanese syllabary) and user defined symbols

∙Icon mode: reduced current consumption while displaying icons only(1)

∙Icon blink function

∙On-chip:

–generation of LCD supply voltage, programmable by instruction (external supply also possible)

–temperature compensation of on-chip generated VLCD: −8 to −12 mV/K at 5.0 V

(programmable by instruction)

–generation of intermediate LCD bias voltages

–oscillator requires no external components (external clock also possible)

∙Display data RAM: 80 characters

∙Character generator ROM: 240, 5 × 8 characters

∙Character generator RAM: 16, 5 × 8 characters;

3 characters used to drive 120 icons, 6 characters used if icon-blink feature is used in application

∙4 or 8-bit parallel bus and 2-wire I2C-bus interface

∙CMOS compatible

∙18 row, 60 column outputs

(1)Icon mode is used to save current. When only icons are displayed, a much lower operating voltage VLCD can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as VLCD. Never use the voltage generator in icon mode.

4 ORDERING INFORMATION

∙MUX rates 1 : 18 (for normal operation) and 1 : 2 (for icon-only mode)

∙Uses common 11 code instruction set (extended)

∙Logic supply voltage range, VDD − VSS = 1.8 to 4.0 V (up to 5.5 V if external VLCD is used); chip may be driven with two battery cells

∙Display supply voltage range, VLCD − VSS = 2.2 to 6.5 V

∙Very low current consumption (20 to 200 μA):

–icon mode: <25 μA

–power-down mode: <2.5 μA.

2 APPLICATIONS

∙Telecom equipment

∙Portable instruments

∙Point-of-sale terminals.

3 GENERAL DESCRIPTION

The PCF2113x is a low power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2 line by 12 and 1 line by 24 characters with 5 × 8 dot format.

All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2113x interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I2C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. Three character sets (A, D and E) are currently available (see Figs 7, 8 and 9). Various other character sets can be manufactured on request.

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	PCF2113AU/10/F2	−	chip on flexible film carrier	−
	PCF2113DU/10/F2	−	chip on flexible film carrier	−
	PCF2113DU/F2	−	chip in tray	−
	PCF2113DH/F2	LQFP100	plastic low profile quad flat package; 100 leads; body	SOT407-1
			14 × 14 × 1.4 mm
	PCF2113EU/2/F2	−	chip with bumps in tray	−

1997 Apr 04

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Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

5 BLOCK DIAGRAM

C1 to C60

R1 to R18

18 to 77

9 to 17

60

78 to 86

18

8

BIAS

COLUMN DRIVERS

ROW DRIVERS

VLCD1

VOLTAGE

60

GENERATOR

18

DATA LATCHES

SHIFT REGISTER 18-BIT

7

VLCD

60

VLCD2

SHIFT REGISTER 5 × 12 BIT

GENERATOR

5

OSCILLATOR

2

OSC

CURSOR AND DATA CONTROL

5

VDD1, 2

1, 100

CHARACTER

CHARACTER

GENERATOR

GENERATOR

RAM (128 × 5)

ROM

5, 6

(CGRAM)

(CGROM)

VSS1, 2

16 CHARACTERS

240 CHARACTERS

TIMING

GENERATOR

8

T1

4

7

DISPLAY DATA RAM

3

(DDRAM)

PD

80 CHARACTERS/BYTES

7

7

ADDRESS COUNTER

DISPLAY

(AC)

ADDRESS

COUNTER

7

7

INSTRUCTION

DECODER

8

PCF2113x

DATA

REGISTER

BUSY

INSTRUCTION

(DR)

FLAG

REGISTER

8

8

POWER-ON

RESET

I/O BUFFER

96 to 99

92 to 95

89

91

90

87

88

MGE990

DB0 to DB3/SA0

DB4 to DB7

E

R/W

RS

SCL

SDA

Fig.1

Block diagram.

1997 Apr 04

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Philips Semiconductors						Product specification
LCD controller/driver						PCF2113x
6 PINNING
SYMBOL			PIN		TYPE	DESCRIPTION
VDD1			1		P	supply voltage for all except high voltage generator
OSC			2		I	oscillator/external clock input
PD			3		I	power-down pad input
T1			4		I	test pad (connected to VSS)
VSS1			5		P	ground for all except high voltage generator
VSS2			6		P	ground for high voltage generator
VLCD2			7		O	VLCD output; note 1
VLCD1			8		I	VLCD input; note 2
R9 to R16			9 to 16		O	LCD row driver outputs 9 to 16
R18			17		O	LCD row driver output 18
C60 to C1			18 to 77		O	LCD column driver outputs 60 to 1
R8 to R1			78 to 85		O	LCD row driver outputs 8 to 1
R17			86		O	LCD row driver output 17
SCL			87		I	I2C serial clock input
SDA			88		I/O	I2C serial data input/output
E			89		I	data bus clock input
RS			90		I	register select input
			91		I	read/write input
R/W
DB7			92		I/O	1 bit of 8-bit bidirectional data bus
DB6			93		I/O	1 bit of 8-bit bidirectional data bus
DB5			94		I/O	1 bit of 8-bit bidirectional data bus
DB4			95		I/O	1 bit of 8-bit bidirectional data bus
DB3/SA0			96		I/O	1 bit of 8-bit bi-directional data bus/I2C address pin
DB2			97		I/O	1 bit of 8-bit bidirectional data bus
DB1			98		I/O	1 bit of 8-bit bidirectional data bus
DB0			99		I/O	1 bit of 8-bit bidirectional data bus
VDD2			100		P	supply voltage for high voltage generator; note 3

Notes

1.This is the VLCD output pin, if VLCD is generated internally and has to be connected to VLCD1. If VLCD1 is generated externally, VLCD2 has to be left open or connected to ground.

2.This is the voltage used for the generation of LCD bias levels.

3.This is the supply for the high voltage generator. If VLCD is generated externally, connect VDD2 to VSS.

1997 Apr 04

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Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

VDD1 1 OSC 2 PD 3 T1 4

VSS1 5 VSS2 6

VLCD2 7 VLCD1 8 R9 9 R10 10

R11 11

R12 12

R13 13

R14 14

R15 15

R16 16

R18 17

C60 18

C59 19

C58 20

C57 21

C56 22

C55 23

C54 24

C53 25

V		DB0		DB1		DB2		DB3/SA0		DB4		DB5		DB6		DB7			R/W		RS		E		SDA		SCL		R17		R1		R2		R3		R4		R5		R6		R7		R8		C1		C2
DD2
100		99		98		97		96		95		94		93		92		91			90		89		88		87		86		85		84		83		82		81		80		79		78		77		76

PCF2113x

26		27		28		29		30		31		32		33		34		35		36		37		38		39		40		41		42		43		44		45		46		47		48		49		50
C52		C51		C50		C49		C48		C47		C46		C45		C44		C43		C42		C41		C40		C39		C38		C37		C36		C35		C34		C33		C32		C31		C30		C29		C28

75 C3

74 C4

73 C5

72 C6

71 C7

70 C8

69 C9

68 C10

67 C11

66 C12

65 C13

64 C14

63 C15

62 C16

61 C17

60 C18

59 C19

58 C20

57 C21

56 C22

55 C23

54 C24

53 C25

52 C26

51 C27

MGE989

Fig.2 Pin configuration (LQFP100).

1997 Apr 04

6

Philips Semiconductors

Product specification

LCD controller/driver

PCF2113x

7 PIN FUNCTIONS

NAME

FUNCTION

DESCRIPTION

RS

register select

RS selects the register to be accessed for read and write when the device is

controlled by the parallel interface. There is an internal pull-up on this pin.

RS = logic 0 selects the instruction register for write and the Busy Flag and Address

Counter for read.

RS = logic 1 selects the data register for both read and write.

read/write

R/W

R/W selects either the read (R/W = logic 1) or write (R/W = logic 0) operation when

the device is controlled by the parallel interface. There is an internal pull-up on this

pin.

E

data bus clock

The E pin is set HIGH to signal the start of a read or write operation when the device

is controlled by the parallel interface. Data is clocked in or out of the chip on the

negative edge of the clock. Note that this pin must be tied to logic 0 (VSS) when

I2C-bus control is used.

DB7 to DB0

data bus

The parallel interface of the device. This bi-directional, 3-state data bus transfers

data between the system controller and the PCF2113x. There is an internal pull-up

on each of the data lines.

DB7 to DB0 must be connected to V

or left open circuit when I2C-bus control is

DD

used. Note that DB3 shares the same pin as SA0.

In 4-bit operations only DB7 to DB4 are used, and DB3 to DB0 must be left open

circuit. See note 1.

DB7 may be used as the Busy Flag, signalling that internal operations are not yet

completed.

C1 to C60

column driver

These pins output the data for columns.

outputs

R1 to R18

row driver

These pins output the row select waveforms to the display.

outputs

R17 and R18 drive the icons.

VLCD

LCD power

Positive power supply for the liquid crystal display. This may be generated on-chip or

supply

supplied externally.

OSC

oscillator

When the on-chip oscillator is used this pin must be connected to VDD.

An external clock signal, if used, is input at this pin.

SCL

serial clock line

Input for the I2C-bus clock signal.

SCL must be connected to VSS or VDD when the parallel interface is used.

SDA

serial data line

I/O for the I2C-bus data line.

SDA must be connected to VSS or VDD when the parallel interface is used.

SA0

address pin

The hardware sub-address line is used to program the device sub-address for two

different PCF2113xs on the same I2C bus. Note that SA0 shares the same pin as

DB3.

T1

test pad

T1 must be connected to VSS and is not user accessible.

PD

power-down pad

PD selects chip power-down mode. For normal operation PD = logic 0.

Note

1.If the 4-bit interface is used without reading out from the PCF2113x (i.e. R/W is set permanently to logic 0), the unused ports DB0 to DB3 can either be set to VSS or VDD instead of leaving them open.

1997 Apr 04

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Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

8 FUNCTIONAL DESCRIPTION (see Fig.1)

8.1LCD supply voltage generator

The LCD supply voltage may be generated on-chip. The voltage generator is controlled by two internal 6-bit

registers, VA and VB. The nominal LCD operating voltage at room temperature is given by the relationships:

VOP(nom) = [(integer value of register) × 0.08 + 1.9] V

8.2Programming ranges (Tref = 27 °C)

Programmed value range: 1 to 63.

Voltage range: 1.90 to 6.84 V.

Values producing more than 6.5 V at operating temperature are not allowed. Operation above this voltage may damage the device. When programming the operating voltage the VLCD temperature coefficient must be taken into account.

Values below 2.2 V are below the specified operating range of the chip and are therefore not allowed.

Value 0 for VA and VB switches the generator off.

Usually register VA is programmed with the voltage for character mode and register VB with the voltage for icon mode. VB must be programmed to FF in character mode and VA must be programmed to 00 in icon mode.

When VLCD is generated on-chip the VLCD pins should be decoupled to VSS with a suitable capacitor. The generated

VLCD is independent of VDD and is temperature compensated. When the generator is switched off an

external voltage may be supplied at connected pins

VLCD1,2. VLCD1,2 may be higher or lower than VDD if external VLCD is used. If internally generated it must not

be lower than VDD and VDD ≤ 4V .

8.3LCD bias voltage generator

The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels and is given by the relationships given in Tables 1 and 2. Using a 5-level bias

scheme for 1 : 18 maximum rate allows VLCD < 5 V for most LCD liquids.

Table 1		Optimum/maximum values for VOP (off pixels start darkening; Voff = Vth)
MUX RATE			NUMBER OF LEVELS	Von/Vth		VOP/Vth	VOP (typical; for Vth = 1.4 V)
1	: 18		5	1.272		3.7	5.2 V
1	: 2		3	2.236		2.283	3.9 V
Table 2		Minimum values for VOP (on pixels clearly visible; Von > Vth)
MUX RATE			NUMBER OF LEVELS	Von/Vth		VOP/Vth	VOP (typical; for Vth = 1.4 V)
1	: 18		5	1.12		3.2	4.6 V
1	: 2		3	1.2		1.5	2.1 V

8.4Oscillator

The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pin must be connected to VDD.

8.5External clock

If an external clock is to be used this is input at the OSC pin. The resulting display frame frequency is given by

fOSC

fframe = -------------

3 072

Only in the power-down state is the clock allowed to be stopped (OSC connected to Vss), otherwise the LCD is frozen in a DC state.

8.6Power-on reset

The on-chip power-on reset block initializes the chip after power-on or power failure. This is a synchronous reset and requires 3 OSC cycles to be executed.

1997 Apr 04

8

Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x
8.7 Power-down mode	8.11 Display Data RAM (DDRAM)

The chip can be put into power-down mode where all static currents are switched off (no internal oscillator, no bias level generation, all LCD-outputs are internally connected to VSS) when PD = logic 1.

During power-down, the whole chip is reset and will restart with a clear display after power-down. Therefore, the whole chip has to be initialized after a power-down as after initial powerup.

The device should be put into ‘display off’ mode (instruction ‘Display control’) before putting the chip in power-down mode, otherwise the LCD output voltages are not defined.

8.8Registers

The PCF2113x has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select signal (RS) determines which register will be accessed. The instruction register stores instruction codes such as ‘Display clear’ and ‘Cursor shift’, and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written from but not read by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the ‘Read data’ instruction.

8.9Busy Flag

The Busy Flag indicates the free/busy status of the PCF2113x. Logic 1 indicates that the chip is busy and further instructions will not be accepted. The Busy Flag is output to pin DB7 when RS = logic 0 and R/W = logic 1. Instructions should only be written after checking that the Busy Flag is logic 0 or waiting for the required number of cycles.

8.10Address Counter (AC)

The Address Counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the instructions ‘Set CGRAM address’ and

‘Set DDRAM address’. After a read/write operation the Address Counter is automatically incremented or decremented by 1. The Address Counter contents are output to the bus (DB6 to DB0) when RS = logic 0 and R/W = logic 1.

The DDRAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic DDRAM-to-display mapping is shown in Fig.3. With no display shift the characters represented by the codes in the first 24 RAM locations starting at address 00 in line 1 are displayed. Figures 4 and 5 show the display mapping for right and left shift respectively.

When data is written to or read from the DDRAM wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together.

The address ranges and wraparound operations for the various modes are shown in Table 3.

Table 3 Address space and wrap-around operation

MODE	1 × 24	2 × 12
address space	00 to 4F	00 to 27; 40 to 67
read/write wrap-around	4F to 00	27 to 40; 67 to 00
(moves to next line)
display shift wrap-around	4F to 00	27 to 00; 67 to 40
(stays within line)

8.12Character Generator ROM (CGROM)

The Character Generator ROM (CGROM) generates 240 character patterns in 5 × 8 dot format from 8-bit character codes. Figures 7, 8 and 9 show the character sets that are currently implemented.

8.13Character Generator RAM (CGRAM)

Up to 16 user defined characters may be stored in the Character Generator RAM (CGRAM). Some CGRAM characters (see Fig.17) are also used to drive icons (6 if icons blink and both icon rows are used in application; 3 if no blink but both icon rows are used in application; 0 if no icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.7). Figure 10 shows the addressing principle for the CGRAM.

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Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x
8.14 Cursor control circuit	8.16 LCD row and column drivers

The cursor control circuit generates the cursor (underline and/or cursor blink as shown in Fig.6) at the DDRAM address contained in the Address Counter. When the Address Counter contains the CGRAM address the cursor will be inhibited.

8.15Timing generator

The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses.

The PCF2113x contains 18 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows.

The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 11, 12 and 13 show typical waveforms. Unused outputs should be left unconnected.

handbook, full pagewidth	display	1	2	3	4	5	22 23 24						non-displayed DDRAM addresses
	position
	DDRAM	00	01	02	03	04		15	16	17	18		19						4C		4D			4E	4F
	address
	1-line display
												non-displayed DDRAM address
		1	2	3	4	5	10 11 12																	line 1
		00	01	02	03	04		09	0A	0B	0C		0D		24	25		26		27
	DDRAM
		1	2	3	4	5	10 11 12
	address
		40	41	42	43	44		49	4A	4B	4C		4D		64	65		66		67				line 2
	2-line display																MGE991

Fig.3 DDRAM-to-display mapping: no shift.

display	1	2	3	4	5	22 23 24
position
DDRAM	4F	00	01	02	03		14	15	16
address
1-line display
	1	2	3	4	5	10 11 12
	27	00	01	02	03		08	09	0A	line 1
DDRAM
	1	2	3	4	5	10 11 12
address
	67	40	41	42	43		48	49	4A	line 2

MGE992

2-line display

Fig.4 DDRAM-to-display mapping: right shift.

1997 Apr 04

10

Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

display	1	2	3	4	5	22 23 24
position
DDRAM	01	02	03	04	05		16	17	18
address
1-line display
	1	2	3	4	5	10 11 12
	01	02	03	04	05		0A	0B	0C	line 1
DDRAM
	1	2	3	4	5	10 11 12
address
	41	42	43	44	45		4A	4B	4C	line 2
2-line display								MGE993

Fig.5 DDRAM-to-display mapping: left shift.

cursor

MGA801

5 x 7 dot character font

alternating display

cursor display example blink display example

Fig.6	Cursor and blink display examples.
1997 Apr 04	11

Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

handbook,	full pagewidth
		upper
	lower	4 bits		0000	0001	0010	0011	0100	0101	0110	0111		1000	1001	1010	1011	1100	1101	1110	1111
	4 bits
	xxxx	0000		1
	xxxx	0001		2
	xxxx	0010		3
	xxxx	0011		4
	xxxx	0100		5
	xxxx	0101		6
	xxxx	0110		7
	xxxx	0111		8
	xxxx	1000		9
	xxxx	1001		10
	xxxx	1010		11
	xxxx	1011		12
	xxxx	1100		13
	xxxx	1101		14
	xxxx	1110		15
	xxxx	1111		16
																				MGE994

Fig.7 Character set ‘A’ in CGROM: PCF2113A.

1997 Apr 04

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Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

handbook,	full pagewidth
		upper
	lower	4 bits	0000	0001	0010	0011	0100	0101	0110	0111	1000	1001	1010	1011	1100	1101	1110	1111
	4 bits
	xxxx	0000	1
	xxxx	0001	2
	xxxx	0010	3
	xxxx	0011	4
	xxxx	0100	5
	xxxx	0101	6
	xxxx	0110	7
	xxxx	0111	8
	xxxx	1000	9
	xxxx	1001	10
	xxxx	1010	11
	xxxx	1011	12
	xxxx	1100	13
	xxxx	1101	14
	xxxx	1110	15
	xxxx	1111	16

MGD688

Fig.8 Character set ‘D’ in CGROM: PCF2113D.

1997 Apr 04

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Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

handbook,	full pagewidth
		upper
	lower	4 bits		0000	0001	0010	0011	0100	0101	0110	0111	1000	1001	1010	1011	1100	1101	1110	1111
	4 bits
	xxxx	0000		1
	xxxx	0001		2
	xxxx	0010		3
	xxxx	0011		4
	xxxx	0100		5
	xxxx	0101		6
	xxxx	0110		7
	xxxx	0111		8
	xxxx	1000		9
	xxxx	1001		10
	xxxx	1010		11
	xxxx	1011		12
	xxxx	1100		13
	xxxx	1101		14
	xxxx	1110		15
	xxxx	1111		16

MGD689

Fig.9 Character set ‘E’ in CGROM: PCF2113E.

1997 Apr 04

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Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

handbook, full pagewidthcharacter codes														CGRAM								character patterns													character code
					(DDRAM data)									address									(CGRAM data)												(CGRAM data)
7			6		5	4	3	2	1	0	6		5	4	3	2	1	0				4	3		2	1			0					4	3	2	1	0
			higher						lower				higher				lower			higher					lower
				order					order				order				order				order				order
				bits					bits				bits				bits				bits					bits
0			0		0	0	0	0	0	0	0		0	0	0	0	0	0											0					1	1	1	1	0
																0	0	1						0	0	0						character		1	0	0	0	1
																0	1	0						0	0	0								1	0	0	0	1
																0	1	1											0			pattern		1	1	1	1	0
																1	0	0						0			0		0		example 1			1	0	1	0	0
																1	0	1						0	0				0					1	0	0	1	0
																1	1	0						0	0		0						cursor	1	0	0	0	1
																1	1	1				0		0	0	0			0					0	0	0	0	0
																																	position	1	0	0	0	1
0			0		0	0	0	0	0	1	0		0	0	1	0	0	0						0	0	0
																0	0	1				0			0				0			character		0	1	0	1	0
																0	1	0																1	1	1	1	1
																0	1	1				0	0				0		0			pattern		0	0	1	0	0
																1	0	0													example 2			1	1	1	1	1
																1	0	1				0	0				0		0					0	0	1	0	0
																1	1	0				0	0				0		0					0	0	1	0	0
																1	1	1				0	0		0		0		0					0	0	0	0	0
0			0		0	0	0	0	1	0	0		0	1	0	0	0	0																			MGE995
																0	0	1
0			0		0	0	1	1	1	1	1		1	1	1	1	0	0
0			0		0	0	1	1	1	1	1		1	1	1	1	0	1
0			0		0	0	1	1	1	1	1		1	1	1	1	1	0
0			0		0	0	1	1	1	1	1		1	1	1	1	1	1

Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.

CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th position will appear in the cursor position.

Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in this figure.

CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display.

Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ instruction. Bit 6 can be set using the ‘set DDRAM address’ instruction in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘Read busy flag and address’ instruction.

Fig.10 Relationship between CGRAM addresses and data and display patterns.

1997 Apr 04

15

Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

frame n frame n + 1

VLCD V2

ROW 1 V3/V4 V5 VSS

VLCD

V2

ROW 9 V3/V4

V5

VSS

VLCD

V2

ROW 2 V3/V4

V5

VSS

VLCD

V2

COL1 V3/V4

V5

VSS

VLCD

V2

COL2 V3/V4

V5

VSS

VOP

0.5VOP

0.25VOP state 1 0 V

−0.25VOP

−0.5VOP

−VOP

VOP

0.5VOP

0.25VOP state 2 0 V

−0.25VOP

−0.5VOP

−VOP

MGE996

1

2

3

18

1

2

3

18

state 1 (ON)

state 2 (OFF)

R1

R2

R3

R4

R5

R6

R7

R8

R9

Fig.11 Typical LCD waveforms; character mode.

1997 Apr 04

16

Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

frame n frame n + 1

VLCD ROW 17 2/3 1/3 VSS

VLCD ROW 18 2/3 1/3 VSS

VLCD ROW 1 to 16 2/3 1/3 VSS

VLCD

2/3 COL 1 ON/OFF 1/3

VSS

VLCD

2/3 COL 2 OFF/ON 1/3

VSS

VLCD

2/3 COL 3 ON/ON 1/3

VSS

VLCD

2/3 COL 4 OFF/OFF 1/3

VSS

only icons are driven (MUX 1 : 2)

MGE997

Fig.12 MUX 1 : 2 LCD waveforms; icon-mode.

1997 Apr 04

17

Philips Semiconductors	Product specification
LCD controller/driver	PCF2113x

handbook, full pagewidth VPIXEL

	VOP
	2/3 VOP
state 1	1/3 VOP
COL 1 -	0
ROW 17	−1/3 VOP
	−2/3 VOP
	−VOP
	VOP
	2/3 VOP
state 2	1/3 VOP
COL 2 -	0
ROW 17	−1/3 VOP
	−2/3 VOP
	−VOP
	VOP
	2/3 VOP
state 3	1/3 VOP
COL 1 -	0
ROW 1 to 16	−1/3 VOP
	−2/3 VOP
	−VOP

VON(rms) = 0.745VOP.

VOFF(rms) = 0.333VOP.

VON

D = ------------- = 2.23

VOFF

frame n

frame n + 1

state 1 (ON)

state 2 (OFF)

R17

R18

R1-16

state 3 (OFF)

MGE998

Fig.13 MUX 1 : 2 LCD waveforms; icon-mode.

1997 Apr 04

18