Philips P87CE560EFB-01, P87CE560EFB-007, P87CE560EFB-018, P83CE560EFB-100, P80CE560EFB-00 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

P8xCE560

8-bit microcontroller

Product specification			1997 Aug 01
File under Integrated Circuits, IC20

Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

CONTENTS

1FEATURES

2GENERAL DESCRIPTION

2.1Electromagnetic Compatibility (EMC)

2.2Recommendation on ALE

3ORDERING INFORMATION

4BLOCK DIAGRAM

5FUNCTIONAL DIAGRAM

6PINNING INFORMATION

6.1Pinning diagram

6.2Pin description

7FUNCTIONAL DESCRIPTION

8MEMORY ORGANIZATION

8.1Program Memory

8.2Internal Data Memory

8.3Addressing

9I/O FACILITIES

10PULSE WIDTH MODULATED OUTPUTS (PWM)

10.1Prescaler Frequency Control Register (PWMP)

10.2Pulse Width Register 0 (PWM0)

10.3Pulse Width Register 1 (PWM1)

11 ANALOG-TO-DIGITAL CONVERTER (ADC)

11.1ADC features

11.2ADC functional description

11.3ADC timing

11.4ADC configuration and operation

11.5ADC during Idle and Power-down mode

11.6ADC resolution and characteristics

11.7ADC after reset

11.8ADC Special Function Registers

12 TIMERS/COUNTERS

12.1Timer 0 and Timer 1

12.2Timer T2

12.3Watchdog Timer T3

13 SERIAL I/O PORTS

13.1Serial I/O Port: SIO0 (UART)

13.2Serial I/O Port: SIO1 (I2C-bus interface)

14 INTERRUPT SYSTEM

14.1Interrupt Enable Registers

14.2Interrupt Handling

14.3Interrupt Priority Structure

14.4Interrupt vectors

14.5Interrupt Enable and Priority Registers

15 POWER REDUCTION MODES

15.1Idle mode

15.2Power-down mode

15.3Wake-up from Power-down mode

15.4Status of external pins

15.5Power Control Register (PCON)

16 OSCILLATOR CIRCUITS

16.1XTAL1; XTAL2 oscillator: standard 80C51

16.2XTAL3; XTAL4 oscillator: 32 kHz PLL oscillator (with Seconds timer)

17 RESET CIRCUITRY

17.1Power-on Reset

18 INSTRUCTION SET

18.1Addressing modes

18.280C51 family instruction set

18.3Instruction set description

19LIMITING VALUES

20DC CHARACTERISTICS

21AC CHARACTERISTICS

22EPROM CHARACTERISTICS

22.1Programming and verification

22.2Security

23SPECIAL FUNCTION REGISTERS OVERVIEW

24PACKAGE OUTLINES

25SOLDERING

25.1Introduction

25.2Reflow soldering

25.3Wave soldering

25.4Repairing soldered joints

26DEFINITIONS

27LIFE SUPPORT APPLICATIONS

28PURCHASE OF PHILIPS I2C COMPONENTS

1997 Aug 01

2

Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

1 FEATURES

∙80C51 Central Processing Unit (CPU)

∙64 kbytes ROM (only P83CE560)

∙64 kbytes EPROM (only P87CE560)

∙ROM/EPROM Code protection

∙2048 bytes RAM, expandable externally to 64 kbytes

∙Two standard 16-bit timers/counters

∙An additional 16-bit timer/counter coupled to four capture registers and three compare registers

∙A 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog inputs and programmable autoscan

∙Two 8-bit resolution, Pulse Width Modulation outputs

∙Five 8-bit I/O ports plus one 8-bit input port shared with analog inputs

∙I2C-bus serial I/O port with byte oriented master and slave functions

∙Full-duplex UART compatible with the standard 80C51

∙On-chip Watchdog Timer

∙15 interrupt sources with 2 priority levels (2 to 6 external sources possible)

∙Phase-Locked Loop (PLL) oscillator with 32 kHz reference and software-selectable system clock frequency

∙Seconds timer

∙Software enable/disable of ALE output pulse

∙Electromagnetic compatibility improvements

∙Wake-up from Power-down by external or seconds interrupt

∙Frequency range for 80C51-family standard oscillator: 3.5 to 16 MHz

∙Extended temperature range: −40 to +85 C

∙Supply voltage: 4.5 to 5.5 V.

2 GENERAL DESCRIPTION

The 8-bit microcontrollers P80CE560, P83CE560 and P87CE560 - hereafter referred to as P8xCE560 - are manufactured in an advanced CMOS process and are derivatives of the 80C51 microcontroller family.

The P8xCE560 contains a volatile 2048 bytes read/write Data Memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level,

nested interrupt structure, an 8-input ADC, a dual Digital-to-Analog Convertor (DAC), Pulse Width Modulated interface, two serial interfaces (UART and I2C-bus), a Watchdog Timer, an on-chip oscillator and timing circuits.

The P8xCE560 is available in 3 versions:

∙P80CE560: ROMless version

∙P83CE560: containing a non-volatile 64 kbytes mask programmable ROM

∙P87CE560: containing 64 kbytes programmable EPROM/OTP.

The P8xCE560 is a control-oriented CPU with on-chip Program and Data Memory; it cannot be extended with external Program Memory. It can access up to 64 kbytes of external Data Memory. For systems requiring extra capability, the P8xCE560 can be expanded using standard TTL compatible memories and peripherals.

In addition, the P8xCE560 has two software selectable reduced power modes: Idle mode and Power-down mode. The Idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.The Power-down mode can be terminated by an external reset, by the seconds interrupt and by any one of the two external interrupts;

see Section 15.3.

The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic as well as bit-handling capabilities. The instruction set of the P8xCE560 is the same as the 80C51 and consists of over 100 instructions: 49 one-byte, 45 two-byte, and

17 three-byte. With a 16 MHz system clock, 58% of the instructions are executed in 0.75 μs and 40% in 1.5 μs. Multiply and divide instructions require 3 μs.

1997 Aug 01

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

2.1Electromagnetic Compatibility (EMC)

Primary attention is paid to the reduction of electromagnetic emission of the microcontroller P8xCE560. The following features reduce the electromagnetic emission and additionally improve the electromagnetic susceptibility:

·Four digital part supply voltage pins (VDD1 to VDD4) and four digital ground pins (VSS1 to VSS4) are placed as pairs of VDDn and VSSn at two adjacent pins, at each side of the package.

·Separated VDD pins for the internal logic and the port buffers.

·Internal decoupling capacitance improves the EMC radiation behaviour and the EMC immunity.

·External capacitors should be connected across

associated VDDn and VSSn pins (i.e. VDD1 and VSS1). Lead length should be as short as possible. Ceramic chip capacitors are recommended (100 nF).

3 ORDERING INFORMATION

2.2Recommendation on ALE

For applications that require no external memory or temporarily no external memory: the ALE output signal (pulses at a frequency of 1¤6 ´ fOSC) can be disabled under software control (bit RFI; SFR: PCON.5); if disabled, no ALE pulse will occur. ALE pin will be pulled down internally, switching an external address latch to a quiet state. The MOVX instruction will still toggle ALE (external Data Memory is accessed). ALE will retain its normal HIGH value during Idle mode and a LOW value during Power-down mode while in the ‘RFI reduction mode’.

Additionally during internal access (EA = 1) ALE will toggle normally when the address exceeds the internal Program Memory size. During external access (EA = 0) ALE will always toggle normally, whether the flag ‘RFI’ is set or not.

	TYPE NUMBER		PACKAGE		FREQUENCY	TEMPERATURE
		NAME	DESCRIPTION	VERSION	RANGE (MHZ)	RANGE (°C)
	P80CE560EFB(1)		plastic quad flat package;
	P83CE560EFB/nnn(2)	QFP80	80 leads (lead length 1.95 mm);	SOT318-2	3.5 to 16	-40 to +85
			body 14 ´ 20 ´ 2.8 mm
	P87CE560EFB(3)

Notes

1.ROMless type.

2.ROM coded type; ‘nnn’ denotes the ROM code number.

3.EPROM/OTP type.

1997 Aug 01

4

01 Aug 1997

5

ADC0 to ADC7

PWM0

Vref(p)(A)

SDA SCL

XTAL3

ADEXS

VDD

VSS

PWM1

T0

T1

INT0

INT1

VDDA VSSA

Vref(n)(A)

XTAL4

(4)

(4)

(4)

(4)

(6)

SELXTAL

RSTIN

TWO 16 - BIT

PROGRAM

DATA MEMORY

PLL

256 bytes

TIMER/

MEMORY

I2C-BUS

OSCILLATOR

RAM

DUAL

XTAL1

EVENT

CPU

ADC

SERIAL

+

64 kbytes

+

PWM

COUNTERS

I/O

'SECONDS'

XTAL2

ROM/

1792 bytes

(T0,T1)

TIMER

EPROM (7)

AUX-RAM

EA

80C51

ALE

core

excluding

PSEN

ROM/RAM

8-bit internal bus

WR

(4)

16

P8xCE560

RD

(4)

AD0 to AD7

FOUR

16-BIT

THREE

PARALLEL

SERIAL

8-BIT

16-BIT

COMPARATOR

WATCHDOG

(1)

TIMER/

16

I/O PORTS

16-BIT

COMPARATORS

UART

I/O

EVENT

OUTPUT

TIMER

&

CAPTURE

WITH

PORT

PORTS

COUNTER

SELECTION

(T3)

A8 to A15

EXT. BUS

LATCHES

(T2)

REGISTERS

(3)

		(4)	(4)			(2)		(2)	(5)
P0	P1 P2 P3	TXD	RXD	P5	P4	CT0I to CT3I	T2	RT2	CMSR0 to CMSR5 RSTOUT	EW
									CMT0, CMT1

MBH074

(1)Alternative function of Port 0.

(2)Alternative function of Port 1.

(3)Alternative function of Port 2.

(4)Alternative function of Port 3.

(5)Alternative function of Port 5.

(6)Alternative function of Port 6.

(7)Not present in P80CE560.

Fig.1 Block diagram P8xCE560.

DIAGRAM BLOCK 4

microcontroller bit-8

P8xCE560

Semiconductors Philips

specification Product

Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560
5 FUNCTIONAL DIAGRAM

XTAL1

XTAL2

							(1)
				EA/VPP
									PSEN
										(1)
				ALE/PROG
								PWM0
								PWM1
									SCL
									SDA
						ADEXS
					Vref(p)(A)
					Vref(n)(A)
alternative function
						STADC
ADC0		0
ADC1				1
ADC2				2
ADC3				3
				PORT 5
ADC4				4
ADC5				5
ADC6				6
ADC7				7
CMSR0			0
CMSR1			1
CMSR2			2
CMSR3			3
				PORT 4
CMSR4			4
CMSR5			5
CMT0			6
CMT1			7

RSTIN

RSTOUT

EW

P8xCE560

MBH075

SELXTAL1

XTAL4

XTAL3

0

1

2 3

PORT 0

4

5

6 7

0

1

2

3

PORT 1

4

5

6 7

0

1

2

3

PORT 2

4

5

6 7

0

1

2

3

PORT 3

4

5

6 7

VSSA

VDDA

VSS (2)

VDD

alternative function

	AD0
	AD1
	AD2	LOW ORDER
	AD3
		ADDRESS
	AD4	AND
		DATA BUS
	AD5
	AD6
	AD7

CT0I/INT2

CT1I/INT3

CT2I/INT4

CT3I/INT5

T2

RT2

	A8
	A9
	A10	HIGH ORDER
	A11
		ADDRESS
	A12
		BUS
	A13
	A14
	A15

RXD/DATA

TXD/CLOCK

INT0

INT1

T0

T1

WR

RD

(1)Only the P87CE560 with an alternative function.

(2)VDDA/VSSA - 2 analog supply pairs; VDD/VSS - 4 digital supply pairs.

Fig.2 Functional diagram.

1997 Aug 01

6

Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

6 PINNING INFORMATION

6.1Pinning diagram

							SELXTAL1		XTAL4		XTAL3		SSA2		DDA2		P0.0/AD0		P0.1/AD1		P0.2/AD2		P0.3/AD3		P0.4/AD4		P0.5/AD5		P0.6/AD6		P0.7/AD7		SS4		DD4	(1) PP
																																					EA/V
													V		V																		V		V
							80		79		78		77		76		75		74		73		72		71		70		69		68		67		66		65
Vref(n)(A)
					1
Vref(p)(A)
					2
VSSA1
					3
VDDA1
					4
P5.7/ADC7					5
P5.6/ADC6
					6
P5.5/ADC5
					7
P5.4/ADC4
					8
P5.3/ADC3
					9
P5.2/ADC2
					10
P5.1/ADC1
					11
P5.0/ADC0
					12															P8xCE560
	VSS1
					13
	VDD1
					14
ADEXS
					15
	PWM0				16
PWM1					17
	EW				18
P4.0/CMSR0					19
P4.1/CMSR1
					20
P4.2/CMSR2					21
P4.3/CMSR3
					22
RSTOUT
					23
P4.4/CMSR4
					24
							25		26		27		28		29		30		31		32		33		34		35		36		37		38		39		40
							P4.5/CMSR5		P4.6/CMT0		P4.7/CMT1		V		V		RSTIN		P1.0/CT0I/INT2		P1.1/CT1I/INT3		P1.2/CT2I/INT4		P1.3/CT3I/INT5		P1.4/T2		P1.5/RT2		P1.6		P1.7		SCL		SDA
													DD2		SS2

(1) Only the P87CE560 with this alternative function.

Fig.3 Pin configuration QFP80/SOT318 version.

											(1)
64	ALE/PROG
63		PSEN
	P2.7/A15
62
61	P2.6/A14
60	P2.5/A13
59	P2.4/A12
58	P2.3/A11
	P2.2/A10
57
56	P2.1/A9
	P2.0/A8
55
	VSS3
54
	VDD3
53
52	XTAL1
	XTAL2
51
		n.c.
50
49		n.c.
48	P3.7/RD
47	P3.6/WR
	P3.5/T1
46
	P3.4/T0
45
44	P3.3/INT1
43	P3.2/INT0
	P3.1/TXD
42
41	P3.0/RXD
	MBH076

1997 Aug 01

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

6.2Pin description

Table 1 Pin description for QFP80 (SOT318-2)

To avoid a ‘latch-up’ effect at power-on: VSS − 0.5 V < ‘voltage at any pin at any time’ < VDD + 0.5 V.

SYMBOL

PIN

DESCRIPTION

Vref(n)(A)

1

Low-end of ADC reference resistor.

Vref(p)(A)

2

High-end of ADC reference resistor.

VSSA1

3

Ground, analog part. For ADC receiver and reference voltage.

VDDA1

4

Power supply, analog part (+5 V). For ADC receiver and reference voltage.

P5.7/ADC7 to

5 to 12

Port 5 (P5.7 to P5.0): 8-bit input port lines;

P5.0/ADC0

ADC7 to ADC0: 8 input channels to the ADC.

VSS1 to VSS4

13, 29,

Ground; digital part; circuit ground potential. VSS1, VSS2, VSS4 must be connected,

54, 67

VSS3 is internally connected to digital ground, but should be connected externally.

VDD1 to VDD4

14, 28,

Power supply, digital part (+5 V). Power supply pins during normal operation and

53, 66

power reduction modes. All pins must be connected.

ADEXS

15

Start ADC operation. Input starting ADC, triggered by a programmable edge; ADC

operation can also be started by software. This pin must not float.

16

Pulse Width Modulation output 0.

PWM0

17

Pulse Width Modulation output 1.

PWM1

18

Enable Watchdog Timer (WDT): enable for T3 Watchdog Timer and disable

EW

Power-down mode. This pin must not float.

P4.0/CMSR0 to

19 to 22,

Port 4 (P4.0 to P4.7): 8-bit quasi-bidirectional I/O port lines;

P4.5/CMSR5

24, 25

CMSR0 to CMSR5: compare and set/reset outputs for Timer T2;

CMT0 to CMT1: compare and toggle outputs for Timer T2.

P4.6/CMT0 to

26, 27

P4.7/CMT1

RSTOUT

23

Reset output of the P8xCE560 for resetting peripheral devices during initialization

and Watchdog Timer overflow.

RSTIN

30

Reset input to reset the P8xCE560.

P1.0/CT0I/INT2 to

31 to 34

Port 1 (P1.0 to P1.7): 8-bit quasi-bidirectional I/O port lines;

P1.3/CT3I/INT5

CT0I to CT3I: Capture timer inputs for Timer T2;

INT2 to INT5: external interrupts 2 to 5;

P1.4/T2 to

35, 36

T2: T2 event input (rising edge triggered);

P1.5/RT2

RT2: T2 timer reset input (rising edge triggered).

P1.6 to P1.7

37 to 38

SCL

39

I2C-bus serial clock I/O port. If SCL is not used, it must be connected to VSS.

SDA

40

I2C-bus serial data I/O port. If SDA is not used, it must be connected to VSS.

P3.0/RXD

41

Port 3 (P3.0 to P3.7): 8-bit quasi-bidirectional I/O port lines;

RXD: Serial input port;

P3.1/TXD

42

TXD: Serial output port;

P3.2/INT0

43

INT0: External interrupt input 0;

44

P3.3/INT1

: External interrupt input 1;

INT1

P3.4/T0

45

T0: Timer 0 external interrupt input;

T1: Timer 1external interrupt input;

P3.5/T1

46

WR

: External Data Memory Write strobe;

P3.6/WR

47

RD: External Data Memory Read strobe.

48

P3.7/RD

n.c.

49, 50

Not connected pins.

1997 Aug 01

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Philips Semiconductors

Product specification

8-bit microcontroller

P8xCE560

SYMBOL

PIN

DESCRIPTION

XTAL2

51

Crystal pin 2: output of the inverting amplifier that forms the oscillator.

Left open-circuit when an external oscillator clock is used.

XTAL1

52

Crystal pin 1: input to the inverting amplifier that forms the oscillator, and input to the

internal clock generator. Receives the external oscillator clock signal when an external

oscillator is used. Must be connected to logic HIGH if the PLL oscillator is selected

(SELXTAL1 = LOW).

P2.0/A08 to

55 to 62

Port 2 (P2.0 to P2.7): 8-bit quasi-bidirectional I/O port lines;

P2.7/A15

A08 to A15: High-order address byte for external memory.

63

Program Store Enable output: read strobe to the external Program Memory via

PSEN

Ports 0 and 2. Is activated twice each machine cycle during fetches from external

Program Memory. When executing out of external Program Memory two activations of

PSEN

are skipped during each access to external Data Memory.

PSEN

is not

activated (remains HIGH) during no fetches from external Program Memory.

PSEN

can sink/source 8 LSTTL inputs. It can drive CMOS inputs without external pull-ups.

64

Address Latch Enable output. Latches the low byte of the address during access of

ALE/PROG

external memory in normal operation. It is activated every six oscillator periods except

during an external Data Memory access. ALE can sink/source 8 LSTTL inputs. It can

drive CMOS inputs without an external pull-up. To prohibit the toggling of ALE pin (RFI

noise reduction) the bit RFI (SFR: PCON.5) must be set by software; see Section 2.2.

PROG

: the programming pulse input; alternative function for the P87CE560.

65

External Access input. If, during reset,

is held at a TTL level HIGH the CPU

EA/VPP

EA

executes out of the internal Program Memory. If, during reset,

EA

is held at a TTL level

LOW the CPU executes out of external Program Memory via Port 0 and Port 2.

EA

is

not allowed to float.

EA

is latched during reset and don’t care after reset.

VPP: the programming supply voltage; alternative function for the P87CE560.

P0.7/AD7 to

68 to 75

Port 0 (P0.7 to P0.0): 8-bit open-drain bidirectional I/O port lines;

P0.0/AD0

AD7 to AD0: Multiplexed Low-order address and Data bus for external memory.

VDDA2

76

Power supply, analog part (+5 V). For PLL oscillator.

VSSA2

77

Ground, analog part. For PLL oscillator.

XTAL3

78

Crystal pin 3: output of the inverting amplifier that forms the 32 kHz oscillator.

XTAL4

79

Crystal pin 2: input to the inverting amplifier that forms the 32 kHz oscillator. XTAL3 is

pulled LOW if the PLL oscillator is not selected (SELXTAL1 = 1) or if reset is active.

SELXTAL1

80

SELXTAL1 = HIGH, selects the HF oscillator, using the XTAL1/XTAL2 crystal.

If SELXTAL1 = LOW the PLL is selected for clocking of the controller, using the

XTAL3/XTAL4 crystal.

1997 Aug 01

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560
7 FUNCTIONAL DESCRIPTION
The P8xCE560 is a stand-alone high-performance
microcontroller designed for use in real time applications
such as instrumentation, industrial control, medium to
high-end consumer applications and specific automotive
control applications.
In addition to the 80C51 standard functions, the device
provides a number of dedicated hardware functions for
these applications.
The P8xCE560 is a control-oriented CPU with on-chip
program and Data Memory, but it cannot be extended with
external Program Memory. It can access up to 64 kbytes
of external Data Memory. For systems requiring extra
capability, the P8xCE560 can be expanded using standard
memories and peripherals.
The functional description of the device is described in:
Chapter 8 “Memory organization”
Chapter 9 “I/O facilities”
Chapter 10 “Pulse Width Modulated outputs”
Chapter 11 “Analog-to-Digital Converter (ADC)”
Chapter 12 “Timers/counters”
Chapter 13 “Serial I/O ports”
Chapter 14 “Interrupt system”
Chapter 15 “Reduced power modes”
Chapter 16 “Oscillator circuits”
Chapter 17 “Reset circuitry”.

1997 Aug 01

10

Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560
8 MEMORY ORGANIZATION	8.2 Internal Data Memory

The Central Processing Unit (CPU) manipulates operands in three memory spaces; these are the 64 kbytes external Data Memory, 2048 bytes internal Data Memory (consisting of 256 bytes standard RAM and 1792 bytes AUX-RAM) and the 64 kbytes internal or 64 kbytes external Program Memory (see Fig.4).

The internal Data Memory is divided into three physically separated parts: 256 bytes of RAM, 1792 bytes of AUX-RAM, and a 128 bytes Special Function Registers (SFRs) area. These parts can be addressed each in a different way as described in Sections 8.2.1 to 8.2.2 and Table 3.

8.1Program Memory

The Program Memory of the P8xCE560 consists of

64 kbytes ROM or 64 kbytes EPROM. If, during reset, the EA pin was held HIGH, the P8xCE560 always executes out of the internal Program Memory. If the EA pin was held LOW during reset the P8xCE560 fetches all instructions from the external Program Memory. The EA input is latched during reset and is don’t care after reset.

The internal Program Memory content is protected by setting a mask programmable security bit (ROM) or by the software programmable security bits (EPROM) respectively, i.e. it cannot be read out at any time by any test mode or by any instruction in the external Program Memory space. The MOVC instructions are the only ones which have access to program code in the internal or external Program Memory. The EA input is latched during reset and is don’t care after reset. This implementation prevents from reading internal program code by switching from external Program Memory to internal Program Memory during MOVC instruction or an instruction that handles immediate data. Table 2 lists the access to the internal and external Program Memory with MOVC instructions whether the security feature has been activated or not.

Due to the maximum size of the internal Program Memory, the MOVC instructions can always operate either in the internal or in the external Program Memory.

Table 2 Memory access by the MOVC instruction

For code protection of the P87CE560 see Section 23.2.

MOVC	PROGRAM MEMORY ACCESS
INSTRUCTION	INTERNAL	EXTERNAL
MOVC in internal	YES	NO(1)
Program Memory
MOVC in external	NO(1)	YES
Program Memory
Note

1.Not applicable due to 64 kbytes internal Program Memory.

Table 3 Internal Data Memory map

MEMORY	LOCATION	ADDRESS MODE
RAM	0 to 127	Direct and indirect
	128 to 255	Indirect only
SFR	128 to 255	Direct only
AUX-RAM	0 to 1791	Indirect only with MOVX

8.2.1RAM

∙RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank.

∙RAM 128 to 255 can only be addressed indirectly. Address pointers are R0 and R1 of the selected register bank.

Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal 256 bytes RAM. The stack depth is only limited by the available internal RAM space of 256 bytes (see Fig.6). All registers except the Program Counter and the four register banks reside in the Special Function Register address space.

8.2.2SPECIAL FUNCTION REGISTERS

The Special Function Registers can only be addressed directly in the address range from 128 to 255 (see Fig.7).

8.2.3AUX-RAM

∙AUX-RAM 0 to 1791 is indirectly addressable via page register (XRAMP) and MOVX-Ri instructions, unless it is disabled by setting ARD = 1 (see Fig.5). When executing from internal Program Memory, an access to AUX-RAM 0 to 1791 will not affect the ports P0, P2, P3.6 and P3.7.

∙AUX-RAM 0 to 1791 is also indirectly addressable as external Data Memory locations 0 to 1791 via MOVX-Ri instructions, unless it is disabled by setting ARD = 1.

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An access to external Data Memory locations higher than 1791 will be performed with the MOVX @DPTR instructions in the same way as in the 80C51 structure, so with P0 and P2 as data/address bus and P3.6 and P3.7 as write and read timing signals.

Note that the external Data Memory cannot be accessed with R0 and R1 as address pointer if the AUX-RAM is enabled (ARD = 0, default).

8.2.4AUX-RAM PAGE REGISTER (XRAMP)

The AUX-RAM Page Register is used to select one of seven 256-bytes pages of the internal 1792 bytes AUX-RAM for MOVX-accesses via R0 or R1. Its reset value is ‘XXXX X000B’.

Table 4 AUX-RAM Page Register (address FAH)

7				6			5		4		3		2		1	0
XRAMPx				XRAMPx			XRAMPx		XRAMPx		XRAMPx		XRAMP2		XRAMP1	XRAMP0
Table 5 Description of XRAMP bits
BIT					SYMBOL							FUNCTION
7 to 3					XRAMPx				Reserved for future use. During read XRAMPx = undefined; a write
									operation must write logic 0s to these locations.
2 to 0				XRAMP2 to XRAMP0					AUX-RAM page select bits 2 to 0; see Table 6.
Table 6 Memory locations for all possible MOVX-accesses
X = don’t care.
ARD(1)		XRAMP2			XRAMP1		XRAMP0				MEMORY LOCATIONS
MOVX @Ri,A and MOVX A,@Ri instructions access
0		0			0		0		AUX-RAM locations 0 to 255 (reset condition)
0		0			0		1		AUX-RAM locations 256 to 511
0		0			1		0		AUX-RAM locations 512 to 767
0		0			1		1		AUX-RAM locations 768 to 1023
0		1			0		0		AUX-RAM locations 1024 to 1279
0		1			0		1		AUX-RAM locations 1280 to 1535
0		1			1		0		AUX-RAM locations 1536 to 1791
0		1			1		1		No valid memory access; reserved for future use
1			X		X		X		External RAM locations 0 to 255
MOVX @DPTR,A and MOVX A,@DPTR instructions access
0			X		X		X		AUX-RAM locations 0 to 1791 (reset condition);
									External RAM locations 1792 to 65535
1			X		X		X		External RAM locations 0 to 65535

Note

1. ARD: AUX-RAM disable, is a bit in SFR PCON (bit PCON.6); see Section 15.5.

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

andbook, full pag width	64 kbytes	64 kbytes
64 kbytes

OVERLAPPED SPACE

1791

255

INTERNAL

EXTERNAL

SPECIAL

AUXILIARY

FUNCTION

(ARD = 1)

INDIRECT ONLY

RAM

REGISTERS

(EA = 1)

(EA = 0)

127

DIRECT AND

(ARD = 0)

1792 bytes

INDIRECT

0

0

0

MAIN RAM

PROGRAM MEMORY

INTERNAL DATA

EXTERNAL DATA

MEMORY

MEMORY

MBH077

Fig.4 Memory map and address space.

			255		1791
				(XRAMP) = 06 H
		0			1536
			255	(XRAMP) = 05 H	1535
		0			1280
			255	(XRAMP) = 04 H	1279
	MOVX @Ri, A	0			1024
	MOVX A, @Ri		255		1023
				(XRAMP) = 03 H		MOVX @DPTR, A
						MOVX A, @DPTR
		0			768
			255	(XRAMP) = 02 H	767
		0			512
			255	(XRAMP) = 01 H	511
		0			256
			255	(XRAMP) = 00 H	255
		0			0
						MBH078

Fig.5 Indirect addressing AUX-RAM (1792 bytes); ARD = 0 (bit PCON.6).

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

8.3Addressing

The P8xCE560 has five methods for addressing:

∙Register

∙Direct

∙Register-Indirect

∙Immediate

∙Base-Register plus Index-Register-Indirect.

The first three methods can be used for addressing destination operands. Most instructions have a ‘destination/source’ field that specifies the data type, addressing methods and operands involved.

For operations other than MOVs, the destination operand is also a source operand.

Access to memory addresses is as follows:

∙Register in one of the four register banks through Register, Direct or Register-Indirect addressing.

∙Internal RAM (2048 bytes) through Direct or Register-Indirect addressing.

–Internal RAM: bytes 0 to 127; may be addressed directly/indirectly.

–Internal RAM: bytes 128 to 255; share their address location with the SFRs and so may only be addressed indirectly as data RAM.

–AUX-RAM: bytes 0 to 1791; can only be addressed indirectly via MOVX.

∙Special Function Registers through direct addressing at address locations 128 to 255 (see Fig.7).

∙External Data Memory through Register-Indirect addressing.

∙Program Memory look-up tables through Base-Register plus Index-Register-Indirect addressing.

BYTE		BIT ADDRESS		BYTE
ADDRESS				ADDRESS
(HEX)		(HEX)		(DECIMAL)
FFH	(MSB)		(LSB)	255

2FH
	7F	7E	7D	7C	7B	7A	79	78	47
2EH	77	76	75	74	73	72	71	70	46
2DH
	6F	6E	6D	6C	6B	6A	69	68	45
2CH	67	66	65	64	63	62	61	60	44
2BH
	5F	5E	5D	5C	5B	5A	59	58	43
2AH	57	56	55	54	53	52	51	50	42
29H
	4F	4E	4D	4C	4B	4A	49	48	41
28H
	47	46	45	44	43	42	41	40	40
27H	3F	3E	3D	3C	3B	3A	39	38	39
26H	37	36	35	34	33	32	31	30	38
25H	2F	2E	2D	2C	2B	2A	29	28	37
24H	27	26	25	24	23	22	21	20	36
23H
	1F	1E	1D	1C	1B	1A	19	18	35
22H	17	16	15	14	13	12	11	10	34
21H
	0F	0E	0D	0C	0B	0A	09	08	33
20H	07	06	05	04	03	02	01	00	32
1FH									31
				BANK 3
18H									24
17H									23
				BANK 2
10H									16
0FH									15
				BANK 1
08H									8
07H									7
				BANK 0
00H									0
							MBH079

Fig.6 Internal MAIN RAM bit addresses.

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

BYTE ADDRESS				BIT ADDRESS					REGISTER
(HEX)				(HEX)					(MNEMONIC)
FFH	(MSB)							(LSB)
	PT2	PCM2	PCM1	PCM0	PCT3	PCT2	PCT1	PCT0
									IP1
F8H	FF	FE	FD	FC	FB	FA	F9	F8
									B
F0H	F7	F6	F5	F4	F3	F2	F1	F0
	ET2	ECM2	ECM1	ECM0	ECT3	ECT2	ECT1	ECT0
F8H	EF	EE	ED	EC	EB	EA	E9	E8	IEN1
									ACC
E0H	E7	E6	E5	E4	E3	E2	E1	E0
	CR2	ENS1	STA	STO	SI	AA	CR1	CR0
D8H	DF	DE	DD	DC	DB	DA	D9	D8	S1CON
	CY	AC	F0	RS1	RS0	OV	F1	P
D0H	D7	D6	D5	D4	D3	D2	D1	D0	PSW
	T2OV	CMI2	CMI1	CMI0	CTI3	CTI2	CTI1	CTI0
C8H	CF	CE	CD	CC	CB	CA	C9	C8	TM2IR
									P4
C0H	C7	C6	C5	C4	C3	C2	C1	C0
	-	PAD	PS1	PS0	PT1	PX1	PT0	PX0
B8H	BF	BE	BD	BC	BB	BA	B9	B8	IP0
									P3
B0H	B7	B6	B5	B4	B3	B2	B1	B0
	EA	EAD	ES1	ES0	ET1	EX1	ET0	EX0
A8H	AF	AE	AD	AC	AB	AA	A9	A8	IEN0
									P2
A0H	A7	A6	A5	A4	A3	A2	A1	A0
	SM0	SM1	SM2	REN	TB8	RB8	TI	RI
98H	9F	9E	9D	9C	9B	9A	99	98	S0CON
									P1
90H	97	96	95	94	93	92	91	90
	TF1	TR1	TF0	TR0	IE1	IT1	IE0	IT0
88H	8F	8E	8D	8C	8B	8A	89	88	TCON
									P0
80H	87	86	85	84	83	82	81	80
								MBH456

Fig.7 Special Function Registers bit addresses.

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

9 I/O FACILITIES

The P8xCE560 has six 8-bit ports. Ports 0 to 3 are the same as in the 80C51, with the exception of the additional functions of Port 1. The parallel I/O function of Port 4 is equal to that of Ports 1, 2 and 3. All ports are bidirectional with the exception of Port 5 which is only a parallel input port.

Ports 0, 1, 2, 3, 4 and 5 perform the following alternative functions:

Port 0 Provides the multiplexed low-order address and data bus used for expanding the P8xCE560 with standard memories and peripherals.

Port 1 Is used for a number of special functions:

∙4 capture inputs (or external interrupt request inputs if capture information is not utilized)

∙external counter input

∙external counter reset input.

Port 2 Provides the high-order address bus when the P8xCE560 is expanded with external Data Memory and / or the P8xCE560 executes from external Program Memory.

Port 3 Pins can be configured individually to provide:

∙External interrupt request inputs

∙Counter inputs

∙Receiver input and transmitter output of serial port SIO 0 (UART)

∙Control signals to read and write external Data Memory.

Port 4 Can be configured to provide signals indicating a match between timer/counter T2 and its compare registers.

Port 5 May be used in conjunction with the ADC interface. Unused analog inputs can be used as digital inputs. As Port 5 lines may be used as inputs to the ADC, these digital inputs have an inherent hysteresis to prevent the input logic from drawing too much current from the power lines when driven by analog signals. Channel-to-channel crosstalk should be taken into consideration when both digital and analog signals are simultaneously input to Port 5 (see Chapter 21).

A pin of which the alternative function is not used may be used as normal bidirectional I/O. The generation or use of a Port 1, Port 3 or Port 4 pin as an alternative function is carried out automatically by the P8xCE560 provided the associated Special Function Register bit is set HIGH.

The SDA and SCL lines serve the serial port SI01 (I2C-bus). Because the I2C-bus may be active while the device is disconnected from VDD, these pins are provided with open-drain drivers.

Figure 8 shows the pull-up arrangements of Ports 1 to 4; Transistor ‘p1’ is turned on for 2 oscillator periods after Q makes a HIGH-to-LOW transition. During this time, ‘p1’ also turns on ‘p3’ through the inverter to form an additional pull-up.

	strong pull-up	VDD
	2 oscillator
	periods	p2
	p1	p3
		I/O PIN
Q
from port latch	n
		I1
input data
	INPUT	MLC926 - 1
read port pin	BUFFER

Fig.8 I/O buffers in the P8xCE560 (Port 1 to Port 4).

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

10 PULSE WIDTH MODULATED OUTPUTS

The P8xCE560 contains two Pulse Width Modulated (PWM) output channels (see Fig.9). These channels generate pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for the counter.

The prescaler and counter are common to both PWM channels. The 8-bit counter counts modulo 255, i.e., from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two registers: PWM0 and PWM1.

Provided the contents of either of these registers is greater than the counter value, the corresponding PWM0 or PWM1 output is set LOW. If the contents of these registers are equal to, or less than the counter value, the output will be HIGH. The pulse-width-ratio is therefore defined by the contents of the registers PWM0 and PWM1.

The pulse-width-ratio is in the range of 0¤255 to 255¤255 and may be programmed in increments of 1¤255.

Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be proportional to the contents of PWMn. The PWM outputs may also be configured as a dual DAC.

In this application, the PWM outputs must be integrated using conventional operational amplifier circuitry. If the resulting output voltages have to be accurate, external buffers with their own analog supply should be used to buffer the PWM outputs before they are integrated.

The repetition frequency fPWM, at the PWMn outputs is

	given by: fPWM	=	fCLK
			´ (PWMP + 1) ´ 255
		2

This gives a repetition frequency range of 123 Hz to

31.4 kHz (at fclk = 16 MHz). By loading the PWM registers with either 00H or FFH, the PWM channels will output a

constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the PWM registers when they are loaded with FFH.

When a compare register (PWM0 or PWM1) is loaded with a new value, the associated output is updated immediately. It does not have to wait until the end of the

current counter period. Both PWMn output pins are driven by push-pull drivers. These pins are not used for any other purpose.

handbook, full pagewidth
			PWM0
I				OUTPUT
N			8-BIT COMPARATOR		PWM0
				BUFFER
T
	fclk
E
R
N
A	1/2	PRESCALER	8-BIT COUNTER
L
B		PWMP
U
S				OUTPUT
			8-BIT COMPARATOR		PWM1
				BUFFER
			PWM1		MGA154

Fig.9 Functional diagram of Pulse Width Modulated outputs.

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

10.1Prescaler Frequency Control Register (PWMP)

Reading PWMP gives the current reload value. The actual count of the prescaler cannot be read.

Table 7 Prescaler Frequency Control Register (address FEH)

7	6	5	4	3			2	1	0
PWMP.7	PWMP.6	PWMP.5	PWMP.4	PWMP.3			PWMP.2	PWMP.1	PWMP.0
Table 8 Description of PWMP bits
BIT	SYMBOL					DESCRIPTION
7 to 0	PWMP.7 to PWMP.0		Prescaler division factor. The Prescaler division factor = (PWMP) + 1.
10.2 Pulse Width Register 0 (PWM0)
Table 9 Pulse width register (address FCH)
7	6	5	4	3			2	1	0
PWM0.7	PWM0.6	PWM0.5	PWM0.4	PWM0.3			PWM0.2	PWM0.1	PWM0.0
Table 10 Description of PWM0 bits
BIT	SYMBOL					DESCRIPTION
7 to 0	PWM0.7 to PWM0.0		Pulse width ratio.
							( PWM0)
			LOW/HIGH ratio of PWM0 signals = 255 –( PWM0)-----------------------------------------
10.3 Pulse Width Register 1 (PWM1)
Table 11 Pulse width register (address FDH)
7	6	5	4	3			2	1	0
PWM1.7	PWM1.6	PWM1.5	PWM1.4	PWM1.3			PWM1.2	PWM1.1	PWM1.0
Table 12 Description of PWM1 bits
BIT	SYMBOL					DESCRIPTION
7 to 0	PWM1.7 to PWM1.0		Pulse width ratio.
							( PWM1)
			LOW/HIGH ratio of PWM1 signals = 255 –( PWM1)-----------------------------------------

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

11 ANALOG-TO-DIGITAL CONVERTER (ADC)

11.1ADC features

·10-bit resolution

·8 multiplexed analog inputs

·Programmable autoscan of the analog inputs

·Bit oriented 8-bit scan-select register to select analog inputs

·Continuous scan or one time scan configurable from

1to 8 analog inputs

·Start of a conversion by software or with an external signal

·Eight 10-bit buffer registers, one register for each analog input channel

·Interrupt request after one channel scan loop

·Programmable prescaler (dividing by 2, 4, 6, 8) to adapt to different system clock frequencies

·Conversion time for one analog-to-digital conversion:

15to 50 ms

·Differential non-linearity (DLe): ±1 LSB

·Integral non-linearity (ILe): ±2 LSB

·Offset error (OSe): ±2 LSB

·Gain error (Ge): ±4%

·Absolute voltage error (Ae): 3 LSB

·Channel-to-channel matching (Mctc): ±1 LSB

·Crosstalk between analog inputs (Ct): < 60 dB at

100kHz

·Monotonic and no missing codes

·Separated analog (VDDA, VSSA) and digital (VDD, VSS) supply voltages

·Reference voltage at two special pins: Vref(n)(A) and

Vref(p)(A).

For information on the ADC characteristics, refer to Chapter 21.

11.2ADC functional description

The P8xCE560 has a 10-bit successive approximation ADC with 8 multiplexed analog input channels, comprising a high input impedance comparator, DAC (built with 1024 series resistors and analog switches), registers and

control logic. Input voltage range is from Vref(n)(A) (typical 0 V) to Vref(p)(A) (typical +5 V).

Each of the set of 8 buffer registers (10-bit wide) store the conversion results of the proper analog input channel.

Eleven Special Function Registers (SFRs) perform the user software interface to the ADC; see Table 14 for an overview of the ADC SFRs. In order to have a minimum of ADC service overhead in the microcontroller program, the ADC is able to operate autonomously within its user configurable autoscan function.

Figure 10 shows the functional diagram of the ADC.

11.3ADC timing

A programmable prescaler is controlled by the user selectable bits ADPR1 and ADPR0 in SFR ADCON to adapt the conversion time for different microcontroller clock frequencies.

Table 13 shows conversion times (tADC) for one analog-to-digital conversion at some convenient system clock frequencies (fclk) and ADC programmable prescaler divisors: m.

Conversion time tADC = (6 ´ m + 1) machine cycles.

A conversion time tADC consists of one sample time period (which equals two bit conversion times), 10 bit conversion time periods and one machine cycle to store the result.

After result storage an extra initializing time period follows to select the next analog input channel (according to the contents of SFR ADPSS), before the input signal is sampled.Thus the time period between two adjacent conversions within an autoscan loop is larger than the pure time tADC. This autoscan cycle time is (7 ´ m) machine cycles.

At the start of an autoscan conversion the time between writing to SFR ADCON and the first analog input signal sampling depends on the current prescaler value (m) and the relative time offset between this write operation and the internal (divided) ADC clock. This gives a variation range for the analog-to-digital conversion start time of (1¤2 ´ m) machine cycles.

Table 13 Conversion time configuration examples

	m		tADC (ms) at fCLK:
		6 MHz	8 MHz	12 MHz	16 MHz
	2	26.00	19.50	13.00(1)	9.75(1)
	4	50.00	37.50	25.00	18.75
	6	74.00(1)	55.50(1)	37.00	27.75
	8	98.00(1)	73.50(1)	49.00	36.75

Note

1.Prohibited tADC values; for tADC outside the limits of 15 ms £ tADC £ 50 ms, the specified ADC characteristics are not guaranteed.

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Philips Semiconductors				Product specification
8-bit microcontroller				P8xCE560

			COMPARATOR
ADC0	ANALOG
to				SAR
	MULTIPLEXER
ADC7
Vref(p)(A)				10
			DAC	10
Vref(n)(A)
VDDA1
VSSA1				10
ADEXS			8 x 10-BIT RESULT
	SCAN LOGIC			REGISTERS
			2	8
	ADPSS	ADCON	2 LATCHES
			Read ADRSH	Read ADRSLn
	8	8	2	8
			INTERNAL BUS

MBH080

Fig.10 Functional diagram of ADC.

11.4ADC configuration and operation

Every analog-to-digital conversion is an autoscan conversion. The two user selectable general operation modes are continuous scan and one-time scan mode.

The desired analog input port channel(s) for conversion is(are) selected by programming analog-to-digital input port scan-select bits in SFR ADPSS. An analog input channel is included in the autoscan loop if the corresponding bit in SFR ADPSS is logic 1, a channel is skipped if the corresponding bit in SFR ADPSS is logic 0.

An autoscan is always started according to the lowest bit position of SFR ADPSS that contains a logic 1.

An autoscan conversion is started by setting the flag ADSST in register ADCON either by software or by an external start signal at input pin ADEXS, if enabled.

Either no edge (external start totally disabled), a rising edge or/and a falling edge of ADEXS is selectable for external conversion start by the bits ADSRE and ADSFE in register ADCON.

After completion of an analog-to-digital conversion the 10-bit result is stored in the corresponding 10-bit buffer register. Then the next analog input is selected according to the next higher set bit position in ADPSS, converted and stored, and so on.

When the result of the last conversion of this autoscan loop is stored, the ADC interrupt flag ADINT (SFR ADCON), is set. It is not cleared by interrupt hardware - it must be cleared by software.

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

In continuous scan mode (ADCSA = 1; ADCON.2) the ADC start and status flag ADSST (ADCON.3) retains the set state and the autoscan loop restarts from the beginning. In one-time scan mode (ADCSA = 0) conversions stop after the last selected analog input was converted, ADINT (ADCON.4) is set and ADSST is cleared automatically.

ADSST cannot be set (neither externally nor by software) as long as ADINT = 1, i.e. as long as ADINT is set, a new conversion start - by setting flag ADSST - is inhibited; actually it is only delayed until ADINT is cleared. If a logic 1 is written to ADSST while ADINT = 1, this new value is internally latched and preserved, not setting ADSST until ADINT = 0. In this state, a read of SFR ADCON will display ADSST = 0, because always the effective ADC status is read.

Note that under software control the analog inputs can also be converted in arbitrary order, when one-time scan mode is selected and in SFR ADPSS only one bit is set at a time. In this case ADINT is set and ADSST is cleared after every conversion.

11.5ADC during Idle and Power-down mode

The analog-to-digital converter is active only when the microcontroller is in normal operating mode. If the Idle or Power-down mode is activated, then the ADC is switched off and put into a power saving idle state - a conversion in progress is aborted, a previously set ADSST flag is cleared and the internal clock is halted. The conversion result registers are not affected.

The interrupt flag ADINT will not be set by activation of Idle or Power-down mode. A previously set flag ADINT will not be cleared by the hardware. (Note: ADINT cannot be cleared by hardware at all, except for a reset - it must be cleared by the user software.)

After a wake-up from Idle or Power-down mode a set flag ADINT indicates that at least one autoscan loop was finished completely before the microcontroller was put into the respective power reduction mode and it indicates that the stored result data may be fetched now - if desired.

For further information on Idle and Power-down modes, refer to Chapter 15.

11.6ADC resolution and characteristics

The ADC system has its own analog supply pins VDDA1 and VSSA1. It is referenced by two special reference voltage input pins sourcing the resistance ladder of the

DAC: Vref(p)(A) and Vref(n)(A). The voltage between Vref(p)(A) and Vref(n)(A) defines the full-scale range. Due to the 10-bit resolution the full scale range is divided into 1024 unit

steps.

The unit step voltage is 1 LSB, which is typically 5 mV

(Vref(p)(A) = 5.12 V, Vref(n)(A) = 0 V = VSSA1).

The DAC's resistance ladder has 1023 equally spaced taps, separated by a unit resistance ‘R’.

The first tap is located 0.5 ´ R above Vref(n)(A), the last tap is located 1.5 ´ R below Vref(p)(A). This results in a total ladder resistance of 1024 ´ R. This structure ensures that

the DAC is monotonic and results in a symmetrical quantization error. For input voltages between:

·Vref(n)(A) and [Vref(n)(A) + 1¤2 ´ LSB] the 10-bit conversion result code will be 0000000000B (= 000H or 0D)

·[Vref(p)(A) - 3¤2 ´ LSB] and Vref(p)(A) the 10-bit conversion result code will be 1111111111B (= 3FFH or 1023D).

The result code corresponding to an analog input voltage (Vin(A)) can be calculated from the formula:

´ Vin(A) –Vref(n)(A)

Result code = 1024 -----------------------------------------------

Vref(p)(A) –Vref(n)(A)

The analog input voltage should be stable when it is sampled for conversion. At any times the input voltage slew rate must be less than 10 V/ms (5 V conversion range) in order to prevent an undefined result.

This maximum input voltage slew rate can be ensured by an RC low pass filter with R = 2.2 kW and C = 100 nF. The capacitor between analog input pin and analog ground pin shall be placed close to the pins in order to have maximum effect in minimizing input noise coupling.

11.7ADC after reset

After a reset of the microcontroller the ADCON and ADPSS registers are initialized to zero. Registers ADRSLn and ADRSH are not initialized by a reset.

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11.8ADC Special Function Registers

Table 14 ADC Special Function Registers overview

The SFRs are not bit addressable. For more information on Special Function Registers refer to Section 8.2.

	ADDRESS	NAME	R/W	RESET	DESCRIPTION
				VALUE
	86H	ADRSL0	R	−	ADC Result Registers Low Byte: ADRSL0 to ADRSL7; The read value
					after reset is indeterminate. Their data are not affected by chip reset.
	96H	ADRSL1
	A6H	ADRSL2
	B6H	ADRSL3
	C6H	ADRSL4
	D6H	ADRSL5
	E6H	ADRSL6
	F6H	ADRSL7
	F7H	ADRSH	R	00H	ADC Result Register High Bits: one common result SFR for the upper
					2 result bits.
	E7H	ADPSS	R/W	00H	ADC Input Port Scan-Select Register. Contains control bits to select the
					analog input channel(s) to be scanned for analog-to-digital conversion.
	D7H	ADCON	R/W	00H	ADC Control Register. Contains control and status bits for the
					analog-to-digital converter peripheral block.
	C7H	P5	R	−	Digital Input Port Register; shared with analog inputs. P5 is not affected by
					chip reset.

11.8.1ADC RESULT REGISTERS

The binary result code of the analog-to-digital conversions is accessed by the ADC Result Registers:

∙ADRSLn (ADRSL0 to ADRSL7); eight input channel related conversion result SFRs for the 8 result lower bytes. Each of ADRSLn is associated with the indexed analog input channel ADCn (ADC0/P5.0 to ADC7/P5.7).

∙ADRSH for the ADC; one general SFR for the 2 result upper bits (bit 9 and 8).

During read (by software) of the ADRSLn register, simultaneously the two highest bits of the 10-bit conversion result are copied into the two latches, ADRSH.0 and ADRSH.1 (SFR ADRSH) preserving them until the next read of any ADRSLn register. Thus to ensure that the 10-bit result of the same single analog-to-digital conversion is captured, first read the ADRSLn register and then the ADRSH register.

Table 15	ADC Result Register Low Byte; ADRSLn; n = 0 to 7 (address see 86H to F6H)
7		6	5	4	3		2		1	0
ADRSn.7		ADRSn.6	ADRSn.5	ADRSn.4	ADRSn.3		ADRSn.2		ADRSn.1	ADRSn.0
Table 16	Description of ADRSLn bits
BIT		SYMBOL				DESCRIPTION
7 to 0		ADRSn.7 to ADRSn.0		ADC result lower byte.

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Philips Semiconductors										Product specification
8-bit microcontroller										P8xCE560
Table 17 ADC Result Register High Bits; ADRSH (address F7H)
7	6		5	4		3		2		1	0
0	0		0	0		0		0		ADRSn.9	ADRSn.8
Table 18 Description of ADRSH bits
BIT	SYMBOL						DESCRIPTION
7 to 2	−			The upper 6 bits ADRSH.2 to ADRSH.7 are always read as a logic 0.
1 to 0	ADRSn.9 to ADRSn.8			ADC result upper 2 bits.

11.8.2ADC INPUT PORT SCAN-SELECT REGISTER (ADPSS)

Table 19 ADC Input Port Scan-Select Register (address E7H)

7	6		5	4	3	2	1	0
ADPSS7	ADPSS6		ADPSS5	ADPSS4	ADPSS3	ADPSS2	ADPSS1	ADPSS0
Table 20 Description of ADPSS bits
BIT	SYMBOL				DESCRIPTION
7 to 0	ADPSS7	Control bits to select the analog input channel(s) to be scanned for
	to	analog-to-digital conversion. If all bits ADPSS0 to ADPSS7 = 0, then no conversion can
	ADPSS0	be started. If ADPSS is written while an analog-to-digital conversion is in progress
		(ADSST = 1; ADCON.3) then the autoscan loop with the previous selected analog
		inputs is completed first. The next autoscan loop is performed with the new selected
		analog inputs. For each individual bit position ADPSSn (n = 0 to 7):
		∙	If ADPSSn = 0, then the corresponding analog input is skipped in the autoscan loop
		∙	If ADPSSn = 1, then the corresponding analog input is included in the autoscan loop.

11.8.3ADC CONTROL REGISTER (ADCON)

Table 21 ADC Control Register (address D7H)

7	6	5	4	3	2	1		0
ADPR1	ADPR0	ADPOS	ADINT	ADSST	ADCSA	ADSRE		ADSFE
Table 22 Description of ADCON bits
BIT	SYMBOL			DESCRIPTION
7	ADPR1	These two bits determine the value of the prescaler divisor (m); see Table 23.
6	ADPR0
5	ADPOS	ADPOS is reserved for future use. Must be a logic 0 if ADCON is written.
4	ADINT	ADC interrupt. This flag is set when all selected analog inputs are converted (both in
		continuous scan and in one-time scan mode). An interrupt is invoked if this interrupt flag
		is enabled. ADINT must be cleared by software. It cannot be set by software.

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Philips Semiconductors				Product specification
8-bit microcontroller				P8xCE560
BIT		SYMBOL		DESCRIPTION
3		ADSST	ADC start and status. Setting this bit by software or by hardware (via ADEXS input)
			starts the analog-to-digital conversion of the selected analog inputs. ADSST stays a
			logic 1 in continuous scan mode. In one-time scan mode, ADSST is cleared by
			hardware when the last selected analog input channel has been converted. As long as
			ADSST = 1, new start commands to the ADC-block are ignored. An analog-to-digital
			conversion in progress is aborted if ADSST is cleared by software.
2		ADCSA	ADCSA =1 results in a continuous scan of the selected analog inputs after a start of an
			analog-to-digital conversion. ADCSA = 0 results in an one-time scan of the selected
			analog inputs after a start of an analog-to-digital conversion.
1		ADSRE	If ADSRE = 1, then a rising edge at input ADEXS will start the analog-to-digital
			conversion and generate a capture signal. If ADSRE = 0, then a rising edge at input
			ADEXS has no effect.
0		ADSFE	If ADSFE = 1, then a falling edge at input ADEXS will start the analog-to-digital
			conversion and generate a capture signal. If ADSFE = 0, then a falling edge at input
			ADEXS has no effect.
Table 23	Prescaler selection
	ADPR1		ADPR0	PRESCALER DIVISOR (m)
	0		0	2 (default by reset)
	0		1	4
	1		0	6
	1		1	8

11.8.4DIGITAL INPUT PORT REGISTER (P5)

Digital Input Port Register (P5) is shared with analog inputs. P5 is not affected by chip reset. SFR P5 always represents the binary value of the logic level at input pins P5.0/ADC0 to P5.7/ADC7. Reading P5 does not affect analog-to-digital conversions. But it is recommended to use the digital input port function of the hardware Port 5 only as an alternative to analog input voltage conversions. Simultaneous mixed operation is discouraged to guarantee a reliable and accurate ADC result. For more information on P5 refer to Chapter 9.

Table 24	Digital Input Port Register (address C7H)
7		6		5	4	3		2		1	0
P5.7		P5.6		P5.5	P5.4	P5.3		P5.2		P5.1	P5.0
Table 25	Description of P5 bits
BIT		SYMBOL					DESCRIPTION
7 to 0		P5.7 to P5.0			Binary value of the logic level at input pins P5.0/ADC0 to P5.7/ADC.7.

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Philips Semiconductors	Product specification
8-bit microcontroller	P8xCE560

12 TIMERS/COUNTERS

The P8xCE560 contains,

·Three 16-bit timer/event counters: Timer 0, Timer 1 and Timer T2

·One 8-bit timer, T3.

12.1Timer 0 and Timer 1

Timer 0 and Timer 1 may be programmed to carry out the following functions:

·Measure time intervals and pulse durations

·Count events

·Generate interrupt requests.

Timers 0 and 1 each have a control bit in SFR TMOD that selects the timer or counter function of the corresponding timer.

In the timer function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of

12 oscillator periods, the count rate is 1¤12 ´ the oscillator frequency.

In the counter function, the register is incremented in response to a HIGH-to-LOW transition at the corresponding external input pin, T0 or T1. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a HIGH in one cycle and a LOW in the next cycle, the counter is incremented. Thus, it takes two machine cycles

(24 oscillator periods) to recognize a HIGH-to-LOW transition. There are no restrictions on the duty cycle of the external input signal. To ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.

Timer 0 and Timer 1 can be programmed independently to operate in one of four modes:

Mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler.

Mode 1 16-bit time-interval or event counter.

Mode 2 8-bit time-interval or event counter with automatic reload upon overflow.

Mode 3 Timer 0: one 8-bit time-interval or event counter and one 8-bit time-interval counter.

Timer 1: stopped.

When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt request flag or generate an interrupt. However, the overflow from Timer 1 can be used to pulse the serial port baud rate generator. With a 16 MHz crystal, the counting frequency of these timers/counters is as follows:

·In the timer function, the timer is incremented at a frequency of 1.33 MHz (1¤12 ´ the system clock frequency)

·When programmed for external inputs: 0 to 660 kHz (1¤24 ´ the system clock frequency).

Both internal and external inputs can be gated to the counter by a second external source for directly measuring pulse durations. When configured as a counter, the register is incremented on every falling edge on the corresponding input pin T0 or T1. The earliest moment, the incremented register value can be read is during the second machine cycle following the machine cycle within which the incrementing pulse occurred.

The counters are started and stopped under software control. Each one sets its interrupt request flag when it overflows from all HIGHs to all LOWs (or automatic reload value), with the exception of Mode 3 as previously described.

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Philips Semiconductors								Product specification
8-bit microcontroller									P8xCE560
12.1.1 TIMER/COUNTER MODE CONTROL REGISTER (TMOD)
Table 26 Timer/Counter Mode Control Register (address 89H)
7	6		5	4		3	2	1		0
GATE	C/T		M1	M0		GATE	C/T	M1		M0

Table 27 Description of TMOD bits for Timer 1 and Timer 0

Timer 0: bit TMOD.0 to TMOD.3; Timer 1: bit TMOD.4 to TMOD.7; n = 0, 1.

BIT	SYMBOL	DESCRIPTION
7 and 3	GATE	Gating control. When set Timer/counter ‘n’ is enabled only while		pin is HIGH and
			INTn
		control bit TRn (TR1 or TR0) is set. When cleared Timer ‘n’ is enabled whenever TRn
		control bit is set.
6 and 2	C/T	Timer or Counter Selector. Cleared for Timer operation; input from internal system
		clock. Set for Counter operation; input from pin Tn (T1 or T0).
5 and 1	M1	Timer 0, Timer 1 mode select; see Table 28.
4 and 0	M0
Table 28 Timer 0, Timer 1 mode select
M1	M0	OPERATING
0	0	Timer TL0/TL1 serves as 5-bit prescaler.
0	1	16-bit Timer/Counter TH0/TH1 and TL0/TL1 are cascaded; there is no prescaler.
1	0	8-bit auto-reload Timer/Counter TH0/TH1 holds a value which is to be reloaded into
		TL0/TL1 each time it overflows.
1	1	Timer 0: TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.
		TH0 is an 8-bit timer only controlled by Timer 1 control bits.
1	1	Timer 1: Timer/Counter 1 stopped.

12.1.2TIMER/COUNTER CONTROL REGISTER (TCON)

Table 29 Timer/Counter Control Register (address 88H)

7	6	5		4	3		2	1	0
TF1	TR1		TF0	TR0	IE1		IT1	IE0	IT0
Table 30 Description of TCON bits
BIT	SYMBOL				DESCRIPTION
7 and 5	TF1 and TF0		Timer 1 and Timer 0 overflow flag . Set by hardware on Timer/Counter overflow.
			Cleared by hardware when processor vectors to interrupt routine.
6 and 4	TR1 and TR0		Timer 1 and Timer 0 run control bit. Set/cleared by software to turn Timer/Counter
			on/off.
3 and 1	IE1 and IE0		Interrupt 1 and Interrupt 0 edge flag . Set by hardware when external interrupt edge
			detected. Cleared when interrupt processed.
2 and 0	IT1 and IT0		Interrupt 1 and Interrupt 0 type control bit. Set/cleared by software to specify falling
			edge/low level triggered external interrupts.

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