Philips PCF8578H-F1, PCF8578T, PCF8578U, PCF8578U-10, PCF8578U-12 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

PCF8578

LCD row/column driver for dot matrix graphic displays

Product specification

1998 Sep 08

Supersedes data of 1997 Mar 28

File under Integrated Circuits, IC12

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

CONTENTS

1FEATURES

2APPLICATIONS

3GENERAL DESCRIPTION

4ORDERING INFORMATION

5BLOCK DIAGRAM

6PINNING

7FUNCTIONAL DESCRIPTION

7.1Mixed mode

7.2Row mode

7.3Multiplexed LCD bias generation

7.4Power-on reset

7.5Internal clock

7.6External clock

7.7Timing generator

7.8Row/column drivers

7.9Display mode controller

7.10Display RAM

7.11Data pointer

7.12Subaddress counter

7.13I2C-bus controller

7.14Input filters

7.15RAM access

7.16Display control

7.17TEST pin

18 SOLDERING

18.1Introduction

18.2Reflow soldering

18.3Wave soldering

18.3.1LQFP

18.3.2VSO

18.3.3Method (LQFP and VSO)

18.4Repairing soldered joints

19DEFINITIONS

20LIFE SUPPORT APPLICATIONS

21PURCHASE OF PHILIPS I2C COMPONENTS

8	I2C-BUS PROTOCOL

8.1Command decoder

9	CHARACTERISTICS OF THE I2C-BUS

9.1Bit transfer

9.2Start and stop conditions

9.3System configuration

9.4Acknowledge

10LIMITING VALUES

11HANDLING

12DC CHARACTERISTICS

13AC CHARACTERISTICS

14APPLICATION INFORMATION

15CHIP DIMENSIONS AND BONDING PAD LOCATIONS

16CHIP-ON GLASS INFORMATION

17PACKAGE OUTLINE

1998 Sep 08

2

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

1 FEATURES

·Single chip LCD controller/driver

·Stand-alone or may be used with up to 32 PCF8579s (40960 dots possible)

·40 driver outputs, configurable as 32¤8, 24¤16, 16¤24 or 8¤32 rows/columns

·Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32

·Externally selectable bias configuration, 5 or 6 levels

·1280-bit RAM for display data storage and scratch pad

·Display memory bank switching

·Auto-incremented data loading across hardware subaddress boundaries (with PCF8579)

·Provides display synchronization for PCF8579

·On-chip oscillator, requires only 1 external resistor

·Power-on reset blanks display

·Logic voltage supply range 2.5 to 6 V

·Maximum LCD supply voltage 9 V

·Low power consumption

·I2C-bus interface

·TTL/CMOS compatible

·Compatible with most microcontrollers

·Optimized pinning for single plane wiring in multiple device applications (with PCF8579)

·Space saving 56-lead plastic mini-pack and 64 pin quad flat pack

·Compatible with chip-on-glass technology.

2 APPLICATIONS

·Automotive information systems

·Telecommunication systems

·Point-of-sale terminals

·Computer terminals

·Instrumentation.

3 GENERAL DESCRIPTION

The PCF8578 is a low power CMOS LCD row/column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device has 40 outputs, of which 24 are programmable,

configurable as 32¤8, 24¤16, 16¤24 or 8¤32 rows/columns. The PCF8578 can function as a stand-alone LCD

controller/driver for use in small systems, or for larger systems can be used in conjunction with up to

32 PCF8579s for which it has been optimized. Together these two devices form a general purpose LCD dot matrix driver chip set, capable of driving displays of up to 40960 dots. The PCF8578 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). Communication overheads are minimized by a display RAM with auto-incremented addressing and display bank switching.

4 ORDERING INFORMATION

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	PCF8578T	VSO56	plastic very small outline package; 56 leads	SOT190-1
	PCF8578U/2	-	chip with bumps in tray	-
	PCF8578H	LQFP64	plastic low profile quad flat package; 64 leads; body 10 ´ 10 ´ 1.4 mm	SOT314-2

1998 Sep 08

3

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

5 BLOCK DIAGRAM

						C39 - C32
						R31/C31 - R8/C8
						R7 - R0
						17 - 56
						(29 to 35, 37, 38 to 46
VDD	9 (20)					48 to 62, 63, 64, 1 to 6)
V2	10 (21)
	11 (22)
V3						(1)
	12 (23)					ROW/COLUMN	PCF8578
V4						DRIVERS
	13 (24)
V5
	14 (25)
VLCD
	6 (12)
TEST
				DISPLAY
						OUTPUT
				MODE
						CONTROLLER
				CONTROLLER
				Y DECODER		32 x 40-BIT	DISPLAY
				AND SENSING
						DISPLAY RAM	DECODER
				AMPLIFIERS
						X DECODER
								(9) 3		SYNC
	POWER-ON		SUBADDRESS				TIMING
					RAM DATA POINTER			(10) 4
	RESET		COUNTER				GENERATOR			CLK
					Y	X
SCL	2 (8)			I2C-BUS				(16) 8		OSC
		INPUT				COMMAND
	1 (7)						OSCILLATOR
		FILTERS		CONTROLLER		DECODER			R
SDA										OSC
		(14, 15, 17 to 19						(11) 5		VSS
	15, 16			7 (13)
		26 to 28	36, 47)
	n.c.	n.c.						MSA842
				SA0

(1) Operates at LCD voltage levels, all other blocks operate at logic levels. The pin numbers given in parenthesis refer to the LQFP64 package.

Fig.1 Block diagram.

1998 Sep 08

4

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

6 PINNING

	SYMBOL			PIN		DESCRIPTION
			VSO56		LQFP64
SDA			1		7	I2C-bus serial data input/output
	SCL		2		8	I2C-bus serial clock input
			3		9	cascade synchronization output
	SYNC
	CLK		4		10	external clock input/output
	VSS		5		11	ground (logic)
	TEST		6		12	test pin (connect to VSS)
	SA0		7		13	I2C-bus slave address input (bit 0)
	OSC		8		16	oscillator input
	VDD		9		20	positive supply voltage
	V2 to V5		10 to 13		21 to 24	LCD bias voltage inputs
	VLCD		14		25	LCD supply voltage
	n.c.		15, 16		14, 15, 17 to 19,	not connected
					26 to 28, 36, 47
	C39 to C32		17 to 24		29 to 35, 37	LCD column driver outputs
	R31/C31 to R8/C8		25 to 48		38 to 46, 48 to 62	LCD row/column driver outputs
	R7 to R0		49 to 56		63, 64, 1 to 6	LCD row driver outputs

1998 Sep 08

5

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

	SDA					R0
			1		56
			2
	SCL				55	R1
SYNC			3		54	R2
	CLK					R3
			4		53
	VSS					R4
			5		52
	TEST					R5
			6		51
	SA0
			7		50	R6
	OSC
			8		49	R7
	V DD					R8/C8
			9		48
	V 2
			10		47	R9/C9
	V 3
			11		46	R10/C10
	V 4		12
					45	R11/C11
	V 5		13		44	R12/C12
V LCD			14	PCF8578	43	R13/C13
	n.c.		15		42	R14/C14
	n.c.
			16		41	R15/C15
					40
	C39		17			R16/C16
	C38				39
			18			R17/C17
	C37		19		38	R18/C18
	C36		20		37	R19/C19
	C35		21		36	R20/C20
	C34		22		35	R21/C21
	C33
			23		34	R22/C22
	C32		24		33	R23/C23
R31/C31
			25		32	R24/C24
R30/C30			26		31	R25/C25
R29/C29
			27		30	R26/C26
R28/C28
			28		29	R27/C27
				MSA839

Fig.2 Pin configuration (VSO56).

1998 Sep 08

6

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

R6		R7		R8/C8		R9/C9		R10/C10		R11/C11		R12/C12		R13/C13		R14/C14		R15/C15		R16/C16		R17/C17		R18/C18		R19/C19		R20/C20		R21/C21
64		63		62		61		60		59		58		57		56		55		54		53		52		51		50		49

R5 1

R4 2

R3 3

R2 4

R1 5

R0 6

SDA 7

SCL 8

PCF8578

SYNC 9

CLK 10

VSS 11

TEST 12

SA0 13

n.c. 14

n.c. 15

OSC 16

17		18		19		20		21		22		23		24		25		26		27		28		29		30		31		32
n.c.		n.c.		n.c.		DD	2		3		4		5			LCD		n.c.		n.c.		n.c.		C39		C38		C37		C36
						V		V		V		V		V		V

48 R22/C22

47 n.c.

46 R23/C23

45 R24/C24

44 R25/C25

43 R26/C26

42 R27/C27

41 R28/C28

40 R29/C29

39 R30/C30

38 R31/C31

37 C32

36 n.c.

35 C33

34 C34

33 C35

MBH588

Fig.3 Pin configuration (LQFP64).

1998 Sep 08

7

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

7 FUNCTIONAL DESCRIPTION

The PCF8578 row/column driver is designed for use in one of three ways:

∙Stand-alone row/column driver for small displays (mixed mode)

∙Row/column driver with cascaded PCF8579s (mixed mode)

∙Row driver with cascaded PCF8579s (mixed mode).

7.1Mixed mode

In mixed mode, the device functions as both a row and column driver. It can be used in small stand-alone applications, or for larger displays with up to 15 PCF8579s (31 PCF8579s when two slave addresses are used). See Table 1 for common display configurations.

7.2Row mode

In row mode, the device functions as a row driver with up to 32 row outputs and provides the clock and synchronization signals for the PCF8579. Up to 16 PCF8579s can normally be cascaded (32 when two slave addresses are used).

Timing signals are derived from the on-chip oscillator, whose frequency is determined by the value of the resistor connected between OSC and VSS.

Commands sent on the I2C-bus from the host microcontroller set the mode (row or mixed), configuration (multiplex rate and number of rows and columns) and control the operation of the device. The device may have one of two slave addresses. The only difference between these slave addresses is the least significant bit, which is set by the logic level applied to SA0. The PCF8578 and PCF8579 also have subaddresses. The subaddress of the PCF8578 is only defined in mixed mode and is fixed at 0. The RAM may only be accessed in mixed mode and data is loaded as described for the PCF8579.

Bias levels may be generated by an external potential divider with appropriate decoupling capacitors. For large displays, bias sources with high drive capability should be used. A typical mixed mode system operating with up to 15 PCF8579s is shown in Fig.5 (a stand-alone system would be identical but without the PCF8579s).

Table 1 Possible displays configurations

	APPLICATION	MULTIPLEX	MIXED MODE		ROW MODE		TYPICAL APPLICATIONS
		RATE	ROWS	COLUMNS	ROWS	COLUMNS
	Stand alone	1 : 8	8	32	−	−	small digital or
							alphanumerical displays
		1 : 16	16	24	−	−
		1 : 24	24	16	−	−
		1 : 32	32	8	−	−
	With PCF8579	1 : 8	8(1)	632(1)	8 × 4 4(2)	640(2)	alphanumeric displays and
							dot matrix graphic displays
		1 : 16	16(1)	624(1)	16 × 2(2)	640(2)
		1 : 24	24(1)	616(1)	24(2)	640(2)
		1 : 32	32(1)	608(1)	24(2)	640(2)

Notes

1.Using 15 PCF8579s.

2.Using 16 PCF8579s.

1998 Sep 08

8

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

7.3Multiplexed LCD bias generation

The bias levels required to produce maximum contrast depend on the multiplex rate and the LCD threshold voltage (Vth). Vth is typically defined as the RMS voltage at which the LCD exhibits 10% contrast. Table 2 shows the optimum voltage bias levels for the PCF8578 as functions of Vop (Vop = VDD − VLCD), together with the discrimination ratios (D) for the different multiplex rates. A practical value

for Vop is obtained by equating Voff(rms) with Vth. Figure 4 shows the first 4 rows of Table 2 as graphs. Table 3 shows

the relative values of the resistors required in the configuration of Fig.5 to produce the standard multiplex rates.

Table 2 Optimum LCD voltages

	PARAMETER		MULTIPLEX RATE
		1 : 8	1 : 16	1 : 24	1 : 32
	V2	0.739	0.800	0.830	0.850
	---------
	Vop
	V3	0.522	0.600	0.661	0.700
	---------
	Vop
	V4	0.478	0.400	0.339	0.300
	---------
	Vop
	V5	0.261	0.200	0.170	0.150
	---------
	Vop
	Voff ( rms)	0.297	0.245	0.214	0.193
	-----------------------
	Vop
	Von ( rms)	0.430	0.316	0.263	0.230
	----------------------
	Vop
	Von ( rms)	1.447	1.291	1.230	1.196
	D = -----------------------
	Voff ( rms)
	Vop	3.370	4.080	4.680	5.190
	---------
	Vth

Table 3 Multiplex rates and resistor values for Fig.5

	RESISTORS	MULTIPLEX RATE (n)
		n = 8	n = 16, 24, 32
	R1	R	R
	R2	( n –2) R	R
	R3	( 3 – n) R	( n –3) R

7.4Power-on reset

At power-on the PCF8578 resets to a defined starting condition as follows:

1.Display blank

2.1 : 32 multiplex rate, row mode

3.Start bank, 0 selected

4.Data pointer is set to X, Y address 0, 0

5.Character mode

6.Subaddress counter is set to 0

7.I2C-bus interface is initialized.

Data transfers on the I2C-bus should be avoided for 1 ms following power-on, to allow completion of the reset action.

MSA838

V bias

1.0

Vop

V2

0.8

V3

0.6

0.4

V4

0.2

V5

0

1:8

1:16

1:24

1:32

multiplex rate

Vbias = V2, V3, V4, V5. See Table 2.

Fig.4

Vbias/Vop as a function of the multiplex rate.

1998 Sep 08

9

_
08 Sep 1998
							LCD DISPLAY
				n	40	n
				rows	columns
VDD			VDD
	R1							40
								columns
	C
			V2
	R2
	C
			V3			VDD	VDD		A0
HOST	R3
MICROCONTROLLER						VLCD	VLCD		A1
	C									subaddress 1
10			V4	PCF8578		VSS	VSS	PCF8579	A2	VSS / VDD
SCL
	R2					VSS / VDD
							SA0		A3
SDA	C							CLK SYNC V4 V3
							SDA SCL
			V5
	R1
	C
			VLCD
			VSS		SA0	VSS / VDD
VSS	VLCD	R	OSC
			OSC SDA	SCL	CLK SYNC

MSA843

Fig.5 Typical mixed mode configuration.

matrix dot for driver row/column LCD displays graphic

PCF8578

Semiconductors Philips

specification Product

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

T frame

0

1

2

3

4

5

6

7

VDD

V 2

V3

ROW 0 V4

V5

VLCD

VDD

V 2

V3

COLUMN V4

V5

VLCD

SYNC

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

VDD

V 2

V3

ROW 0 V4

V5

VLCD

VDD

V 2

V3

COLUMN V4

V5

VLCD

SYNC

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

VDD

V 2

V3

ROW 0 V4

V5

VLCD

VDD

V 2

V3

COLUMN V4

V5

VLCD

SYNC

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

VDD

V 2

V3 ROW 0 V4 V5

VLCD

VDD

V 2

V3

COLUMN V4

V5

VLCD

SYNC

MSA841

ON

OFF

1:8

1:16

1:24

1:32

column display

Fig.6 LCD row/column waveforms.

1998 Sep 08

11

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

ROW 1

R1 (t)

ROW 2

R2 (t)

COL 1

C1 (t)

COL 2

C2 (t)

V state 1 (t)

V state 2 (t)

T frame

VDD

V2

V3 V4 V5

VLCD

VDD

V2

V3

V4

V5

VLCD

VDD

V2

V3

V4

V5

VLCD

VDD

V2

V3

V4

V5

VLCD

Vop

0.261 Vop

0 V

0.261 Vop

Vop

Vop

0.478 Vop

0.261 Vop

0 V

0.261 Vop

0.478 Vop

Vop

Vstate 1	(t) = C1(t)						R1(t):
Von(rms)	=	1				8				1				= 0.430
Vop		8				8 (		8					1)
Vstate 2	(t) = C2(t)						R2(t):

	Voff(rms)	=	2 ( 8	1)				= 0.297
			8 (				1) 2
	Vop			8

state 1 (OFF)

state 2 (ON)

dot matrix

1:8 multiplex rate

MSA840

general relationship (n = multiplex rate)

	Von(rms) =		1		n	1
	Vop		n	n (	n	1)
	Voff(rms)	=	2 (	n	1)
	Vop		n (		n	1) 2

Fig.7 LCD drive mode waveforms for 1 : 8 multiplex rate.

1998 Sep 08

12

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

ROW 1

R1 (t)

ROW 2

R2 (t)

COL 1

C1 (t)

COL 2

C2 (t)

V state 1 (t)

V state 2 (t)

T frame

state 1 (OFF)

VDD

state 2 (ON)

V2

V3

V4

V5

VLCD

VDD

V2

V3

V4

V5

VLCD

VDD

V2

V3

V4

V5

dot matrix

VLCD

1:16 multiplex rate

VDD

V2

V3

V4

V5

VLCD

Vop

0.2 Vop

0 V

0.2 Vop

Vop

Vop

0.6 Vop

0.2 Vop

0 V

0.2 Vop

0.6 Vop

Vop

																																											MSA836
Vstate 1 (t) = C1(t)							R1(t):															general relationship (n = multiplex rate)
Von(rms)			=	1				16						1						= 0.316	Von(rms)			=		1					n						1
	V							(											)			V								(											)
		op		16		16				16							1						op			n			n			n								1
Vstate 2 (t) = C2(t)							R2(t):														Voff(rms)			=		2 (			n			1)
V	off(rms)		=	2 (		16				1)								= 0.254				Vop					n (				n					1) 2
	Vop			16		( 16							1) 2

Fig.8 LCD drive mode waveforms for 1 : 16 multiplex rate.

1998 Sep 08

13

Philips Semiconductors	Product specification

LCD row/column driver for dot matrix

PCF8578

graphic displays

7.5Internal clock

The clock signal for the system may be generated by the internal oscillator and prescaler. The frequency is determined by the value of the resistor ROSC, see Fig.9. For normal use a value of 330 kW is recommended.

The clock signal, for cascaded PCF8579s, is output at CLK and has a frequency 1¤6 (multiplex rate 1 : 8, 1 : 16 and

1 : 32) or 1¤8 (multiplex rate 1 : 24) of the oscillator frequency.

MSA837

10 3

f OSC (kHz)

102

10

1

10 102 103 104 R OSC (kΩ )

To avoid capacitive coupling, which could adversely affect oscillator stability, ROSC should be placed as closely as possible to the OSC pin. If this proves to be a problem, a filtering capacitor may be connected in parallel to ROSC.

Fig.9 Oscillator frequency as a function of external oscillator resistor, ROSC.

7.6External clock

If an external clock is used, OSC must be connected to VDD and the external clock signal to CLK. Table 4

summarizes the nominal CLK and SYNC frequencies.

7.7Timing generator

The timing generator of the PCF8578 organizes the internal data flow of the device and generates the LCD frame synchronization pulse SYNC, whose period is an integer multiple of the clock period. In cascaded applications, this signal maintains the correct timing relationship between the PCF8578 and PCF8579s in the system.

7.8Row/column drivers

Outputs R0 to R7 and C32 to C39 are fixed as row and column drivers respectively. The remaining 24 outputs R8/C8 to R31/C31 are programmable and may be configured (in blocks of 8) to be either row or column drivers. The row select signal is produced sequentially at each output from R0 up to the number defined by the multiplex rate (see Table 1). In mixed mode the remaining outputs are configured as columns. In row mode all programmable outputs (R8/C8 to R31/C31) are defined as row drivers and the outputs C32 to C39 should be left open-circuit.

Using a 1 : 16 multiplex rate, two sets of row outputs are driven, thus facilitating split-screen configurations, i.e. a row select pulse appears simultaneously at R0 and R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex rate of 1 : 8, four sets of row outputs are driven simultaneously. Driver outputs must be connected directly to the LCD. Unused outputs should be left open-circuit. In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32

R0 to R31/C31 are rows.

Table 4 Signal frequencies required for nominal 64 Hz frame frequency; note 1.

	OSCILLATOR		FRAME FREQUENCY				DIVISION	CLOCK FREQUENCY
	FREQUENCY					MULTIPLEX RATE (n)
			f		(Hz)		RATIO	fCLK (Hz)
	f	(2) (Hz)		SYNC
		OSC
		12288	64			1 : 8, 1 : 16, 1 : 32	6	2048
		12288	64			1 : 24	8	1536

Notes

1.A clock signal must always be present, otherwise the LCD may be frozen in a DC state.

2.ROSC = 330 kW.

1998 Sep 08

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