Philips PCF8574T, PCF8574TS-F3, PCF8574U-10, PCF8574U-9, PCF8574AP Datasheet

INTEGRATED CIRCUITS

DATA SHEET

PCF8574

Remote 8-bit I/O expander for I2C-bus

Product specification

1997 Apr 02

Supersedes data of September 1994

File under Integrated Circuits, IC12

Philips Semiconductors	Product specification
Remote 8-bit I/O expander for I2C-bus	PCF8574

CONTENTS

1FEATURES

2GENERAL DESCRIPTION

3ORDERING INFORMATION

4BLOCK DIAGRAM

5PINNING

6CHARACTERISTICS OF THE I2C-BUS

6.1Bit transfer

6.2Start and stop conditions

6.3System configuration

6.4Acknowledge

7	FUNCTIONAL DESCRIPTION

7.1Addressing

7.2Interrupt

7.3Quasi-bidirectional I/Os

8LIMITING VALUES

9HANDLING

10DC CHARACTERISTICS

11I2C-BUS TIMING CHARACTERISTICS

12PACKAGE OUTLINES

13SOLDERING

13.1Introduction

13.2DIP

13.2.1Soldering by dipping or by wave

13.2.2Repairing soldered joints

13.3SO and SSOP

13.3.1Reflow soldering

13.3.2Wave soldering

13.3.3Repairing soldered joints

14DEFINITIONS

15LIFE SUPPORT APPLICATIONS

16PURCHASE OF PHILIPS I2C COMPONENTS

1997 Apr 02	2

Philips Semiconductors	Product specification
Remote 8-bit I/O expander for I2C-bus	PCF8574

1 FEATURES

∙Operating supply voltage 2.5 to 6 V

∙Low standby current consumption of 10 μA maximum

∙I2C to parallel port expander

∙Open-drain interrupt output

∙8-bit remote I/O port for the I2C-bus

∙Compatible with most microcontrollers

∙Latched outputs with high current drive capability for directly driving LEDs

∙Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A)

∙DIP16, or space-saving SO16 or SSOP20 packages.

2 GENERAL DESCRIPTION

The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C).

The device consists of an 8-bit quasi-bidirectional port and an I2C-bus interface. The PCF8574 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. This means that the PCF8574 can remain a simple slave device.

The PCF8574 and PCF8574A versions differ only in their slave address as shown in Fig.9.

3 ORDERING INFORMATION

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	PCF8574P;	DIP16	plastic dual in-line package; 16 leads (300 mil)	SOT38-1
	PCF8574AP
	PCF8574T;	SO16	plastic small outline package; 16 leads; body width 7.5 mm	SOT162-1
	PCF8574AT
	PCF8574TS	SSOP20	plastic shrink small outline package; 20 leads; body width 4.4 mm	SOT266-1

1997 Apr 02

3

Philips Semiconductors	Product specification
Remote 8-bit I/O expander for I2C-bus	PCF8574
4 BLOCK DIAGRAM

handbook, full pagewidth
INT	13		INTERRUPT			LP FILTER
			LOGIC
A0	1				PCF8574
	2
A1								4
	3							P0
A2								5
								P1
	14							6
SCL			I2C					P2
		INPUT		BUS				7
	15
SDA		FILTER	CONTROL		SHIFT	8 BIT	I/O	P3
								9
					REGISTER		PORT
								P4
								10
								P5
								11
								P6
								12
								P7
					WRITE pulse
VDD	16				READ pulse
	8	POWER-ON
VSS
		RESET
								MBD980

Fig.1 Block diagram (SOT38-1 and SOT162-1).

1997 Apr 02

4

Philips Semiconductors																		Product specification
	Remote 8-bit I/O expander for I2C-bus																		PCF8574
5 PINNING
	SYMBOL				PIN								DESCRIPTION
			DIP16; SO16				SSOP20
A0					1			6			address input 0
A1					2			7			address input 1
A2					3			9			address input 2
P0					4			10			quasi-bidirectional I/O 0
P1					5			11			quasi-bidirectional I/O 1
P2					6			12			quasi-bidirectional I/O 2
P3					7			14			quasi-bidirectional I/O 3
VSS					8			15			supply ground
	P4				9			16			quasi-bidirectional I/O 4
	P5				10			17			quasi-bidirectional I/O 5
	P6				11			19			quasi-bidirectional I/O 6
	P7				12			20			quasi-bidirectional I/O 7
					13			1			interrupt output (active LOW)
	INT
	SCL				14			2			serial clock line
	SDA				15			4			serial data line
	VDD				16			5			supply voltage
	n.c.				−			3			not connected
	n.c.				−			8			not connected
	n.c.				−			13			not connected
	n.c.				−			18			not connected
													handbook, halfpage
													INT			1		20	P7
	handbook, halfpage												SCL						P6
			A0	1			16	VDD								2		19
														n.c.
																3		18	n.c.
			A1	2			15	SDA
			A2										SDA			4		17	P5
				3			14		SCL
													VDD
			P0	4	PCF8574		13		INT							5	PCF8574TS	16	P4
					PCF8574A														VSS
			P1	5			12	P7						A0		6		15
			P2					P6
				6			11							A1		7		14	P3
			P3	7			10	P5						n.c.		8		13	n.c.
		VSS
				8			9	P4						A2		9		12	P2
					MBD979									P0					P1
																10		11
																	MBD978
		Fig.2 Pin configuration (DIP16; SO16).											Fig.3 Pin configuration (SSOP20).

1997 Apr 02

5

Philips Semiconductors	Product specification
Remote 8-bit I/O expander for I2C-bus	PCF8574

6 CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

6.2Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Fig.5).

6.3System configuration

6.1Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Fig.4).

A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Fig.6).

SDA

SCL

data line		change
stable;		of data
data valid		allowed		MBC621

Fig.4 Bit transfer.

SDA

SDA

SCL

SCL

S

P

STOP condition

START condition

MBC622

Fig.5 Definition of start and stop conditions.

SDA

SCL

MASTER		SLAVE		SLAVE		MASTER		MASTER
TRANSMITTER /				TRANSMITTER /				TRANSMITTER /
		RECEIVER				TRANSMITTER
RECEIVER				RECEIVER				RECEIVER
								MBA605

Fig.6 System configuration.

1997 Apr 02

6

Philips Semiconductors	Product specification
Remote 8-bit I/O expander for I2C-bus	PCF8574

6.4Acknowledge

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave

transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

	DATA OUTPUT
	BY TRANSMITTER
				not acknowledge
	DATA OUTPUT
	BY RECEIVER
				acknowledge
	SCL FROM	1	2	8	9
	MASTER
		S
		START			clock pulse for
				MBC602	acknowledgement
		CONDITION

Fig.7 Acknowledgment on the I2C-bus.

1997 Apr 02

7

Philips Semiconductors	Product specification
Remote 8-bit I/O expander for I2C-bus	PCF8574

7	FUNCTIONAL DESCRIPTION
handbook, full pagewidth				VDD
	write pulse
				100
				μA
	data from	D	Q
	shift register
		FF
		CI		P0 to P7
		S
	power-on			VSS
	reset
			D	Q
			FF
	read pulse		CI
			S
	data to			to interrupt
				logic
	shift register
				MBD977

Fig.8 Simplified schematic diagram of each I/O.

7.1Addressing

For addressing see Figs 9, 10 and 11.

handbook, full pagewidth

slave address

slave address

S

0 1

0 0 A2 A1 A0 0

A

S

0

1 1 1 A2 A1 A0

0

A

MBD973

a.

b.

(a)PCF8574.

(b)PCF8574A.

Fig.9 PCF8574 and PCF8574A slave addresses.

Each of the PCF8574’s eight I/Os can be independently used as an input or output. Input data is transferred from the port to the microcontroller by the READ mode

(see Fig.11). Output data is transmitted to the port by the WRITE mode (see Fig.10).

1997 Apr 02

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