Philips PCF8582C-2P-03, PCF8582C-2T-03, PCF8582C-2TS, PCF8582C-2W-03-280, PCF8598C-2T Datasheet

INTEGRATED CIRCUITS

PCF85xxC-2 family

256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface

Product specification			1997 Feb 13
File under Integrated Circuits, IC12

Philips Semiconductors	Product specification

256 to 1024 × 8-bit CMOS EEPROMs with

PCF85xxC-2 family

I2C-bus interface

CONTENTS

1FEATURES

2GENERAL DESCRIPTION

3QUICK REFERENCE DATA

4ORDERING INFORMATION

5DEVICE SELECTION

6BLOCK DIAGRAM

7PINNING

7.1Pin description PCF8582C-2

7.2Pin description PCF8594C-2

7.3Pin description PCF8598C-2

8	I2C-BUS PROTOCOL

8.1Bus conditions

8.2Data transfer

8.3Device addressing

8.4Write operations

8.4.1Byte/word write

8.4.2Page write

8.4.3Remark

8.5Read operations

8.5.1Remark

9LIMITING VALUES

10CHARACTERISTICS

11I2C-BUS CHARACTERISTICS

12WRITE CYCLE LIMITS

13EXTERNAL CLOCK TIMING

14PACKAGE OUTLINES

15SOLDERING

15.1Introduction

15.2DIP

15.2.1Soldering by dipping or by wave

15.2.2Repairing soldered joints

15.3SO

15.3.1Reflow soldering

15.3.2Wave soldering

15.3.3Repairing soldered joints

16DEFINITIONS

17LIFE SUPPORT APPLICATIONS

18PURCHASE OF PHILIPS I2C COMPONENTS

1997 Feb 13

2

Philips Semiconductors

Product specification

256 to 1024 × 8-bit CMOS EEPROMs with

PCF85xxC-2 family

I2C-bus interface

1 FEATURES

∙ Low power CMOS:

–maximum operating current: 2.0 mA (PCF8582C-2)

2.5 mA (PCF8594C-2)

4.0 mA (PCF8598C-2)

–maximum standby current 10 μA (at 6.0 V), typical 4 μA

∙Non-volatile storage of:

–2 kbits organized as 256 × 8-bit (PCF8582C-2)

–4 kbits organized as 512 × 8-bit (PCF8594C-2)

–8 kbits organized as 1024 × 8-bit (PCF8598C-2)

∙Single supply with full operation down to 2.5 V

∙On-chip voltage multiplier

∙Serial input/output I2C-bus

∙Write operations:

–byte write mode

–8-byte page write mode

(minimizes total write time per byte)

∙Read operations:

–sequential read

–random read

∙Internal timer for writing (no external components)

∙Power-on-reset

∙High reliability by using a redundant storage code

∙Endurance: 1000000 Erase/Write (E/W) cycles at Tamb = 22 °C

∙10 years non-volatile data retention time

∙Pin and address compatible to: PCF8570, PCF8571, PCF8572 and PCF8581.

2 GENERAL DESCRIPTION

The PCF85xxC-2 is a family of floating gate Electrically Erasable Programmable Read Only Memories (EEPROMs) with 2, 4 and 8 kbits (256, 512 and

1024 × 8-bit). By using an internal redundant storage code it is fault tolerant to single bit errors. This feature dramatically increases the reliability compared to conventional EEPROMs. Power consumption is low due to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier.

As data bytes are received and transmitted via the serial I2C-bus, a package using eight pins is sufficient. Up to eight PCF85xxC-2 devices may be connected to the I2C-bus. Chip select is accomplished by three address inputs (A0, A1 and A2).

Timing of the E/W cycle is carried out internally, thus no external components are required. Pin 7 (PTC) must be connected to either VDD or left open-circuit. There is an option of using an external clock for timing the length of an E/W cycle.

3 QUICK REFERENCE DATA

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VDD	supply voltage		2.5	6.0	V
IDDR	supply current read	fSCL = 100 kHz
		VDD = 2.5 V	−	60	μA
		VDD = 6 V	−	200	μA
IDDW	supply current E/W	fSCL = 100 kHz
	PCF8582C-2	VDD = 2.5 V	−	0.6	mA
		VDD = 6 V	−	2.0	mA
	PCF8594C-2	VDD = 2.5 V	−	0.8	mA
		VDD = 6 V	−	2.5	mA
	PCF8598C-2	VDD = 2.5 V	−	1.0	mA
		VDD = 6 V	−	4.0	mA
IDD(stb)	standby supply current	VDD = 2.5 V	−	3.5	μA
		VDD = 6 V	−	10	μA

1997 Feb 13

3

Philips Semiconductors

Product specification

256 to 1024 × 8-bit CMOS EEPROMs with

PCF85xxC-2 family

I2C-bus interface

4

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

PCF8582C-2P

PCF8594C-2P

DIP8

plastic dual in-line package; 8 leads (300 mil)

SOT97-1

PCF8598C-2P

PCF8582C-2T

SO8

plastic small outline package; 8 leads (straight); body width 3.9 mm

SOT96-1

PCF8594C-2T

PCF8598C-2T

SO8

plastic small outline package; 8 leads; body width 7.5 mm

SOT176-1

5

DEVICE SELECTION

Table 1 Device selection code

SELECTION

DEVICE CODE

CHIP ENABLE

R/W

Bit

b7(1)

b6

b5

b4

b3

b2

b1

b0

Device

1

0

1

0

A2

A1

A0

R/W

Note

1. The Most Significant Bit (MSB) ‘b7’ is sent first.

1997 Feb 13

4

13 Feb1997

DIAGRAM BLOCK 6

I

bit-8 × 1024 to 256

SemiconductorsPhilips

2

VDD

interface bus-C

8

SCL

6

INPUT

I2C-BUS CONTROL LOGIC

5

SDA

FILTER

n

BYTE

ADDRESS

SEQUENCER

DIVIDER

CMOS

HIGH

COUNTER

(

128)

REGISTER

EEPROMs

3

ADDRESS

SHIFT

BYTE

ADDRESS

4

EE

SWITCH

REGISTER

LATCH

POINTER

8

EEPROM

CONTROL

(8 bytes)

5

with

A2

3

TIMER

7

2

A1

TEST MODE DECODER

(

16)

PTC

1

A0

POWER-ON-RESET

PCF85xxC-2

OSCILLATOR

4

family 2-PCF85xxC

MGD927

VSS

The pin numbers in this block diagram refer to the PCF8582C-2.

full pagewidth

specification Product

handbook,

For PCF8594C-2 and PCF8598C-2 please see Chapter 7.

Fig.1 Block diagram.

Philips Semiconductors

Product specification

256 to 1024 × 8-bit CMOS EEPROMs with

PCF85xxC-2 family

I2C-bus interface

7 PINNING

7.1Pin description PCF8582C-2

SYMBOL	PIN	DESCRIPTION
A0	1	address input 0
A1	2	address input 1
A2	3	address input 2
VSS	4	negative supply voltage
SDA	5	serial data input/output (I2C-bus)
SCL	6	serial clock input (I2C-bus)
PTC	7	programming time control output
VDD	8	positive supply voltage

7.2Pin description PCF8594C-2

SYMBOL	PIN	DESCRIPTION
WP	1	write-protection input
A1	2	address input 1
A2	3	address input 2
VSS	4	negative supply voltage
SDA	5	serial data input/output (I2C-bus)
SCL	6	serial clock input (I2C-bus)
PTC	7	programming time control output
VDD	8	positive supply voltage

7.3Pin description PCF8598C-2

SYMBOL	PIN	DESCRIPTION
WP	1	write-protection input
n.c.	2	not connected
A2	3	address input 2
VSS	4	negative supply voltage
SDA	5	serial data input/output (I2C-bus)
SCL	6	serial clock input (I2C-bus)
PTC	7	programming time control output
VDD	8	positive supply voltage

handbook, halfpage						VDD
A0	1				8
						PTC
A1	2	PCF8582C-2			7
A2						SCL
	3				6
VSS
	4				5	SDA
			MGD928

Fig.2 Pin configuration PCF8582C-2.

						VDD
WP	1				8
						PTC
A1	2	PCF8594C-2			7
A2						SCL
	3				6
VSS
	4				5	SDA
			MGL001

Fig.3 Pin configuration PCF8594C-2.

handbook, halfpage

WP	1			8		VDD
						PTC
n.c.	2		7
A2			PCF8598C-2			SCL
	3			6
VSS
	4		5			SDA
			MGL002

Fig.4 Pin configuration PCF8598C-2.

1997 Feb 13

6

Philips Semiconductors

Product specification

256 to 1024 × 8-bit CMOS EEPROMs with

PCF85xxC-2 family

I2C-bus interface

8 I2C-BUS PROTOCOL

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The serial bus consists of two bidirectional lines: one for data signals (SDA), and one for clock signals (SCL).

Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

∙Data transfer may be initiated only when the bus is not busy.

∙During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals.

8.1Bus conditions

The following bus conditions have been defined:

∙Bus not busy: both data and clock lines remain HIGH.

∙Start data transfer: a change in the state of the data line, from HIGH-to-LOW, while the clock is HIGH, defines the START condition.

∙Stop data transfer: a change in the state of the data line, from LOW-to-HIGH, while the clock is HIGH, defines the STOP condition.

∙Data valid: the state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.

8.2Data transfer

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes, transferred between the START and STOP conditions is limited to 7 bytes in the E/W mode and

8 bytes in the page E/W mode.

Data transfer is unlimited in the read mode.

The information is transmitted in bytes and each receiver acknowledges with a ninth bit.

Within the I2C-bus specifications a low-speed mode (2 kHz clock rate) and a high speed mode (100 kHz clock rate) are defined. The PCF85xxC-2 operates in both modes.

By definition a device that sends a signal is called a ‘transmitter’, and the device which receives the signal is called a ‘receiver’. The device which controls the signal is called the ‘master’. The devices that are controlled by the master are called ‘slaves’.

Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level, put on the bus by the transmitter. The master generates an extra acknowledge related clock pulse. The slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte.

The master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse.

Set-up and hold times must be taken into account.

A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master generation of the STOP condition.

1997 Feb 13

7

Philips Semiconductors

Product specification

256 to 1024 × 8-bit CMOS EEPROMs with

PCF85xxC-2 family

I2C-bus interface

8.3Device addressing

Following a START condition the bus master must output the address of the slave it is accessing. The 4 MSBs of the slave address are the device type identifier (see Fig.5).

For the PCF85xxC-2 this is fixed to ‘1010’.

The next three significant bits address a particular device or memory page (page = 256 bytes of memory). A system could have up to eight PCF8582C-2 (or four PCF8594C-2 containing two memory pages each or two PCF8598C-2 containing four memory pages each, respectively) devices on the bus. The eight addresses are defined by the state of the A0, A1 and A2 inputs.

The last bit of the slave address defines the operation to be performed. When set to logic 1 a read operation is selected.

Address bits must be connected to either VDD or VSS.

handbook, halfpage	1	0	1	0	A2	A1	A0
								R/W
							MBC793

Fig.5 Slave address.

8.4Write operations

8.4.1BYTE/WORD WRITE

For a write operation the PCF85xxC-2 requires a second address field. This address field is a word address providing access to the 256 words of memory. Upon receipt of the word address the PCF85xxC-2 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. Word address is automatically incremented. The master can now terminate the transfer by generating a STOP condition or transmit up to six more bytes of data and then terminate by generating a STOP condition.

After this STOP condition the E/W cycle starts and the bus is free for another transmission. Its duration is 10 ms per byte.

During the E/W cycle the slave receiver does not send an acknowledge bit if addressed via the I2C-bus.

8.4.2PAGE WRITE

The PCF85xxC-2 is capable of an eight-byte page write operation. It is initiated in the same manner as the byte write operation. The master can transmit eight data bytes within one transmission. After receipt of each byte the PCF85xxC-2 will respond with an acknowledge.

The typical E/W time in this mode is 9 × 3.5 ms = 31.5 ms. Erasing a block of 8 bytes in page mode takes typical 3.5 ms and sequential writing of these 8 bytes another typical 28 ms.

After the receipt of each data byte the three low order bits of the word address are internally incremented. The high order five bits of the address remain unchanged. The slave acknowledges the reception of each data byte with an ACK. The I2C-bus data transfer is terminated by the master after the 8th byte with a STOP condition. If the master transmits more than eight bytes prior to generating the STOP condition, no acknowledge will be given on the ninth (and following) data bytes and the whole transmission will be ignored and no programming will be done. As in the byte write operation, all inputs are disabled until completion of the internal write cycles.

8.4.3REMARK

A write to the EEPROM is always performed if the pin WP is LOW (not on PCF8582C-2). If WP is HIGH, then the upper half of the EEPROM is write-protected and no acknowledge will be given by the PCF85xxC-2 when one of the upper 256 EEPROM bytes (PCF8594C-2) or

512 EEPROM bytes (PCF8598C-2) is addressed. However, an acknowledge will be given after the slave address and the word address.

1997 Feb 13

8