INTEGRATED CIRCUITS
PCF85116-3
2048 × 8-bit CMOS EEPROM with I2C-bus interface
Product specification |
1997 Apr 02 |
Supersedes data of 1997 Feb 24
File under Integrated Circuits, IC12
Philips Semiconductors |
Product specification |
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2048 × 8-bit CMOS EEPROM with I2C-bus
PCF85116-3
interface
CONTENTS
1FEATURES
2DESCRIPTION
2.1Remark
3QUICK REFERENCE DATA
4ORDERING INFORMATION
5DEVICE SELECTION
6BLOCK DIAGRAM
7PINNING
8I2C-BUS PROTOCOL
8.1Bus conditions
8.2Data transfer
8.3Device addressing
8.4Write operations
8.4.1Byte/word write
8.4.2Page Write
8.4.3Remark
8.5Read operations
8.5.1Remark
9LIMITING VALUES
10CHARACTERISTICS
11I2C-BUS CHARACTERISTICS
12WRITE CYCLE LIMITS
13PACKAGE OUTLINES
14SOLDERING
14.1Introduction
14.2DIP
14.2.1Soldering by dipping or by wave
14.2.2Repairing soldered joints
14.3SO
14.3.1Reflow soldering
14.3.2Wave soldering
14.3.3Repairing soldered joints
15DEFINITIONS
16LIFE SUPPORT APPLICATIONS
17PURCHASE OF PHILIPS I2C COMPONENTS
1997 Apr 02 |
2 |
Philips Semiconductors |
Product specification |
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2048 × 8-bit CMOS EEPROM with I2C-bus
PCF85116-3
interface
1 FEATURES
∙Low power CMOS:
–maximum operating current 1.0 mA
–maximum standby current 10 μA (at 5.5 V), typical 4 μA
∙Non-volatile storage of 16 kbits organized as eight blocks of 256 × 8-bit each
∙Single supply with full operation down to 2.7 V
∙On-chip voltage multiplier
∙Serial input/output I2C-bus (100 kbits/s standard-mode and 400 kbits/s fast-mode)
∙Write operations: multi byte write mode up to 32 bytes
∙Write-protection input
∙Read operations:
–sequential read
–random read
∙Internal timer for writing (no external components)
∙Power-on-reset
∙High reliability by using redundant EEPROM cells
∙Endurance: 1000000 Erase/Write (E/W) cycles at Tamb = 22 °C
∙20 years non-volatile data retention time (minimum)
∙Pin and address compatible to the PCx85xxC-2 family (see also Section 2.1)
∙2 kV ESD protection (Human Body model).
3 QUICK REFERENCE DATA
2 DESCRIPTION
The PCF85116-3 is an 16 kbits (2048 × 8-bit) floating gate Electrically Erasable Programmable Read Only Memory (EEPROM). By using redundant EEPROM cells it is fault tolerant to single bit errors. In most cases multi bit errors are also covered. This feature dramatically increases reliability compared to conventional EEPROM memories. Power consumption is low due to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier.
As data bytes are received and transmitted via the serial I2C-bus, a package using eight pins is sufficient. Only one PCF85116-3 device is required to support all eight blocks of 256 × 8-bit each.
Timing of the E/W cycle is carried out internally, thus no external components are required. A write-protection input at pin 7 (WP) allows disabling of write-commands from the master by a hardware signal. When pin 7 is HIGH the data bytes received will not be acknowledged by the PCF85116-3 and the EEPROM contents are not changed.
2.1Remark
The PCF85116-3 is pin and address compatible to the PCx85xxC-2 family. The PCF85116-3 covers the whole address space of 16 kbits; address inputs are no longer needed. Therefore, pins 1 to 3 are not connected.
The write-protection input is at pin 7.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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VDD |
supply voltage |
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2.7 |
5.5 |
V |
IDDR |
supply current read |
fSCL = 400 kHz; VDD = 5.5 V |
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1.0 |
mA |
IDDW |
supply current E/W |
fSCL = 400 kHz; VDD = 5.5 V |
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1.0 |
mA |
Istb |
standby supply current |
VDD = 2.7 V |
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6 |
μA |
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VDD = 5.5 V |
− |
10 |
μA |
1997 Apr 02 |
3 |
Philips Semiconductors |
Product specification |
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2048 × 8-bit CMOS EEPROM with I2C-bus
PCF85116-3
interface
4 |
ORDERING INFORMATION |
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TYPE |
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PACKAGE |
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NUMBER |
NAME |
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DESCRIPTION |
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VERSION |
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PCF85116-3P |
DIP8 |
plastic dual in-line package; 8 leads (300 mil) |
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SOT97-1 |
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PCF85116-3T |
SO8 |
plastic small outline package; 8 leads; body width 3.9 mm |
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SOT96-1 |
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5 |
DEVICE SELECTION |
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Table 1 Device selection code |
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SELECTION |
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DEVICE CODE |
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CHIP ENABLE |
R/W |
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Bit |
b7(1) |
b6 |
b5 |
b4 |
b3 |
b2 |
b1 |
b0 |
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Device |
1 |
0 |
1 |
0 |
MEM SEL |
MEM SEL |
MEM SEL |
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R/W |
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Note
1. The Most Significant Bit (MSB) ‘b7’ is sent first.
1997 Apr 02 |
4 |
Philips Semiconductors |
Product specification |
2048 × 8-bit CMOS EEPROM with I2C-bus
PCF85116-3
interface
6 BLOCK DIAGRAM
WP |
7 |
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SEQUENCER |
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DIVIDER |
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OSCILLATOR |
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MBH922 |
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ADDRESS |
POINTER |
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GENERATOR |
6 |
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BUSCONTROL LOGIC |
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SHIFT |
REGISTER |
5 |
HV |
ROW |
DEC |
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Block diagram. |
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I |
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ADDRESS |
COMPARATOR |
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DECODERCOLUMN |
REGISTERPAGE |
EEPROMARRAY |
256(8× × 8) |
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Fig.1 |
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- C |
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2 |
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V |
8 |
6 |
INPUT 5 |
n |
TEST MODE |
REGISTER |
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PCF85116-3 |
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POWER-ON-RESET |
4 |
V |
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FILTER |
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SS |
DD |
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SCL |
SDA |
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1997 Apr 02 |
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5 |
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Philips Semiconductors |
Product specification |
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2048 × 8-bit CMOS EEPROM with I2C-bus
PCF85116-3
interface
7 PINNING
SYMBOL |
PIN |
DESCRIPTION |
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n.c. |
1 |
not connected |
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n.c. |
2 |
not connected |
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n.c. |
3 |
not connected |
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VSS |
4 |
negative supply voltage |
SDA |
5 |
serial data input/output (I2C-bus) |
SCL |
6 |
serial clock input (I2C-bus) |
WP |
7 |
write-protection input |
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VDD |
8 |
positive supply voltage |
8 I2C-BUS PROTOCOL
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The serial bus consists of two bidirectional lines: one for data signals (SDA), and one for clock signals (SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
∙Data transfer may be initiated only when the bus is not busy
∙During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals.
8.1Bus conditions
The following bus conditions have been defined:
∙Bus not busy: both data and clock lines remain HIGH.
∙Start data transfer: a change in the state of the data line, from HIGH-to-LOW, while the clock is HIGH, defines the START condition
∙Stop data transfer: a change in the state of the data line, from LOW-to-HIGH, while the clock is HIGH, defines the STOP condition
∙Data valid: the state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.
8.2Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP condition; the number of the data bytes, transferred between the START and STOP conditions is limited to 32 bytes in the E/W mode.
handbook, halfpage
n.c. |
1 |
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8 |
VDD |
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n.c. |
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WP |
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2 |
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7 |
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PCF85116-3 |
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n.c. |
3 |
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6 |
SCL |
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VSS |
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4 |
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5 |
SDA |
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MBH923 |
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Fig.2 Pin configuration.
Data transfer is unlimited in the read mode.
The information is transmitted in bytes and each receiver acknowledges with a ninth bit.
Within the I2C-bus specifications a low-speed mode (2 kHz clock rate), a high speed mode (100 kHz clock rate) and a fast speed mode (400 kHz clock rate) are defined.
The PCF85116-3 operates in all three modes.
By definition a device that sends a signal is called a ‘transmitter’, and the device which receives the signal is called a ‘receiver’. The device which controls the signal is called the ‘master’. The devices that are controlled by the master are called ‘slaves’.
Each byte is followed by one acknowledge bit.
This acknowledge bit is a HIGH level, put on the bus by the transmitter. The master generates an extra acknowledge related clock pulse. The slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte.
The master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse.
Set-up and hold times must be taken into account.
A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master generation of the STOP condition.
1997 Apr 02 |
6 |
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